MB86060PMCR-G-BNDE1_技术文档

Datasheet

February 2009

Version 2.0

MB86060

FME/MS/SFDAC1/DS/4250

16-bit Interpolating Digital to Analog Converter

The Fujitsu MB86060 is a high performance 12-bit, 400MSa/s

digital to analog converter (DAC) enhanced with a 16-bit

PLASTIC PACKAGE

LQFP-80

interpolation filtering front-end. Use of novel techniques for the

converter architecture delivers high speed operation consistent

with BiCMOS or bipolar devices but at the low power of CMOS.

Fujitsu’s proprietary architecture is the subject of several patent

applications. Additional versatility is provided by selectable

input interpolation filters, programmable dither and noise

shaping facilities. Excellent SFDR performance coupled with

high speed conversion rate and low power make this device

particularly suitable for high performance communication

systems, in particular direct IF synthesis applications.

This device is a pin and functional replacement for,

• MB86060PFV-G-BND-FG (RoHS-5)

• MB86060PFV-G-BNDE1 (RoHS-6)

PIN ASSIGNMENT

FEATURES

• 16-bit Interpolating Digital to Analog conversion

• x2 or x4 interpolation filtering

• 100MSa/s input, with x4 interpolation enabled

• Programmable highpass filtered dither

• Selectable 2nd order noise shaping

DITH0

DITH1

DITH2

VSS

VDD

TWOC

MUL0

MUL1

MUL2

VSS

VDD

CKOUT

CKOUTB

VSS

N/C

VSS

VDD

DSUB

OVER

ASUB

FILTS

VDD

• Versatile CMOS digital interface

• Internal programmable clock multiplier

• Low power, 3.3V operation (345mW @32MSa/s input, x4)

• Performance enhanced pinout with on-chip decoupling

• 0.35µm CMOS technology with Triple Well

• Industrial temperature range (-40°C to +85°C)

DSUB

LOCK

CSUB

NSHAPE

CLKSEL

RESETB

CVDD

CVSS

CLK

MB86060

FILTF

SHUF0

SHUF1

RVSS

BGAP

VREF

CVSS

CLKB

RREF

Pin #1

APPLICATIONS

• Direct IF Synthesis

• Cellular basestations

• Wide-band communication systems

This product has Patents applied for in the US and elsewhere including GB2333191A, EP0935345A, JP11-274934A, GB2333171A, EP0930717A, JP11-

274935A, GB2333190A, EP0929158A, JP11-243339A, GB2335097A, EP0940923A, JP11-317667A, GB2335076A, EP0940852A, JP11-251530A.

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Page 1 of 44

Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

Contents

1

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2.1 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2.2 Clock Multiplier Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2.3 Multiple Device Clock Synchronisation. . . . . . . . . . . . . . . . . 8

1.2.4 Clock Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3 Interpolating Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 Programmable Dither. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.6 Converter Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.6.1 Segment Shuffling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.6.2 Converter Overload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.7 Voltage Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.8 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.8.1 Analog Output Reference Resistor . . . . . . . . . . . . . . . . . . . 12

1.8.2 Analog Output Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.8.3 Analog Output Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.9 Digital Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.9.1 Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.10 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.10.1 Substrate Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.10.2 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.10.3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2

3

4

Interpolating Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Dither Frequency Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1 Power & Ground Plane Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3 Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4 Input Data Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.6 Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.7 Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.8 Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Page 2 of 44

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ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

5

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2 Digital Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.4 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.5 Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.6 Typical Performance Characterisation Graphs . . . . . . . . . . . . . . . . 36

6

7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.2 Pin Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.3 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.3.1 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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Page 3 of 44

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ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

1

Functional Description

The MB86060 integrates a 12-bit 400MSa/s DAC core with selectable front end processing to provide

input interpolation filtering, dither and noise shaping. Versatile interfacing via the 16-bit parallel

CMOS data input allows different system requirements to be accommodated, with either offset binary

or 2’s complement data formats selected by an input format control pin.

The device is manufactured in a 0.35µm advanced CMOS process with Triple Well extension giving

improved isolation between analog blocks and digital-analog.

A functional block diagram is shown in Figure 1.

Clk Select

CLK in (diff.)

Crystal

Clock

Multiplier

2

Dither

Programmable

Dithermay be

excluded from

final MP

Lock

Mult mode

Delay line ctrl

Generator

3

2

devices

HP Filter

Data CLK out

(diff.)

Clock Divider

3

Dither

[x2 slow]

[x2 fast]

x2

NS Enable

16

Noise

Shaper

Data In

x2

Data Format

Over

12

DAC

Output

2

DAC

Bandgap

Reference

Filter control

Reset

2

Shuffle

Control

FML Mixed Signal

Figure 1 MB86060 Functional Block Diagram

1.1 Operating Modes

The device can be configured into a number of different operating modes, depending on which clock

source and interpolation filtering mode is selected. The following sections summarise the MB86060

operating modes according to clock multiplier and interpolation filtering configuration.

The MB86060 has two Interpolation filters, that may be operated in any of the following four modes.

• x1 - Interpolating filters disabled, effectively a conventional 12-bit DAC for up to 200MSa/s

• x2 slow - First interpolating filter only, used for generating 0~43MHz, assuming 100MSa/s data

• x2 fast - Second interpolating filter only, used for generating 0~74MHz, assuming 200MSa/s data

• x4 - Full interpolation, for generating 0~43MHz with 100MSa/s data & maximum DAC rate

Page 4 of 44

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ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

1.2 Clock

The MB86060 incorporates a clock multiplier. This may be used to generate the internal x1, x2 and

x4 clock signals required to clock the DAC core when the interpolation filters are enabled, or as a

general purpose clock multiplier to allow lower frequency clock sources to be used.

The clock multiplier is based on a delay-lock-loop whose delay is adjusted by a charge pump

controlled by a phase detector. A ‘Lock’ indicator pin is provided so that the system can monitor the

multiplier’s condition.

For systems where a high frequency clock is available, or the lowest possible jitter is required, the

clock multiplier should be disabled and an external clock applied directly as the clock multipliers

systematic jitter will cause jitter spurs to appear in the analog output

1.2.1

Input Clock

The input clock is selectable between either a differential system clock, typically a sine wave source

of amplitude 0dBm, or an external crystal using the internal oscillator circuit. A CMOS single ended

clock can also be connected to XIN. See Table 1 for details of these configurations.

Table 1: Input Clock Source Selection

Clock multiplier

mode

Clock

source

CLKSEL

Function

0

x1 (either filter)

or x2 to x8

Crystal

oscillator

Connect crystal between XIN and XOUT, or

connect CMOS clock to XIN

1

Any

Differential Connect differential clock source to CLK and

clock CLKB

When using the internal oscillator with an external crystal, or connecting a single-ended

CMOS clock to XIN, the clock multiplier must be set to multiply modes x2 to x8 so that XIN

is enabled. The operating speed of the internal crystal oscillator circuit is limited. See

section 5.5.

The differential input clock pins CLK and CLKB are internally biased to have a common mode level

equivalent to the voltage applied to pin VREF. When using either the internal oscillator or an external

single ended clock connected to XIN, pins CLK and CLKB should be linked to CVSS.

If minimum jitter is required, then the differential clock should be used, with an amplitude sufficient to

ensure that the specification for minimum slew rate is met. For a 250MHz clock this represents 0dBm,

with higher amplitudes required for lower clock rates. A sine signal is recommended over a square

wave to avoid unwanted harmonics.

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ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

t_sl

t_hi

CLK In

Data CLK

XIN

t_del

t_lo

t_delx

Figure 2 CLK In and Data CLK Timing

1.2.2

Clock Multiplier Modes

The clock multiplier can be set in one of eight modes. These take the form of two basic groups, either

multiplier functioning or bypassed.

Multiplier Bypassed

With the multiplier in bypass mode, MUL[2:0] = 000, then the clock frequency applied at CLK In, (F ),

IN

will be the update frequency used by the DAC core, (F

). The frequency available at Data CLK,

DAC

(F

), will be dependant on the interpolation filter settings. If no filters are selected, then F

=

DATA

F

. If the x2 filter, slow or fast, is selected, then F

= F

/2. If x4 filtering is selected, then

DAC

DATA

DAC

= F

/4. See Table 2.

DATA

DAC

Multiplier Enabled

With the multiplier enabled (modes x1 to x8, MUL[2:0] = 001 to 111), then the clock frequency at CLK

In (F ) will be applied to the input of the clock multiplier (F ), and multiplied by the chosen clock

IN

MULIN

multiplier setting. This will be the frequency available at Data CLK out, (F

). The update

DATA

frequency used by the DAC core, (F

) will then depend on the interpolation filter settings. If no

DAC

filters are selected, F

= F

. If the x2 filter, slow or fast, is selected, then F

= 2.F

. If x4

DAC

DATA

DAC

DATA

filtering is selected, then F

= 4.F

. Hence the DAC core sampling rate will be between 1.F

DAC

DATA IN

and 32.F . See Table 2.

IN

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

Table 2: Multiplier and Filter Mode to DAC Update Frequency Cross Reference Matrix

Multiplier Mode

Filter

Mode

Bypass

x1

x2

x3

x4

x5

x6

x8

F_DAC= F_IN

F_DAC= F_INF_DAC= 2.F_INF_DAC= 3.F_INF_DAC= 4.F_INF_DAC= 5.F_INF_DAC= 6.F_INF_DAC= 8.F_IN

x1

x2

x4

F_DATA= F_DACF_DATA= F_INF_DATA= 2.F_INF_DATA= 3.F_INF_DATA= 4.F_INF_DATA= 5.F_INF_DATA= 6.F_INF_DATA= 8.F_IN

F_DAC= F_INF_DAC= 2.F_INF_DAC= 4.F_INF_DAC= 6.F_INF_DAC= 8.F_INF_DAC= 10.F_INF_DAC= 12.F_INF_DAC= 16.F_IN

F_DATA= F_DAC/2 F_DATA= F_INF_DATA= 2.F_INF_DATA= 3.F_INF_DATA= 4.F_INF_DATA= 5.F_INF_DATA= 6.F_INF_DATA= 8.F_IN

F_DAC= F_INF_DAC= 4.F_INF_DAC= 4.F_INF_DAC= 12.F_INF_DAC= 16.F_INF_DAC= 20.F_INF_DAC= 24.F_INF_DAC= 32.F_IN

F_DATA= F_DAC/4 F_DATA= F_INF_DATA= 2.F_INF_DATA= 3.F_INF_DATA= 4.F_INF_DATA= 5.F_INF_DATA= 6.F_INF_DATA= 8.F_IN

F

and F

must not exceed limits set in Section 5.5. When the clock multiplier is

DATA

DAC

enabled (modes x1 to x8), F (F

) must be within the operational input range of the

IN

MULIN

clock multiplier. See Section 5.5.

Table 3: Clock Multiplier Configuration

MUL[2:0]

Clock Multiplier Mode

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Bypass

x1

x2

†

x3

x4

†

x5

x6

x8

† Clock Multiplier modes x3 and x5 are implemented with a multiply by 6 and divide by 2,

and a multiply by 10 and divide by 2, respectively. Ensure that OSC[1:0] is set for the clock

frequency produced by the x6 or x10 multiplication. F

multiplication frequency.

(max) will apply to the

DAC

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

The OSC[1:0] setting controls the delay response within the delay-lock-loop. Different settings are

required to enable best jitter performance to be achieved and should be set according to the DAC

clock rate being used.

Table 4: Clock Multiplier Oscillator Configuration

DAC Update Frequency (F

)

OSC[1:0]

DAC

Mode

1

0

Min.

Max.

0

1

0

1

0

1

Fastest

250 MHz

150 MHz

80 MHz

250 MHz

150 MHz

80 MHz

Slowest

1.2.3

Multiple Device Clock Synchronisation

To allow multiple devices to be used with a common clock source, a clock synchronization function

is included. This will ensure that the clock out to clock in phase relationship is maintained.

Multiplier Bypassed

With the clock multiplier bypassed, the input clock (CLK In) signal bypasses the clock multiplier block

and connects directly to the clock divider. The divider generates clock out (Data CLK) depending

upon the interpolation filter settings. The phase relationship between clock in and the divided clock

out will vary between devices because the time taken for the divider to start up from power-up will

vary, which will cause the dividers to start from different input clock edges.

Clock synchronisation can be achieved between multiple devices by applying a short FULL-RESET

condition simultaneously during the positive half cycle of CLK In. This simultaneous reset will start

the dividers in each device from a common state, hence synchronising the clock outputs upon the

next input clock edge. The reset pulse must be shorter than one half of one CLK In cycle.

As such a short pulse may be difficult to produce, the input clock may be cleanly stopped for long

enough to create a reset pulse. When the clock is restarted it is important to ensure that no glitches

occur that may falsely trigger the clock input.

Multiplier Enabled

With the clock multiplier enabled, the input clock (CLK In) signal is routed through the multiplier block

before connecting to the clock divider. The multiplier block maintains the phase relationship between

clock in and clock out by producing a re-synchronization pulse from CLK In that sets the clock divider

blocks back to a known state every CLK In cycle.

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

1.2.4

Clock Out

A differential output clock (Data CLK) signal is available to act as a reference to clock data into the

device. Data CLK is available on pins CKOUT and CKOUTB. These pins have a nominal output

resistance of 25Ω each, and are designed to drive a bridged load to reduce the effect of package

inductance. The output waveform will be a square wave.

The Data CLK output frequency (F

bus D[15:0].

) will always be matched to the sample rate of the input data

DATA

1.3 Interpolating Filters

The interpolating filters are configured as two cascaded, independently selectable low-pass stages.

The first filter being slower with sharp roll-off, and the second faster but with relaxed roll-off. It is

important to note that when the interpolation stages are not selected they are not clocked,

significantly reducing the power consumption for either x2 or x1 modes, compared to x4.

Table 5: Interpolating Filter Configuration

Filter Configuration

Reduction in Q noise

FILTF

(Fast filter)

FILTS

(Slow filter)

Noise Shaping

enabled

Mode

disabled

x1

x2 slow

x2 fast

x4

0

1

0

1

0

1

N/A

3dB

6dB

N/A

5dB

22dB

Further information on the interpolating filters, including frequency response, is given in Section 2.

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ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

1.4 Programmable Dither

Dither can be added to improve low-level performance and reduce effects due to nonlinearities within

the DAC, and reducing DNL and glitch energy. The dither has programmable amplitude, see Table

6, and is high pass filtered to fall out of the pass band.

Table 6: Programmable Dither

Dither Setting

DITH1

Dither Amplitude

DITH2

DITH0

rms

Disabled - no dither added

-33.6 dBFS (480 LSBs ) -27.0 dBFS (1458 LSBs )

peak

0

1

16

0

1

0

1

0

1

-27.6 dBFS (960 LSBs ) -21.0 dBFS (2916 LSBs )

16 16

-21.6 dBFS (1920 LSBs ) -15.0 dBFS (5832 LSBs )

16

-15.6 dBFS (3840 LSBs ) -9.0 dBFS (11664 LSBs )

16

-9.6 dBFS (7680 LSBs ) -3.0 dBFS (23328 LSBs )

16

1

0

1

Reserved for factory use only

The frequency characteristics of the added dither is illustrated in Section 3.

1.5 Noise Shaping

Second order noise shaping can be applied to interpolated data prior to being passed to the DAC

core. When enabled this provides an additional reduction in quantisation noise to that gained through

the use of interpolation filtering. For the x4 interpolation mode this improvement will be 16dB,

equivalent to 2.7 bits.

1.6 Converter Architecture

The MB86060 interpolating DAC incorporates a number of novel design aspects that are subject to

patent applications. Key to its operation are the current sources where segmented, common centroid,

interleaved techniques for the most significant bits, as well as load matching ensure good linearity

and low distortion to at least the 12-bit level. In the switch elements tracking capacitance is minimised

to improve settling, while controlled rise and fall times improve SFDR performance. Finally the digital

decoding uses a 3-dimensional addressing approach to minimise propagation delays from latch to

element.

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

1.6.1

Segment Shuffling

The DAC core incorporates a proprietary segment shuffling capability which is provided to further

improve linearity, and hence improve SFDR. This feature reduces any signal level dependent effects

on linearity as the same code can be generated by the same number of MSB cells but taken from

any quarter of the MSB segments. Segment shuffling can be selected to operate every 4, 8 or 16

updates of the DAC output using a random shuffle sequence between the four segments. Most

performance improvement will be observed when the device is used in one of the interpolating

modes. The effect of segment shuffling is to produce a spread noise spectrum, raising the overall

noise floor, but reducing the distortion. For minimum distortion when generating low frequency

signals, it is recommended that the shuffling clock rate is no more than 25MHz (F

/ Segment

DAC

Shuffling setting). See Table 7. However, low shuffle clock rates give reduced spreading out of

distortion components.

Table 7: Segment Shuffling Control

Mode

SHUF1

SHUF0

Segment Shuffling

Disabled

Note

0

1

2

3

0

1

0

1

0

1

Lowest noise

_DAC≤ 100 MSa/s

F

Random - every 4 cycles

Random - every 8 cycles

Random - every 16 cycles

100 ≤ F_DAC≤ 200 MSa/s

200 ≤ F MSa/s

DAC

1.6.2

Converter Overload

Within the front end digital processing there is no automatic protection against converter overload

except for clipping at 12-bit FSD. Warning of 12-bit overload at the input to the DAC is indicated by

a high logic level on the ‘OVER’ status pin. Conditions where care must be taken to avoid problems

due to overload would include input signal level when high levels of dither is selected, and fast edge

input data where inevitable overshoot in the digital filters occurs.

1.7 Voltage Reference

A 1.25V bandgap reference is provided on-chip, although this may be bypassed where an external

reference is to be used. To use the internal bandgap reference pins BGAP and VREF should be

linked via a 50Ω resistor, or smaller if better rejection of reference noise at low frequencies is

required. VREF should be decoupled to Reference Ground (RVSS) with a 100nF capacitor. For

maximum accuracy an external voltage reference is recommended

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February 2009 Version 2.0

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MB86060 16-bit Interpolating Digital to Analog Converter

1.8 Analog Output

The DAC output is a differential current type. A termination resistor should be used appropriate for

the maximum allowable output swing. A power down control places the analog circuitry in a low

power state, switching off the current output drive and reference circuitry. When power down mode

is selected the device enters its reset state setting the input data code to +1/2 in 2’s complement or

0 in unsigned binary. Note that neither IOUT or IOUTB can output zero current.

Table 8: Full Scale Code Representation

Unsigned Binary

2’s Complement

Code

IOUT

IOUTB Effective

Code

IOUT

IOUTB

1023

1

1023

65535

:

1111 1111 1111 1111

1

0111 1111 1111 1111

1

64

/

+2047 /

64

/

1024

2

:

1

1022

1

1022

32769 1000 0000 0000 0001

32768 1000 0000 0000 0000

32767 0111 1111 1111 1111

32766 0111 1111 1111 1110

0000 0000 0000 0001

33 /

32

/

+1 /

33 /

32

/

1024

2

1024

1023

1

1023

33

0000 0000 0000 0000

1111 1111 1111 1111

1111 1111 1111 1110

33

/

+ /

/

1024

2

1023

1022

1

1023

1022

33

32

/

- /

32

/

1024

2

1

/

33 /

:

-1 /

/

33 /

:

1024

2

1024

:

1023

1

1023

0

0000 0000 0000 0000

1

1000 0000 0000 0000

1

64

/

-2047 /

64

/

1024

2

Output values are expressed as proportions of I /4

ref

1.8.1

Analog Output Reference Resistor

From the voltage reference a control loop defines the current through an external resistor, Rref,

where the current in the reference resistor is 4 times the internal segment current, and the full scale

output current is defined as,

63

64

Vref

4 × Rref









I_OP= 63----- × -------------------- ≈ 16 I_ref









therefore,

16 × V_ref

R_ref= ---------------------

I_OP

e.g.Using a 1.25V V , to give a 20mA full scale output => R = 1kΩ

ref.

ref

Page 12 of 44

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MB86060 16-bit Interpolating Digital to Analog Converter

1.8.2

Analog Output Scaling

Power savings can be made by reducing the full scale analog output current (I ) by increasing R .

OP

ref

However, to maintain the specified performance, I

should be set to 20mA, and the digital data

OP

should be pre-scaled to achieve full scale deflection at an output current lower than full scale (I ).

OP

1.8.3

Analog Output Pins

The analog outputs, IOUT and IOUTB, are each connected to two pins to reduce output inductance.

These pins should be directly connected together on the PCB.

CLK In

t_pd

Analog Out

Figure 3 CLK In to Analog Out Timing

1.9 Digital Data Interface

16-bit data is input through pins D[15:0]. D15 is the MSB. Data may be presented in either Unsigned

Binary or 2’s Complement format, depending upon the setting of the TWOC pin. See Table 9.

Table 9: Digital Data Format Control Pin Function

TWOC

Digital Data Format

0

1

Unsigned Binary

2’s Complement

The Digital Data interface has CMOS inputs. The voltage levels of the input data must not exceed

the specifications in section 5.2. Data from a 5V source must not be presented directly to the Digital

Data Interface.

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MB86060 16-bit Interpolating Digital to Analog Converter

1.9.1

Data Timing

Data should be clocked into the device with the rising edge of the Data CLK signal. The timing

relationship between the rising edge of Data CLK and the setup and hold times for Data In, forms an

‘eye’ opening, within which data may be presented to the Digital Data Interface. If data is presented

outside of this ‘eye’, significant distortion will occur. See Figure 4.

Data CLK

t_datasu

Data In

t_datah

Figure 4 Data CLK to Data In Timing

1.10 Power Supplies

The MB86060 features separate power and ground supplies for digital data, digital control, analog,

reference and clock circuits. A low jitter supply, free from data dependent signals is required by all

power supply domains. The analog domain requires a supply with low clock and data noise.

All domains are all implemented using Fujitsu’s Triple-Well extension to the standard CMOS process

to provide the necessary electrical isolation. This isolation makes power supply sequencing un-

necessary.

1.10.1 Substrate Connections

Connections to the analog, digital interface, and clock section substrates are provided. These pins

would typically be directly connected to the main digital ground (VSS), so as to direct any noise that

has been collected by the substrates away from the analog blocks.

1.10.2 Power Dissipation

The power dissipation, P , is dependant on specific operating conditions: supply voltage (V ), full

D

DD

scale output current (I ), DAC output update rate (F

) and input data waveform. Equations for

OP

DAC

calculating power dissipation in certain conditions are given in section 5.3.

Depending on these factors, applications requiring high F frequencies and/or extended lifetime

DAC

o

at ambient temperatures > 70 C may need additional cooling.

Page 14 of 44

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MB86060 16-bit Interpolating Digital to Analog Converter

1.10.3 Pinout

The MB86060 features a performance enhanced pinout to gain the maximum performance from the

PCB. Ground connection pins are provided adjacent to clock in, clock out and analog out pins to

minimise the loop inductance of the return current path. All critical power supplies are paired on

adjacent pins to minimise the decoupling loop inductance, and small value decoupling is provided

on-chip. Discrete decoupling, typically 100nF, must be provided for each power supply pin pair. See

Section 4.

1.11 Reset

A RESETB pin is provided, which when taken low allows the device to be reset and placed in a low

power state. There is a two cycle latency requiring the device to be clocked in order to reset the

device. On power up the device must be reset before it is operational. Multiple device clock

synchronization (see section 1.2.3), and configuration changes require a device reset to be

performed.

There are two reset modes available determined by the state of the TWOC pin. If TWOC is held low

while RESETB is taken low then a PARTIAL-RESET is performed. This will reset and place in a low

power state all sections of the device except the Clock Multiplier and Voltage Reference sections. If

TWOC is held high while RESETB is taken low, a FULL-RESET is performed. This will reset and

place in a low power state all sections of the device.

Table 10: Reset Modes

TWOC

RESETB

Function

Sections Reset

All sections except Clock Multiplier and

Voltage Reference

0

1 > 0

PARTIAL-RESET

1

1 > 0

FULL-RESET

All sections

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MB86060 16-bit Interpolating Digital to Analog Converter

2

Interpolating Filters

The integration of interpolating filters provides a number of benefits to the system implementation. In

general, improved performance can be gained by using a higher DAC conversion rate effectively

providing a higher level of oversampling from the generated signal. For the designer, the problem

with this approach is generating the required high speed digital data, especially when considering

high performance wide-band designs with up to 50MHz of signal. Integrating this processing on-chip

with the DAC alleviates this problem for the designer.

Other benefits include a reduced effect due to the sinx/x roll-off due to the DAC S&H output stage,

which for a conventional DAC represents -4dB at Nyquist, compared to only -0.22dB when operating

in the x4 interpolating mode. Also the digital interpolation filters sharp cutoff and effective stop-band

attentuation improves both in and out-of-band SFDR. This is illustrated in figure 5.

Conventional DAC

-4dB

-13dB

Sinx

x

-18dB

0

50

100

200

300

400

500

F_DAT= F_DAC

MHz

* Reduced data generation rate while maintaining high DAC rate

* Integral digital interpolating filters

4x Interpolating DAC

* Relaxed analog reconstruction filter

* Reduced effect due to Sinx/x function

* Improves both In and Out-of-band SFDR

Sinx

x

-0.22dB

-4dB

0

50

100

F_DAT

200

300

400

F_DAC

500

MHz

Figure 5 Benefits of Interpolating Filters

The MB86060 features four interpolation filter modes x1, x2(slow), x2(fast) and x4. x1 is as per a

conventional DAC, and choosing between the remaining three modes would depend on the system

requirements. x2(slow) may be advantageous to a system requiring the benefits of interpolation

filtering but saving some power by not running the DAC core at full rate. x2(fast) gives access to the

wider band, slower roll-off interpolation filter allowing wider band signals to be generated compared

to the other modes, for example 74MHz (-0.1dB) for 200MSa/s data rate. x4 for the complete

interpolation filter operation. These different modes are illustrated in Figure 6.

Page 16 of 44

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MB86060 16-bit Interpolating Digital to Analog Converter

-4dB

Sinx

x

-13dB

-18dB

x1

mode

0

100

_DAT& F_DAC

200

300

400

500 MHz

F

Filter Pass Band = 0.43.F_DAT(-0.1dB)

Sinx

x

-0.9dB

X2 (slow)

mode

-13dB

0

100

300

500 MHz

F_DAT

F_DAC

Filter Pass Band = 0.37.F_DAT(-0.1dB)

Sinx

x

X2 (fast)

mode

-0.9dB

0

100

200

300

400

500 MHz

F_DAT

F_DAC

Filter Pass Band = 0.43.F_DAT(-0.1dB)

Sinx

x

x4

mode

-0.22dB

0

100

F_DAT

200

300

400

F_DAC

500 MHz

Figure 6 Interpolating Filter Modes

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MB86060 16-bit Interpolating Digital to Analog Converter

Simulated slow and fast x2 interpolation filter responses

20

x2 Slow Filter

Pass Band 0.43fs (-0.1dB)

0

Stop Band -75dBFS from 0.59fs

[note: Frequency axis normalised to

input data rate]

-20

-40

-60

-80

dB

x2 Fast Filter

Pass Band 0.74fs (-0.1dB)

Stop Band -83dBFS from 1.54fs

[note: Frequency axis normalised to

input data rate for x4 interpolation

mode. With only x2 Fast selected then

the input data rate is normalised to 2.0

Frequency]

-100

-120

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Frequency

Figure 7 Slow & Fast Filter Characteristics

Simulated overall x4 interpolation filter response

20

0

Combined Filters, x4 Mode

Pass Band 0.43fs (-0.1dB)

Stop Band -75dBFS from 0.59fs -

(excluding transition band at around

1.5fs)

-20

-40

-60

-80

dB

[note: Frequency axis normalised to

input data rate]

-100

-120

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Frequency

Figure 8 Combined Filter Characteristics

Page 18 of 44

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MB86060 16-bit Interpolating Digital to Analog Converter

CLK In

14 x CLK In cycles

D15

IOUT

Data CLK

A: x1 Interpolation Filter, Clock Multiplier Bypassed

CLK In

49 x CLK In cycles

D15

IOUT

Data CLK

B: x2 slow Interpolation Filter, Clock Multiplier Bypassed

CLK In

39 x CLK In cycles

D15

IOUT

Data CLK

C: x2 fast Interpolation Filter, Clock Multiplier Bypassed

CLK In

110 x CLK In cycles

D15

IOUT

Data CLK

D: x4 Interpolation Filter, Clock Multiplier Bypassed

Figure 9 Pipeline Delays

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3

Dither Frequency Spectrum

The use of dither in data converter applications is not uncommon, where improvements in low-level

performance and reduced effects due to nonlinearities can be achieved. For dither to be used

effectively both amplitude and frequency characteristics must be carefully considered. Obviously the

dither amplitude should be larger than the nonlinearities to be masked, but levels significantly larger

than this will ultimately limit available dynamic range for the wanted signal. Similar considerations

should be made for the frequency characteristics, which in the MB86060 the dither is highpass

filtered such that the majority of the energy is concentrated at Nyquist of the DAC output rate.

In many systems a simple calculation can be used to determine the maximum input signal level for

a given dither amplitude, and in most applications this applies. However, in multi-tone systems such

as discrete multi-tone (DMT) or multi-channel communication systems a more statistical approach

may be adopted where the probability of converter overloads occurring is considered.

The frequency characteristics of the highpass filtered dither is shown in Figure 10.

Dither highpass filter response

0

-10

-20

-30

-40

-50

-60

dB

-70

-80

-90

-100

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Frequency

Figure 10 Dither Frequency Characteristics

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MB86060 16-bit Interpolating Digital to Analog Converter

4

Application Notes

4.1 Power & Ground Plane Regions

The following guidelines are suggested to obtain the specified performance. Any departure from

these recommendations should be investigated to confirm that performance in the application is

acceptable.

The device should be used with a PCB utilizing a minimum of four layers for separate power and

ground planes, manufactured with tolerances capable of producing exact impedance tracking. When

using a four layer board critical analog signals should be routed on the external layer adjacent to the

ground plane (typically layer 1). The power and ground planes should be split to isolate digital, clock

and analog regions of the circuitry to prevent supply noise coupling from one to another. These

separated regions should only be connected together at one place, a star point located underneath

the device, which should also be used as a connection point to the PSU. These isolated regions

should only extend across the PCB as far as necessary, and avoid other sections of the application

circuit that could introduce noise. Signal regions such as the Analog Out and Clock In/Out can be

separated from the remainder of the application circuit by introducing a transformer as an isolator.

The connection to the PSU should also be arranged as a star point, with all other sections of the

application circuit joined at this point. Tracks to this point should be made as wide as possible, and

if they are located in the ground plane layer, should be positioned under static pins. No connection

to the supply tracks should be made midway. See figure 11.

DVSS

VSS

CVSS

PSU Star Point

Device Star Point

Application

Circuit

AVSS

PSU

RVSS

Figure 11 Power Supply Distribution Through Star Points

The DVDD/DVSS and VDD/VSS pins can be connected to the same region, but normally the Digital

supply and ground plane regions should be split further to isolate the Digital control and Digital data

blocks. The Digital data region will normally extend into the application circuit, and as such will be

subject to significant noise from the data source.

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MB86060 16-bit Interpolating Digital to Analog Converter

Another significant reason for splitting the digital data ground plane from the main digital ground is

that when using a remote data generator (e.g. a benchtop pattern or data generator) there is a

tendency for noise to be injected on the data ground by the equipment. This is significant because

the data rate is high, the data bus is wide, and it’s correlation with the signal can cause spurious tones

which degrade SFDR. The coupling mechanism is from the fast-slewing data inputs via the

capacitance of the input pins/pads/protection diodes into the internal circuits. The transient currents

through these parasitics can be several hundred milliamps. For this reason, it is recommended that

this region is not connected to the device star point but to the PSU star point directly.

The data supplies are only used for the input section of the device, so noise in this region cannot

couple into the DAC core. The digital supplies connect to the digital circuits (filters, noise shaper and

ditherer) inside the DAC, including those inside the DAC core. The control inputs can use this supply

because they toggle more slowly (if at all) and aren't correlated with the data. The analog sections

(Analog, Clock and Reference) have separate supply connections as transition dependant currents

from the digital sections will cause delay modulation in the clock path, and amplitude modulation in

the analog output section.

Each supply should be decoupled, producing a low impedance shunt at high frequency. The Digital,

Analog, Clock and Reference sections can be connected directly to the device star point, but

preferably through a small inductor. If a fully split power (VDD) plane is not desired, then as a

minimum only the ground plane need be split as described. However it is very important to isolate the

I/O supply (DVDD) from all other supplies in some way, possibly feeding the supply through a low-R

resistor or ferrite bead. This will help to filter out noise.

If the data (signal) and control lines are connected to the same device (e.g. an ASIC or FPGA), then

generally this should have been designed to support separate supply and ground pins for the digital

data bus. The ground plane at the generating device (ASIC or FPGA) then becomes the star point

for the data, requiring cuts in the ground/supply planes on either side of the data bus, and looping

under the DAC. The digital data decoupling at the DAC should also be inside this loop. This gives a

"U" shaped cut in the planes with the open end at the data source (with decoupling) and the closed

end at the DAC (with decoupling). All the data return currents will then be confined inside this "U",

and so none of them can couple into the analog ground planes to degrade SFDR. It may be advisable

to bury the digital data bus tracks on an internal layer, with data ground planes above, below and

either side of the tracks (the ground layers connected together with a “picket fence” row of vias) to

shield against RF radiation.

Figure 12 shows these principles applied to the ground plane of an application board. The pad on the

left represents the PSU star point, and the pad in the center represents the device star point. These

points could be realized with a via, so that the connection from the PSU out to other star points could

be made on another layer if necessary. The positioning of the plane breaks are also shown. The

breaks in the planes between each section should mark the boundary of that section. It is very

important to ensure that there are no tracks crossing these boundaries, or any splits in the planes

that tracks must cross, as this will create current loops within the plane itself.

The power supply track region is shown extending to the side of the device for reference purposes.

If the PSU region is not required, then the region should be merged with the Digital region.

Page 22 of 44

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MB86060 16-bit Interpolating Digital to Analog Converter

DATA REGION

DIGITAL REGION

PSU Star point

Pin #1

CLOCK REGION

REFERENCE REGION

ANALOG REGION

Figure 12 Recommended Ground Plane Splits

4.2 Power Supplies

Only one clean low-impedance power supply is required. Power distribution should be organized as

shown in Figure 11, with a main star point at the PSU supplying the data (DVDD/DVSS) block, with

a secondary device star point supplying the Digital, Analog, Clock and Reference blocks. If this

supply is used to supply any other circuits, they must not introduce any modulation onto the supply,

or SFDR will be degraded.

If the impedance of the supply is not low enough to prevent modulation by the currents drawn by the

data source, then a separate supply for the Data source should be used. If the Digital, Analog, Clock

and Reference block supply is still not low enough impedance to prevent power supply modulation

being introduced by the Digital block, then a further supply for the Analog block alone must be

introduced.

Bulk decoupling of 100uF or more at the power supply star point is recommended to remove any low

frequency ripple. Smaller value decoupling of around 10uF at the device star point is recommended

to apply a low impedance shunt at high frequency. High quality, very low ESR capacitors such as

solid aluminium types are recommended.

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MB86060 16-bit Interpolating Digital to Analog Converter

Power supply tracks should be kept as short and wide as possible. The ground and supply tracks

should run adjacent to each other for as far as possible, whilst avoiding all signal tracks that may

couple noise into the supply.

4.3 Decoupling

All supplies and references should be decoupled to the appropriate ground plane using surface

mount 100nF capacitors, placed as close as possible to the device. For each pair of VDD/VSS pins

it is recommended that the capacitor is located on the reverse of the PCB, immediately under the

device, with vias to the supply and ground planes as close as physically possible to the device and

capacitor. This layout minimizes the total length of track, including the plated through hole, and hence

keeps loop inductance to a minimum. An example of the recommended layout, using 0603 format

surface mount capacitors and a four layer PCB is illustrated in figure 13.

Layer 1 pads

MUL0

MUL1

MUL2

VSS

DITH0

DITH1

DITH2

VSS

VDD

CKOUT

CKOUTB

VSS

TWOC

N/C

VSS

VDD

DSUB

LOCK

CSUB

NSHAPE

CLKSEL

RESETB

CVDD

CVSS

CLK

DSUB

OVER

ASUB

FILTS

FILTF

SHUF0

SHUF1

RVSS

BGAP

VREF

RREF

CVSS

CLKB

Pin #1

Layer 4 pads

N.B. Not to scale. All vias connect to the appropriate Ground or Power plane.

Figure 13 Recommended Supply Decoupling Layout

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MB86060 16-bit Interpolating Digital to Analog Converter

4.4 Input Data Interfacing

The data input interface is a 16-bit wide CMOS bus, operating at speeds up to 200MHz. As such this

bus can radiate large amounts of RF radiation and generate substantial ground noise problems if it

is routed for any distance across the PCB. In addition to following the PCB layout guidelines in

section 4.1, it may be possible to minimise these problems by transmitting data across the PCB as

LVDS, and only converting to CMOS locally to the DAC.

LVDS is a low-voltage differential signalling format that is becoming increasingly popular for data

transmission, and as such is now well supported by the majority of programmable logic devices. It

has a signal swing of 350mV, and a common mode level of 1.25V. As the signal is transmitted as a

differential signal, immunity to noise pick-up is very high, radiation is minimal, and a direct ground

connection is not required between transmitter and receiver.

Four 4-bit LVDS to CMOS receivers (available from a number of manufacturers) could be used to

interface the MB86060’s 16-bit data interface to an LVDS bus. Many receivers have a flow through

pin-out design, with the power supply pins and CMOS data pins on one side, and the LVDS pins on

the other side of the package. This design makes PCB ground plane layout especially easy as the

data generator and DAC PCB regions can be kept some distance apart. The data generating device

ground plane can extend to just under the LVDS pins on one side of the converters package (to

maintain track impedance of 100Ω), but no further so as not to merge or connect to the DAC’s CMOS

ground plane on the other side. The CMOS data signal tracks from the converter to the DAC can now

be limited to just a few tens of millimetres. The converters 3.3V supply would be connected to the

DAC’s DVDD/DVSS supply region. See figure 14.

DVDD

D0

100Ω

D0

GND

FPGA

DVSS

LVDS to CMOS

DVSS

MB86060

System Ground

Figure 14 Using LVDS to CMOS Converters

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

4.5 Analog Output

To provide a differential analog output which is both isolated form the analog ground plane, and which

gives good common mode rejection, a two stage transformer circuit can be used. The recommended

devices are Mini-Circuits (www.minicircuits.com) ADTT1-1, 1:1 transformer, and ADTL1-4-75

transmission line transformer. The primary of the ADTL1-4-75 is connected to IOUT and IOUTB,

(terminated as shown in figure 15) and the secondary is connected to the ends of the secondary of

the ADTT1-1. The center tapping of the secondary of the ADTT1-1 will be linked to the analog ground

plane. The primary of the ADTT1-1 will be terminated as required by the application circuit. See figure

15.

For optimum performance the transformer should be positioned as close to the device as physically

possible, and should be connected to the analog output pins IOUT and IOUTB with 50Ω tracks. The

connections to the analog ground plane should be made through the same vias as the decoupling

capacitors, which are shown in figure 13 as being on the outside of the device pad pattern, so that

the track length and hence loop inductance can be kept to a minimum.

IOUT

ADTT1-1

ADTL1-4-75

50Ω

50Ω*

100Ω

AVSS

Analog out

AGND

50Ω

*

22pF

IOUTB

AGND

MB86060

* 0.1% Precision resistors

Figure 15 Analog Out Transformer Coupling

4.6 Clock Input

The reference input clock can be connected in a number of ways, depending on the clock source

used. For optimum performance the MB86060 should have ground isolation from the source by the

use of a coupling transformer.

The simplest method is to use the internal oscillator, with a crystal connected across XIN and XOUT.

A 1MΩ resistor should be connected in parallel with the crystal, and capacitors (typically 22pF,

depending on crystal used) should be connected from both XIN and XOUT to the clock ground

region. See figure 16a.

A single ended CMOS crystal oscillator can be used, connected to XIN. This source can be

connected to the clock ground region as long as there are no other devices connected to the clock

signal, i.e. the oscillator has a fan-out of one. See figure 16b.

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

If a common, system wide logic level clock source is to be used, this should be transformer coupled

to remove common mode noise and isolate the clock ground region. The recommended 1:1

impedance transformer is a Mini-Circuits, ADT1-1. The secondary will be connected to the differential

clock inputs CLK and CLKB, and terminated with a 100Ω resistor. The PCB tracks to the device

should be 50Ω tracks. The primary of the transformer will be connected between the digital clock

source and the digital clock source ground. A 100Ω source resistor is used, and the PCB tracks to

the clock source should be 100Ω. See figure 16c.

For connection to a low noise RF source, a Balun transformer should be used. The recommended

transformer is a Mini-Circuits ADTL1-4-75. The secondary terminals should be connected through a

100nF capacitor to the differential clock inputs CLK and CLKB. The clock inputs should be terminated

with a 50Ω resistor. The primary dot should be connected to the RF signal with a 50Ω PCB track, and

the other primary connection should be connected to RF ground. The primary ground may be

connected to clock ground if necessary. See figure 16d. This configuration would allow for a RF

signal level of between -6dBm and +24dBm, giving a differential signal level of up to 5V pk-pk at CLK

and CLKB.

XIN

CLKOUT

XIN

22pF

OSC

MB86060

1MΩ

XTAL

MB86060

GND

CGND

22pF

XOUT

CVSS

CGND

B: Using a dedicated CMOS oscillator

A: Using the internal crystal oscillator

100nF

CLK

ADT1-1

CLK

RF Source

100Ω

System clock

50Ω

100Ω

MB86060

CLKB

ADTL1-4-75

MB86060

CLKB

System Ground

100nF

RF Ground

C: Using a common system clock source

D: Using an RF source

Figure 16 Clock Input Configurations

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

4.7 Clock Output

The data clock output is provided as a reference to clock the data into the device. As with the analog

output and the reference input it is recommended that the data clock is isolated from the application

circuit to remove common mode noise in the digital ground plane.

The output pins CKOUT and CKOUTB are designed to drive a bridged load to reduce the effect of

package inductance, and each pin has a nominal output resistance of 25Ω.

A transformer can again be used, the recommended device being a Mini-Circuits ADT4-1WT. The

ends of the secondary should be connected to CKOUT and CKOUTB through series 75Ω resistors,

and 100Ω PCB tracks, and the centre tapping should be left not connected. The primary dot end

should be connected to the wiper of a 100Ω variable resistor to provide an adjustable bias point for

the output signal. The variable resistor should be placed across the supply and ground rails of the

application circuit, and a 100nF capacitor placed from the wiper to application ground. (If the biasing

is not required connect the primary dot to ground). The data clock is then present at the other end of

the primary. A 50Ω PCB track should be used here. See figure 17.

App. Supply

75Ω

ADT4-1WT

100nF

CKOUT

100Ω

MB86060

App. Ground

75Ω

CKOUTB

Data clock out

Figure 17 Data Clock Out Transformer Coupling

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

4.8 Signal Routing

Where signals have to be tracked as differential pairs, attention should be paid to the routing and

positioning of these tracks. Wherever possible, differential tracks should be routed parallel to each

other, and kept as close together as possible for the maximum distance possible. The total length of

each track in a differential pair should be equalised, and the same number of vias should always be

used. Where differential tracks have to diverge to connect to component pins, the distance that the

two tracks are routed separately should be equalised. See figure 18.

Where multiple routing layers are available, differential tracking should be kept on the same layer,

rather than as a stacked pair on adjacent layers. (This may introduce more noise onto one track than

the other due to each track being coupled to different ground planes). Where tracks are routed close

to other signals or noise sources, sufficient separation should be maintained so as to not introduce

significantly more distortion onto one track than the other. Particular attention should be paid to the

positioning of through board vias, which may be exposed to noise from tracking on the layers they

pass through. Switching tracking from one layer to another with vias should be avoided if possible,

but where necessary the vias should be positioned close to each other, within the same plane region

on all layers, and located so as to avoid potential sources of noise on all layers.

Careful attention should be paid to the positioning of signal tracking around plane splits. Signal tracks

must never cross a ground or power plane split, as the return current (which tends to follow the signal

track within the plane) will be forced to follow the plane split around to the star point or until it can find

another way to couple back into the plane on the other side of the split. This can create large ground

current loops within the planes that may interfere with other sections of the application.

One via closer to plane

split than other

Via moved away from plane

split and closer together

Un-equal net lengths

Near-equalised net lengths

A: Poor Differential Tracking Layout

B: Correct Differential Tracking Layout

Figure 18 Differential Tracking Examples

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

5

Electrical Specifications

5.1 Absolute Maximum Ratings

Ratings

Parameter

Notes Symbol

Units

Min.

Typ.

Max.

Supply voltage

Input Voltage

V_DD

V_IL

V_O

Ι_O

3.0

3.3

3.6

V_DD+0.5

21

V

V_ss-0.2

V_ss- 1.0

Output Voltage

Output Current

1

2

0

V

20

25

mA

^oC

Storage Temperature

T_ST

-40

+125

T_OP(min) to T_OP(max), VDD = DVDD = RVDD = AVDD = CVDD = +3.3V, VSS = DVSS = RVSS = AVSS = CVSS = 0V,

_FS= 20mA, Differential Transformer coupled output, 50Ω doubly terminated, unless otherwise specified.

I

1. IOUT & IOUTB

2. For 1 second per pin (at max.)

CAUTION

ELECTROSTATIC DISCHARGE SENSITIVE DEVICE

High electrostatic charges can accumulate in the human body

and discharge without detection. Ensure proper ESD

procedures are followed when handling this device.

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

5.2 Digital Interface Specifications

Ratings

Typ.

Parameter

Notes Symbol

Units

Min.

Max.

CMOS inputs

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Input capacitance

Setup time

V_IH

V_IL

I_IH

V_DD- 1.0

V_SS

V_DD

V_SS+ 1.0

+10

V

-10

µA

pF

ns

I_IL

-10

+10

5

t_datasu

t_datah

1.0

1.2

Hold time

CMOS outputs

High-level output voltage

Low-level output voltage

Reset timing

V_OH

V_OL

V_DD- 0.4

V_SS

V_DD

V

V_SS+ 0.4

Setup time

t_rstsu

t_rsth

1.0

1.2

1

ns

µs

Hold time

Reset delay, analog out

t_rstdel

T_OP(min) to T_OP(max), VDD = DVDD = RVDD = AVDD = CVDD = +3.3V, VSS = DVSS = RVSS = AVSS = CVSS = 0V,

_FS= 20mA, Differential Transformer coupled output, 50Ω doubly terminated, unless otherwise specified.

I

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

5.3 DC Specifications

Ratings

Typ.

Parameter

Notes

Symbol

Units

Min.

Max.

DC Accuracy

Integral Non Linearity, (Shuffle Off)

Differential Non Linearity

Analog output

INL

10

5

20

10

LSB₁₆

DNL

Full scale output current

Output resistance

1

2

Ι_OP

2

20

100

15

21

mA

kΩ

pF

%FS

V

Output capacitance

Gain error

-1

+1

Output voltage (compliance) - Maximum

Output voltage (compliance) - Best performance

CLK In to Analog Out propagation delay

Output settling time (to 0.1%)

Output rise time (10% to 90%)

Output fall time (90% to 10%)

Bandgap Reference

-0.5

+0.5

V

3

4

5

t_pd

t_st

6

4

ns

1.6

1

ns

Reference voltage

V_BG

I_BG

1.19

0

1.25

3.3

1.31

100

V

Reference output current

Reference Input

µA

Reference voltage

V_REF

I_REF

1.19

-1

1.31

+1

V

Reference input current

Power Supply

µA

VDD, DVDD, RVDD, AVDD, CVDD

3.0

3.6

V

Power Dissipation

Multiplier bypassed, shuffle and dither disabled

100MSa/s input, x1 interpolation

100MSa/s input, x2slow interpolation

100MSa/s input, x4 interpolation

Power down current

6

P_D

204

507

867

<1

mW

mA

^oC

Ambient Temperature

T_A

T_J

-40

25

+85

Junction Temperature

+110

^oC

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

T_OP(min) to T_OP(max), VDD = DVDD = RVDD = AVDD = CVDD = +3.3V, VSS = DVSS = RVSS = AVSS = CVSS = 0V,

I

_FS= 20mA, Differential Transformer coupled output, 50Ω doubly terminated, unless otherwise specified

1. Distortion increases when I_OPdecreases. Set to 20mA for optimum performance.

2. V_REF= 1.25V. See section 1.8.1

3. Propagation delay does not include the data pipeline delays. See section 2, figure 9.

4. Measured differentially. IOUT and IOUTB doubly terminated (25Ω load to AVSS).

5. Measured single-ended. IOUT and IOUTB doubly terminated (25Ω load to AVSS).

6. Nominal power dissipation

x1 mode P_D= 99 + (105 per 100MSa/s) (mW) approx.

x2 slow mode P_D= 99 + (204 per 100MSa/s) (mW) approx.

x2 fast mode P_D= 99 + (147 per 100MSa/s) (mW) approx.

x4 mode P_D= 99 + (192 per 100MSa/s) (mW) approx.

x4 mode and dither enabled P_D= 99 + (245 per 100MSa/s) (mW) approx.

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

5.4 AC Specifications

Ratings

Typ.

Parameter

Notes

Symbol

Units

Min.

Max.

Signal to Noise Ratio

Range DC to 50MHz, F_DAC= 400 MHz, x4 Interpolation mode,

1

SNR

Noise shaping enabled, Dither disabled

2MHz tone, Segment Shuffling - Off

2MHz tone, Segment Shuffling - On

90

80

dB

Total Harmonic Distortion

Range DC to 50MHz, F_DAC= 400 MHz, x4 Interpolation mode,

1

THD

Noise shaping enabled, Dither disabled

2MHz tone, Segment Shuffling - Off

2MHz tone, Segment Shuffling - On

20MHz tone, Segment Shuffling - Off

20MHz tone, Segment Shuffling - On

80

90

65

76

dB

Spurious Free Dynamic Range

Single Tone at -1dBFS, F_DAC= 200MHz, range DC to 100MHz

1

SFDR

2MHz tone, Segment Shuffling - Off

2MHz tone, Segment Shuffling - On

15MHz tone, Segment Shuffling - Off

15MHz tone, Segment Shuffling - On

83

93

70

83

dBc

65

4-tones at -15dBFS, F_DAC= 200MHz, range DC to 100MHz

19.1, 19.3, 19.7, & 19.9MHz tones, missing centre tone

Spurious tone at 19.5MHz, Segment Shuffling - Off

Spurious tone at 19.5MHz, Segment Shuffling - On

Spurious tones 17.5 - 21.5MHz, Segment Shuffling - Off

Spurious tones 17.5 - 21.5MHz, Segment Shuffling - On

88

95

89

97

dBFS

Adjacent Channel Leakage Ratio

4MHz bandwidth, 5MHz channel spacing

1

ACLR

16MHz centre frequency, 64MSa/s, F_DAC=256MSa/s

32MHz centre frequency, 128MSa/s, F_DAC=256MSa/s

80

74

dBc

T_OP(min) to T_OP(max), VDD = DVDD = RVDD = AVDD = CVDD = +3.3V, VSS = DVSS = RVSS = AVSS = CVSS = 0V,

I_FS= 20mA, Differential Transformer coupled output, 50Ω doubly terminated, unless otherwise specified

1. Clock multiplier mode = ‘000’ (bypassed)

Spurious Free Dynamic Range (SFDR) is defined as the highest spurious product (harmonic or non-harmonically related) within a defined

bandwidth while generating a test tone or tones (multi-tone test). SFDR varies with amplitude and frequency of the test tone(s) and should

either be quoted as the difference between the tone and highest spurious component (dBc) or referenced to full scale (dBFS). In both cases

the test tone amplitude and frequency should be quoted as well as the measurement bandwidth. The measurement bandwidth is typically

regarded as DC to Nyquist (of the input data rate where interpolating modes are selected) but occasionally systems will specify an

appropriate narrow band.

Adjacent Channel Power Ratio (ACPR) relates to the ratio of power in an adjacent band compared to that in a wanted transmit band, where

channel bandwidth and channel spacing should be quoted.

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

5.5 Clock Specifications

Ratings

Typ.

Parameter

Notes

Symbol

Units

Min.

Max.

Maximum DAC Conversion rate

VDD < 3.3V

1

F_DAC

350

400

380

416

MSa/s

VDD ≥ 3.3V

Clock multiplier operational range

Minimum input frequency

Maximum input frequency

Maximum input data rate, interpolation modes

x4 interpolation

F_MULIN

10

85

MHz

F_DATA

100

200

104

208

MSa/s

x2 slow interpolation

x2 fast interpolation

x1 (no interpolation)

2

Clock in

Low time

t_LO

t_HI

1

ns

High time

Slew rate for minimum wide-band jitter

Common mode input voltage

Signal level (differential)

Clock out

t_SL

0.5

V/ns

V

3

4

V_cm

V_REF

100

mV

CLK In to Data CLK delay

XIN to Data CLK delay

Crystal oscillator speed

t_del

t_delx

F_xtal

7

ns

5

7.2

40

MHz

T_OP(min) to T_OP(max), VDD = DVDD = RVDD = AVDD = CVDD = +3.3V, VSS = DVSS = RVSS = AVSS = CVSS = 0V,

_FS= 20mA, Differential Transformer coupled output, 50Ω doubly terminated, unless otherwise specified

I

1. Assumes x2 fast or x4 interpolation mode is selected

2. Limited by CMOS digital I/O speed

3. Pins CLK and CLKB are internally biased to the voltage applied to pin VREF

4. Ensure that slew rate specifications are observed

5. CMOS clock signal applied to pin XIN. Clock multiplier in x2 mode

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

5.6 Typical Performance Characterisation Graphs

95

90

85

80

75

70

65

60

Single Tone Spurious Free Dynamic Range

50MSa/s Input Data Rate

x4 Mode, 200MSa/s DAC Rate

Noise Shaper On, Dither Off

Amplitude = -1dBFS

Shuffle On

Shuffle Off

Figure 19 Single Tone SFDR Performance

0

10

20

30

40

Generated Frequency

(MHz)

0

50MSa/s Input Data Rate

Multi-tone test, 4 tones, 200kHz channel

spacing, missing centre tone

x4 Mode, 200MSa/s DAC Rate

Shuffle On & Noise Shaper On

Dither N/A

-20

4 Tones each at -14.3dBFS

-40

-60

-80

-100

-120

17

18

19

20

21

22

Generated Frequency

(MHz)

Figure 20 Multi-tone Performance

W-CDMA direct-IF channel generation

example

4MHz channel, 5MHz channel spacing

16MHz channel centre frequency

F

= 64MSa/s, x4 Interpolation

= 256MSa/s

DATA

DAC

Figure 21 W-CDMA Carrier Direct-IF Gen-

eration

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

6

Pin Description

6.1 Pin Assignment

DITH0

DITH1

DITH2

VSS

MUL0

MUL1

MUL2

VSS

VDD

CKOUT

CKOUTB

VSS

TWOC

N/C

VSS

VDD

DSUB

LOCK

CSUB

NSHAPE

CLKSEL

RESETB

CVDD

CVSS

CLK

MB86060

OVER

ASUB

FILTS

FILTF

SHUF0

SHUF1

RVSS

BGAP

VREF

RREF

CVSS

CLKB

Pin #1

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

6.2 Pin Definition

Data Interface

Input/

Output

Pin Nos.

Pin Name

Description

†

60

59

D0

D1

I

Input data bit 0 (LSB)

†

I

Input data bit 1

57

D2

I

Input data bit 2

Input data bit 3

Input data bit 4

Input data bit 5

Input data bit 6

Input data bit 7

Input data bit 8

Input data bit 9

Input data bit 10

Input data bit 11

Input data bit 12

Input data bit 13

Input data bit 14

56

D3

I

55

D4

I

54

D5

I

52

D6

I

51

D7

I

50

D8

I

49

D9

I

47

D10

D11

D12

D13

D14

D15

DVDD

DVSS

DSUB

I

46

I

45

I

44

I

42

I

41

I

Input data bit 15 (MSB)

43, 53

48, 58

31, 70

Power

Data interface supply, +3.3V. Decouple to DVSS

Data interface ground, 0V

Data interface substrate. Link to VSS

† Connect unused LSB inputs to DVSS, e.g. D0 & D1 for 14-bit source data

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February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

Digital Control Interface

Input/

Output

Pin Nos.

Pin Name

Description

61

DITH0

DITH1

DITH2

FILTS

FILTF

I

Programmable Dither control bit 0. See table 6

Programmable Dither control bit 1. See table 6

Programmable Dither control bit 2. See table 6

Slow Interpolation Filter control. See table 5

Fast Interpolation Filter control. See table 5

Noise shaper, ‘1’ = enabled. See section 1.5

Segment Shuffling control bit 0. See table 7.

Segment Shuffling control bit 1. See table 7.

Input data format selection, ‘1’ = 2’s Complement

Digital overflow warning. ‘1’ = overflow condition

Clock Select. Differential clock =’1‘, Crystal clock via XIN = ‘0’

Delay line control bit 0. Internal pull-down resistor. See table 4.

Delay line control bit 1. Internal pull-down resistor. See table 4.

Clock multiplier mode control bit 2. See table 4.

Clock multiplier mode control bit 1. See table 4

Clock multiplier mode control bit 0. See table 4

DLL locked indicator, ’1’ = locked

62

I

63

I

73

I

74

I

28

NSHAPE

SHUF0

SHUF1

TWOC

OVER

CLKSEL

OSC0

OSC1

MUL2

MUL1

MUL0

LOCK

RESETB

N/C

I

75

I

76

I

66

I

71

O

27

I

3

I

4

I

38

I

39

I

40

I

30

26

O

I

Device reset, ’0’ = reset

67

-

No connection. Do not connect

32, 36, 65, 69

33, 37, 64, 68

VDD

Power

Digital supply, +3.3V. Decouple to VSS

VSS

Digital ground, 0V

Clock Interface

Input/

Output

Pin Nos.

Pin Name

Description

21

23

CLKB

CLK

I

Differential input clock (CLK In), negative input.

Differential input clock (CLK In), positive input.

Differential data output clock (Data CLK), negative output.

Differential data output clock (Data CLK), positive output.

Crystal / clock input. Connect to CVSS when not used

Crystal oscillator circuit output

I

34

CKOUTB

CKOUT

XIN

O

35

O

17

I

O

18

XOUT

CVDD

CVSS

CSUB

19, 25

20, 22, 24

29

Power

-

Clock supply, +3.3V. Decouple to CVSS.

Clock ground, 0V

Clock substrate. Link to VSS

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ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

Analog Interface

Input/

Output

Pin Nos.

Pin Name

Description

7,8

13,14

IOUTB

IOUT

O

DAC current output, negative output. Connect together.

DAC current output, positive output. Connect together.

Analog supply, +3.3V. Decouple to AVSS.

Analog ground, 0V

5, 10, 11, 16

6, 9, 12, 15

72

AVDD

AVSS

ASUB

Power

-

Analog substrate. Link to VSS

Reference Interface

Input/

Output

Pin Nos.

Pin Name

Description

78

79

BGAP

VREF

RREF

RVDD

RVSS

O

I

Bandgap reference. See section 1.7.

Voltage reference input. See section 1.7.

Output reference resistor. See section 1.8.

Reference supply, +3.3V. Decouple to RVSS.

Reference ground, 0V

80

O

2

Power

1, 77

Page 40 of 44

Production

Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

6.3 Package Data

80-pin plastic LQFP

(FPT-80P-M21)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

14.00±0.20(.551±.008)SQ

*

12.00±0.10(.472±.004)SQ

0.145±0.055

(.006±.002)

60

41

61

40

0.08(.003)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 –⁺.^.0⁰0⁰4⁸

0.10±0.10

(.004±.004)

(Stand off)

INDEX

0˚~8˚

80

21

"A"

0.25(.010)

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

1

20

LEAD No.

0.50(.020)

0.20±0.05

(.008±.002)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2006 FUJITSU LIMITED F80035S-c-1-1

6.3.1

Thermal Characteristics

o

• θ_JA= 40.4 C/W, θ_JC= 8 C/W

Figures assume mounting on a 4-layer pcb mounted in free air.

6.4 Ordering Information

The following reference should be used when ordering devices,

• MB86060PMCR-G-BNDE1

The device is RoHS-6 compliant, qualified to Moisture Sensitivity Level (MSL) 3 and a Peak Reflow

o

temperature of 260 C.

Shipment is in plastic trays, each capable of holding 119 devices.

For further assistance please contact your sales representative.

Production

Page 41 of 44

Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

7

Development Kit

A development kit is available for the MB86060 16-bit Interpolating DAC. The kit includes an

evaluation board that enables simple and effective evaluation of the device.

The board provides a complete evaluation environment for the DAC. A transformer coupled

differential output interface is provided to simplify integration into target applications and

development environments. An RF clock source can be connected via the transformer coupled input,

and 16-bit data via a 40-way IDC header or optionally (customer modification) SMA/SMB connectors.

The development kit includes,

• Evaluation board with MB86060 device fitted

• Spare MB86060 for customer development

• User Manual

For further assistance, including price and delivery of the development kit, please contact your sales

representative.

7.1 Ordering Information

The following reference should be used when ordering the customer development kit,

• DK86060-3

Page 42 of 44

Production

Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

Notes:

Production

Page 43 of 44

Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

February 2009 Version 2.0

FME/MS/SFDAC1/DS/4250

MB86060 16-bit Interpolating Digital to Analog Converter

Worldwide Headquarters

Japan

Asia

Tel: +81 3 5322 3347

Fax: +81 3 5322 3387

Tel: +65 281 0770

Fax: +65 281 0220

Fujitsu Microelectronics Limited

Shinjuku Dai-Ichi Seimei Bldg.

7-1, Nishishinjuku 2-chome

Shinjuku-ku

Fujitsu Microelectronics Asia Pte Ltd

151 Lorong Chauan

New Tech Park

#05-08

Tokyo 163-0722

Singapore 556741

Japan

http://www.fujitsu.com/global/services/microelectronics/

http://www.fujitsu.com/sg/services/micro/semiconductor/

USA

Europe

Tel: +1 408 737 5600

Fax: +1 408 737 5999

Tel: +49 6103 6900

Fax: +49 6103 690122

Fujitsu Microelectronics America, Inc.

Fujitsu Microelectronics Europe GmbH

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94088-3470

USA

Pittlerstrasse 47

63225 Langen

Germany

Tel: +1 800 866 8608 Customer Response Center

Fax: +1 408 737 5984 Mon-Fri: 7am-5pm (PST)

http://www.fujitsu.com/us/services/edevices/microelectronics/

http://www.fujitsu.com/emea/services/microelectronics

44

The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU

MICROELECTRONICS sales representatives before ordering.

The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not

intended to be incorporated in devices for actual use. Also, FUJITSU MICROELECTRONICS is unable to assume responsibility for

infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. No license

is granted by implication or otherwise under any patent or patent rights of Fujitsu Microelectronics Europe GmbH.

FUJITSU MICROELECTRONICS semiconductor devices are intended for use in standard applications (computers, office

automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices,

etc.).

CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU MICROELECTRONICS sales representatives before such use. The company will not be

responsible for damages arising from such use without prior approval.

Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such

failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention

of over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export

of those products from Japan.

FME/MS/SFDAC1/DS/4250 2.0

Page 44 of 44

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Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.


型号：	MB86060PMCR-G-BNDE1
厂家：	FUJITSU
描述：	D/A Converter, 1 Func, Parallel, Word Input Loading, 0.004us Settling Time, PQFP80, ROHS COMPLIANT, PLASTIC, LQFP-80 转换器
文件：	总44页 (文件大小：745K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB86060PMCR-G-BNDE1 [FUJITSU]

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