MB86060 [FUJITSU]

16-Bit Interpolating Digital to Analog Converter; 16位内插数模转换器
MB86060
型号: MB86060
厂家: FUJITSU    FUJITSU
描述:

16-Bit Interpolating Digital to Analog Converter
16位内插数模转换器

转换器 数模转换器
文件: 总6页 (文件大小:108K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Product Flyer  
June 2000  
Version 1.2  
MB86060  
16-Bit Interpolating Digital to Analog Converter  
FME/MS/SFDAC1/FL_1/4270  
The Fujitsu MB86060 is a high performance 12-bit, 400MSa/s  
Digital to Analog Converter (DAC) enhanced with a 16-bit  
PLASTIC PACKAGE  
interpolation filtering front-end. Use of novel techniques for the  
converter architecture delivers high speed operation consistent  
with BiCMOS or bipolar devices but at the low power of CMOS.  
Fujitsu’s proprietary architecture is the subject of several patent  
applications. Additional versatility is provided by selectable input  
interpolation filters, programmable dither and noise shaping  
facilities. Excellent SFDR performance coupled with high speed  
conversion rate and low power make this device particularly  
suitable for high performance communication systems, in  
particular direct IF synthesis applications.  
LQFP-80  
Features  
(FPT-80P-M05)  
• 16-bit Interpolating Digital to Analog conversion  
• x1, x2 or x4 interpolation filtering  
• 100MSa/s input, with x4 interpolation enabled  
• Programmable highpass filtered dither  
• Selectable 2nd order noise shaping  
Ordering Information  
• Versatile CMOS digital interface  
• Internal programmable clock multiplier  
Order  
Number  
Part  
• Low power, 3.3V operation (343mW @32MSa/s input, x4)  
• Performance enhanced pinout with on-chip decoupling  
• 0.35µm CMOS technology with Triple Well  
• Industrial temperature range (-40°C to +85°C)  
MB86060 Datasheet  
MB86060 DAC  
Contact Sales  
MB86060PFV  
MB86060Development DK86060-3  
Kit  
Applications  
MB86060Development Contact Sales  
Kit User Manual  
• Direct IF Synthesis  
• Cellular basestations  
• Wide-band communications systems  
This product has Patents applied for in the US and elsewhere including GB2333191A, EP0935345A, JP11-274934A, GB2333171A, EP0930717A, JP11-274935A,  
GB2333190A, EP0929158A, JP11-243339A, GB2335097A, EP0940923A, JP11-317667A, GB2335076A, EP0940852A, JP11-251530A.  
Copyright © 2000 Fujitsu Microelectronics Europe GmbH  
Page 1 of 6  
June 2000 Version 1.2  
FME/MS/SFDAC1/FL_1/4270  
MB86060 16-Bit Interpolating Digital to Analog Converter  
Functional Description  
The MB86060 integrates a 12-bit 400MSa/s DAC with selectable front end processing to provide input  
interpolation filtering, dither and noise shaping. Versatile interfacing via the 16-bit parallel CMOS data input  
allows different system requirements to be accommodated, with either offset binary or 2’s complement data  
formats selected by an input format control.  
The device is manufactured in a 0.35µm advanced CMOS process with Triple Well extension giving  
improved isolation between analog blocks and digital-analog.  
Clk Select  
CLK in (diff.)  
Crystal  
Clock  
Multiplier  
2
Dither  
Programmable  
Dithermay be  
excluded from  
final MP  
Lock  
Mult mode  
Delay line ctrl  
Generator  
3
2
devices  
HP Filter  
Data CLK out  
(diff.)  
Clock Divider  
3
Dither  
[x2 slow]  
[x2 fast]  
x2  
NS Enable  
16  
16  
Noise  
Shaper  
Data In  
x2  
Data Format  
Over  
12  
DAC  
Output  
2
DAC  
Bandgap  
Reference  
Filter control  
Reset  
2
Shuffle  
Control  
FML Mixed
MB86060 Functional Block Diagram  
Converter Architecture  
The MB86060 Interpolating DAC incorporates a number of novel design aspects that are subject to patent  
applications. Key to its operation are the current sources where segmented, common centroid, interleaved  
techniques for the most significant bits, as well as load matching ensure good linearity and low distortion  
to at least the 12-bit level. In the switch elements tracking capacitance is minimised to improve settling,  
while controlled rise and fall times improve SFDR performance. Finally the digital decoding uses a 3-  
dimensional addressing approach to minimise propagation delays from latch to element.  
Page 2 of 6  
Copyright © 2000 Fujitsu Microelectronics Europe GmbH  
June 2000 Version 1.2  
FME/MS/SFDAC1/FL_1/4270  
MB86060 16-Bit Interpolating Digital to Analog Converter  
Segment Shuffling  
The DAC core incorporates a proprietary segment shuffling capability which is provided to further improve  
linearity, and hence improve SFDR. This feature reduces any signal level dependent effects on linearity as  
the same code can be generated by the same number of MSB cells but taken from any quarter of the MSB  
segments. Segment shuffling can be selected to operate every 4, 8 or 16 updates of the DAC output using  
a random shuffle sequence between the four segments. Most performance improvement will be observed  
when the device is used in one of the interpolating modes. The effect of segment shuffling is to produce a  
spread noise spectrum, raising the overall noise  
95  
floor, but reducing the distortion. For minimum  
distortion when generating low frequency  
50MSa/s Input Data Rate  
x4 Mode, 200MSa/s DAC Rate  
Noise Shaper On, Dither Off  
Amplitude = -1dBFS  
90  
85  
80  
75  
70  
65  
60  
signals, it is recommended that the shuffling  
clock rate is no more than 25MHz (DAC Rate /  
Segment Shuffling setting). However, low  
shuffle clock rates give reduced spreading out of  
distortion components.  
ShuffleOn  
ShuffleOff  
Noise Shaping  
Second order noise shaping can be applied to  
interpolated data prior to being passed to the  
DAC core. When enabled this provides an  
additional reduction in quantisation noise to that  
gained through the use of interpolation filtering.  
For the x4 interpolation mode this improvement  
will be 16dB, equivalent to 2.7 bits.  
0
10  
20  
30  
40  
Generated Frequency  
(MHz)  
Single Tone SFDR Performance  
Clock  
The MB86060 incorporates a clock multiplier to generate the required internal x1, x2 and x4 clock signals  
from an external reference. The clock multiplier is based on a delay-lock-loop whose delay is adjusted by  
a charge pump controlled by a phase detector. A ‘Lock’ indicator is provided so that the system can monitor  
the multiplier’s condition. For systems where a high frequency clock is available, or the lowest possible jitter  
is required, then the clock multiplier may be disabled and the external clock used directly.  
Interpolating Filters  
The integration of interpolating filters provides a number of benefits to the system implementation. In  
general, improved performance can be gained by using a higher DAC conversion rate effectively providing  
a higher level of oversampling from the generated signal. For the designer, the problem with this approach  
is generating the required high speed digital data, especially when considering high performance wide-  
band designs with up to 50MHz of signal. Integrating this processing on-chip with the DAC alleviates this  
problem.  
Copyright © 2000 Fujitsu Microelectronics Europe GmbH  
Page 3 of 6  
June 2000 Version 1.2  
FME/MS/SFDAC1/FL_1/4270  
MB86060 16-Bit Interpolating Digital to Analog Converter  
Other benefits include a reduced effect due to the sinx/x roll-off due to the DAC sample and hold output  
stage, which for a conventional DAC represents -4dB at Nyquist, compared to only -0.22dB when operating  
in the x4 interpolating mode. Also the digital interpolation filters sharp cutoff and effective stop-band  
attentuation improves both in and out-of-band SFDR. This is illustrated below.  
-4dB  
Sinx  
x
-13dB  
-18dB  
x1  
mode  
0
100  
DAT & FDAC  
200  
200  
300  
400  
400  
500 MHz  
F
Filter Pass Band = 0.43.FDAT (-0.1dB)  
Sinx  
x
-0.9dB  
X2 (slow)  
mode  
-13dB  
300  
0
100  
500 MHz  
F
DAT  
FDAC  
Filter Pass Band = 0.37.FDAT (-0.1dB)  
Sinx  
x
X2 (fast)  
mode  
-0.9dB  
0
100  
200  
F
DAT  
300  
400  
F
500 MHz  
DAC  
Filter Pass Band = 0.43.FDAT (-0.1dB)  
Sinx  
x
x4  
mode  
-0.22dB  
0
100  
200  
300  
400  
500 MHz  
F
DAT  
FDAC  
The MB86060 features four interpolation filter modes x1, x2(slow), x2(fast) and x4. Mode x1 is as per a  
conventional DAC, and choosing between the remaining three modes would depend on the system  
requirements. Mode x2(slow) may be advantageous to a system requiring the benefits of interpolation  
filtering but saving some power by not running the DAC core at full rate. Mode x2(fast) gives access to the  
wider band, slower roll-off interpolation filter allowing wider band signals to be generated compared to the  
other modes, for example 74MHz (-0.1dB) for 200MSa/s data rate. Mode x4 for the complete interpolation  
filter operation.  
Page 4 of 6  
Copyright © 2000 Fujitsu Microelectronics Europe GmbH  
June 2000 Version 1.2  
FME/MS/SFDAC1/FL_1/4270  
MB86060 16-Bit Interpolating Digital to Analog Converter  
20  
Interpolation Filter Response  
0
Pass Band 0.43fs (-0.1dB)  
Stop Band -75dBFS from 0.59Fs -  
(Excluding transition band image around 1.5Fs)  
-20  
-40  
[Frequency axis normalised to input data rate]  
[Simulated overall x 4 Interpolation filter response]  
dB  
-60  
-80  
-100  
-120  
Combined Filter Characteristics  
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0  
Frequency  
Programmable Dither  
Dither can be added to improve low-level performance and reduce effects due to nonlinearities within the  
DAC, and reducing DNL and glitch energy. The dither has programmable amplitude, and is high pass  
filtered to fall out of the pass band.  
For dither to be used effectively both amplitude and frequency characteristics must be carefully considered.  
Obviously the dither amplitude should be larger than the nonlinearities to be masked, but levels significantly  
larger than this will ultimately limit available dynamic range for the wanted signal. Similar considerations  
should be made for the frequency characteristics, which in the MB86060 the dither is highpass filtered such  
that the majority of the energy is concentrated at Nyquist of the DAC output rate.  
Development Kit  
A development kit, reference DK86060, is available for the MB86060 16-bit Interpolating DAC. The kit  
includes an evaluation board that enables simple and effective evaluation of the device.  
The board provides a complete evaluation environment for the DAC. A transformer coupled differential  
output interface is provided to simplify integration into  
target applications and development environments. An  
RF clock source can be connected via the transformer  
coupled input, and 16-bit data via a 40-way IDC header.  
The development kit includes,  
• Evaluation board with MB86060 device fitted  
• Spare MB86060 for customer development  
• User Manual  
Copyright © 2000 Fujitsu Microelectronics Europe GmbH  
Page 5 of 6  
June 2000 Version 1.2  
FME/MS/SFDAC1/FL_1/4270  
MB86060 16-Bit Interpolating Digital to Analog Converter  
Worldwide Headquarters  
Fujitsu Limited  
Fujitsu Microelectronics Asia  
Pte Limited  
Japan  
Asia  
Tel: +81 44 754 3753  
Tel:  
Fax:  
+65 281 0770  
+65 281 0220  
1015 Kamikodanaka 4-1-1  
Nakahara-ku  
Kawasaki-shi  
151 Lorong Chuan  
#05-08 New Tech Park  
Singapore 556741  
Fax:  
+81 44 754 3329  
Kanagawa-ken 211-88  
Japan  
http://www.fujitsu.co.jp/  
http://www.fmap.com.sg/  
Fujitsu Microelectronics Inc  
Fujitsu Microlectronics Europe  
GmbH  
USA  
Europe  
Tel: +1 408 922 9000  
Tel: +49 6103 6900  
3545 North First Street  
San Jose CA 95134-1804  
USA  
Am Siebenstein 6-10  
D-63303 Dreieich-Buchschlag  
Germany  
Fax:  
Fax:  
+1 408 922 9179  
+49 6103 690122  
Tel: +1 800 866 8608  
Fax:  
http://www.fujitsu-fme.com/  
Customer Response Center  
Mon-Fri: 7am-5pm (PST)  
+1 408 922 9179  
http://www.fujitsumicro.com/  
he contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales  
T
representatives before ordering.  
The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended  
to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or  
other rights of third parties arising from the use of this information or circuit diagrams.  
FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment,  
industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the  
use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury  
or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea  
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales  
representatives before such use. The company will not be responsible for damages arising from such use without prior approval.  
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures  
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention ofover-  
current levels and other abnormal operating conditions.  
If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign  
Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of  
those products from Japan.  
FME/MS/SFDAC1/FL_1/4270 - 1.2  
Page 6 of 6  
Copyright © 2000 Fujitsu Microelectronics Europe GmbH  

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