MB86604LPFV_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS04-22415-1E

ASSP Communication Control

CMOS

SCSI-II Protocol Controller

(with single-ended driver/receiver)

MB86604L

■ DESCRIPTION

The Fujitsu MB86604L is a single-ended transmission type SCSI-II Protocol Controller (SPC) with a single-ended

driver/receiver. The MB86604L facilitates interface control between small/medium host computer and peripheral

devices (such as a hard disk and printer). The specifications conform to the SCSI-II Standard.

The MB86604L supports high-speed synchronous transfer, the MPU/DMA independent system data bus, and

user programmable command set to enable configuration of high-performance systems.

It can also have the phase-to-phase sequence control function to reduce the program overhead of the host MPU.

The MB86604L incorporate with a single-ended type SCSI driver/receiver which can drive 48 mA of large-current,

and so, the device can be directly connected with the SCSI bus.

The device can operate with +5 V single-power supply and in up to 40 MHz clock frequency. As for package, a

100-pin plastic small quad flat package is available.

■ FEATURES

SCSI Bus Interface:

• Conforming to the SCSI-II standard

• Operatable as Initiator and target

(Continued)

■ PACKAGE

100 pin, Plastic LQFP

(FPT-100P-M05)

MB86604L

(Continued)

• Two types of high-speed data transfer:

– Synchronous data transfer (Max. 10 Mbytes/s, max. 32 offsets, 32-step transfer rate)

– Asynchronous data transfer (Max. 5 Mbyte/s)

• Transfer parameters (transfer mode, transfer rate, transfer offset) can be set for up to 7 connected devices.

• Single-ended transmission type (Maximum cable length: 6 m):

– On-chip single-ended driver/receiver which can drive 48 mA of "L" level output current

– Directly connectable with the SCSI bus

• On-chip three-state bidirectional I/O buffers for SCSI REQ and ACK pins (DB7-DB0, DBP, ATN, MSG, C/D, I/

O pins can be selected from either three-state or open-drain buffer by controlling the TEST pins input.)

Transfer Operation:

• Automatic response to selection/reselection (Preset receiving operation can perform at the selection/

reselection.):

– Initiator: Automatically operates until message received without command issue.

– Target: Automatically operates until command received without command issue.

• Automatic receiving:

– Initiator: Automatically receives information for new phase to which target transited without command issue.

– Target: Automatically receives message from initiator when initiator generates attention condition.

• On-chip 32-byte data register (FIFO) for data phase

• On-chip two (send-only and receive-only) 32-byte data buffers for message, command, and status phases

• On-chip 16-bit transfer block register and 24-bit transfer byte register enabling 1 Tbytes transfer (1 Tbytes: 16

Mbytes × 64 k blocks)

• On-chip independent data transfer bus enabling the MPU operation during the data transfer

• Parity through/generate can be specified.

System Bus Interface:

• 8-bit or 16-bit separate MPU and DMA buses

• Directly connectable with a 80 series or 68 series MPU

• Two types of transfer operation:

– Program transfer

– DMA transfer (Burst/Handshake)

Command Set:

• Supports sequential commands and programmable commands in addition to ordinary commands

• Command queuing (Command can be continuously issued by putting tags to commands in command phase.)

• On-chip 256-byte memory for command programming memory and command queuing buffer

Others

• Process: CMOS process

• Supply Voltage: Single +5 V

• Input System Clock: 20 MHz/30 MHz/40 MHz

• Package: 100-pin plastic LQFP

2

MB86604L

■ PIN ASSIGNMENT

(TOP VIEW)

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

I OWR

I ORD

BHE

UDP

D 15

D 14

D 13

D 12

D 11

D 10

D 9

D 8

V ^SS

D 7

D 6

D 5

V ^DD

V SS

DMA 0

LDMDP

DMD 0

DMD 1

DMD 2

DMD 3

DMD 4

DMD 5

DMD 6

DMD 7

V ^SS

DMD 8

DMD 9

DMD 10

DMD 11

DMD 12

DMD 13

DMD 14

DMD 15

UDMDP

DMBHE

D 4

D 3

D 2

D 1

D 0

LDP

CS 1

V ^SS

V DD

CS 0

A4

(FPT-100P-M05)

3

MB86604L

■ PIN DESCRIPTION

1. SCSI Interface

Symbol

number

Pin name

I/O

Function

60

REQ

Request

I/O Transfer request signal in the information transfer phases from

target to initiator. The input signal to this pin is used for the timing

control of data transfer sequence. This is a three-state I/O pin

and an active low pin.

68

ACK

Acknowledge

I/O This pin is for the acknowledge signal from initiator to target for

the REQ signal in the information transfer phases. The input

signal to this pin is used for the timing control of data transfer

sequence. This is a three-state I/O pin and an active low pin.

71

63

ATN

Attention

Message

I/O This pin is for the attention signal that initiator requests target for

the message transfer phase. This is an active-low pin.

MSG*

I/O This pin is for the message signal that specifies type of

information transferred on the data bus. This is an active-low pin

and becomes “L” when message phase is specified.

61

58

C/D*

I/O*

Control/data

Input/output

I/O This pin is for the control/data signal that specifies type of

information transferred on the data bus. This an active-low pin

and becomes “L” level when command, status, or message

phase is specified.

I/O This pin is for the input/output signal that specifies direction of

information transferred on the data bus. This is an active-low pin.

When this pin is “L” level, the information is transferred from

target to initiator. When this pin is “H” level, the information is

transferred from initiator to target.

69

62

67

BSY

SEL

RST

Busy

I/O This pin is for the SCSI bus busy signal. In the arbitration phase,

this is for the request signal for the use of bus acquisition. This is

an active-low pin.

Select

Reset

I/O This pin is for the select signal used by initiator to select target

during the selection phase and by target to reselect initiator

during the reselection phase. This is an active-low pin.

I/O This pin is for the reset signal used by any device on the bus.

When the device is an input operation, the reset signal is input to

this pin. When output operation, the reset signal is output from

this pin. This is an active-low pin.

11, 12, 13, DB7

17, 18, 19, to

Data bus 7

to

data bus 0

I/O These pins are for the bidirectional 8-bit SCSI data bus and 1-bit

odd parity line.

20, 22

DB0

9

DBP

Data bus

parity

* : Regarding the status of information transfer which is indicated by MSG, C/D, and I/O pins, See Table Phase Status.

4

MB86604L

Transfer direction

Initiator Target

Phase name

Data-out phase

MSG

C/D

I/O

H

L

H

L

H

L

→

←

→

←

→

←

Data-in phase

Command phase

Status phase

H

L

Message-out phase

Message-in phase

H

L

Note: The SCSI interface input/output pins can be connected to a single-end type SCSI bus.

2. MPU Interface

Symbol*

Pin name

I/O

Function

number

77

CS0

Chip select 0

I

This is a chip select 0 pin used by MPU to select the SPC as an

I/O device. This is an active-low pin.

80

CS1

Chip select 1

I

This is a chip select 1 pin to select when MPU inputs/outputs the

data on DMA bus through SPC. This is an active-low pin.

98, 97, 96, D15

95, 94, 93, to

Data 15

to

data 8

I/O These pins are for the upper byte and parity bit of MPU data bus.

When the CS0 input is valid, these pins serve as I/O ports for the

SPC internal registers. When the CS1 input is valid, these pins

serve as I/O ports for the DMA bus data.

92, 91

D8

99

UDP

Upper data

parity

89, 88, 87, D7

86, 85, 84, to

Data 7

to

data 0

I/O These pins are for the lower byte and parity bit of the MPU data

bus. When the CS0 input is valid, these pins serve as I/O ports

for the SPC internal registers. When the CS1 input is valid, these

pins serve as I/O ports for the DMA bus data.

83, 82

D0

81

LDP

Lower data

parity

76, 75, 74, A4

Address 4

to

address 0

I

These are address input pins to select the SPC internal

registers.

73, 72

to

A0

2

RD

(R/W)

Read

(read/write)

In the 80-series mode, this is a read signal input pin (IORD or

RD) that MPU reads the SPC. This read signal pin is an active-

low. In the 68-series mode, this pin functions as the control

signal input (R/W) to control the read/write operation to the SPC.

In the read operation, this pin is an active-high. In the write

operation, this pin is an active-low.

1

WR

(LDS)

Write

(lower data

strobe)

I

In the 80-series mode, this pin is a write signal input pin (IOWR

or WR) that MPU writes to the SPC. This write signal input pin is

active-low. In the 68-series mode, this pin function as the lower

data strobe signal input (LDS) that MPU outputs when the lower

byte of data bus is valid. The LDS pin is an active-low.

(Continued)

5

MB86604L

(Continued)

Symbol*

number

Pin name

I/O

Function

100

BHE

(UDS)

Bus high

enable

(strobe)

I

In the 80-series mode, this pin is used for input of the bus high

enable signal (BHE) output from the MPU when the upper byte of

the data bus is valid. The BHE pin is an active-low. In the 68-

series mode, this pin functions as the upper data strobe signal

input pin (UDS) output from the MPU when the upper byte of the

data bus is valid. The UDS pin is also an active-low.

7

8

INT

(INT)

Interrupt

request

O

I

The INT and INT pins are the interrupt request signal output. The

INT pins is used for the 80-series mode (an active-high pin), and

the INT signal is used for the 68-series mode (an active-low pin).

MODE

Mode

This input pin is used to select the type of the MPU and DMA

buses. In the 80-series mode, a high level is input. In the 68-

series mode, a low level is input.

* : The pin symbols in parenthesis are the ones when the MODE input is “L”.

3. DMA Interface

Symbol*

Pin name

I/O

Function

number

52

DREQ

DMA request

O

This is an output pin of DMA transfer request signal to the DMA

controller. The data transfer between the SPC and memory via

the DMA bus is requested. This pin is an active-high.

51

DACK

DMA

acknowledge

I

This is a DMA acknowledge signal input pin output from the

DMA controller that enables the DMA transfer. This pin is an

active-low. When this pin is an active state, the DMA cycle (read/

write) is valid.

48, 47, 46, DMD15

45, 44, 43, to

DMA data 15 I/O These pins are the input/output pins of the upper byte and parity

to

bit of the DMA data bus. When the signal input to the CS1 pin

(pin 80) is valid, these pins are connected directly to the MPU

data bus.

42, 41

DMD8

DMA data 8

49

UDMDP

Upper DMA

data parity

39, 38, 37, DMD7

36, 35, 34, to

DMA data 7

to

DMA data 0

I/O These pins are the input/output pins of the lower byte and parity

bit of the DMA data bus. When the CS1 (pin 80) input is valid,

these pins are connected directly to the MPU data bus.

33, 32

DMD0

31

LDMDP

Lower DMA

data parity

27

26

IORD

I/O read

I

In the 80-series mode, this pin (IORD or RD) is used for the input

pin to output the data from the SPC to the DMA bus. This is an

active-low pin. In the 68-series mode, this pin functions as a

control signal input pin (DMR/W) to input/output the data to the

SPC by the DMA controller. In the output operation, this pin is on

the high-state (active-high state). In the input operation, this pin

is on the low-state (active-low state).

(DMR/W) (DMA read/

write)

IOWR

(DMLDS) (DMA lower

data strobe)

I/O write

I

In the 80-series mode, this (IOWR or WR) is used for the input

pin to input the DMA bus data to the SPC. In the 68-series mode,

this pin functions as a DMA lower data strobe input (DMLDS)

that DMA controller outputs when the lower byte of the DMA bus

data is valid. Both IOWR and DMLDS pins are an active-low.

(Continued)

6

MB86604L

(Continued)

number

Symbol*

Pin name

I/O

Function

50

DMBHE

(DMUDS) high enable

(DMA upper

DMA bus

I

In the 80-series mode, this pin is for the DMA bus high enable

signal input pin (DMBHE) output from the DMA controller when

the upper byte of the DMA data bus is valid. This is an active-low

pin. In the 68-series mode, this pin functions as the DMA upper

data strobe signal input pin (DMUDS) output from the DMA

controller when the upper byte of data bus is valid. The DMUDS

pin is also an active-low.

data strobe)

30

55

DMA0

TP

DMA

address 0

I

In the 80-series mode, this pin is used for the DMA address 0

input pin output from the DMA controller. In the 68-series mode,

a high level should be input to this pin.

Transfer

permission

This is a DMA transfer permission signal input pin. When this pin

is in active-state, the SPC does the DMA transfer. In case that

this pin becomes inactive during the DMA transfer, the DMA

transfer is paused on the block boundary. This pin is an active

high.

* : The pin symbols in parenthesis are the ones when the MODE input is “L”.

4. Others

Symbol*

Pin name

Reset

I/O

Function

number

6

RESET

I

System reset input pin. The input reset active pulse width must

have 4 times of the clock cycle at least. This is an active-low pin.

5

CLK

Clock

I

Clock signal input pin. 20 MHz, 30 MHz, or 40 MHz can be

applied as the input clock frequency.

3, 14, 28 V^DD

53, 64, 78

Power supply

Ground

—

+5 V power supply pins.

4, 10, 15 V^SS

16, 21, 29

40, 54, 59

65, 66, 70

79, 90

Ground pins.

23

TEST1

TEST

I

This pin is used to select the type of I/O buffer on SCSI data bus

pins. In case that DBP, DB7 – DB0 pins are used as an open-

drain I/O, connect this pin to V^SS. In case of three-state I/O,

connect to VDD.

57

TEST2

TMOUT

(OPEN)

TEST

This pin is used to select the type of I/O buffer on SCSI pins. In

case that MSG, C/D, I/O, and ATN pins are used as an open-

drain I/O, connect this pin to VSS. In case of three-state I/O,

connect to VDD.

24

TIMEOUT

O

—

This is a SCSI Timeout pin that indicates the SPC has been

busy longer than the specified time. A high level is output on this

pin if the SPC busy time exceeds the specified time.

This pin can be used for the timeout counter.

25, 26

(Open)

These are open pins. Those pins are not connected with the

device internally. Those pins must be left open.

* : The pin symbols in parenthesis are the symbols when the MODE input is “L”.

7

MB86604L

■ BLOCK DIAGRAM

D15 to D8, UDP

D7 to D0, LDP

TMOUT INT

WR

RD CS0 CS1 A4 to A0 BHE MODE

MPU interface

Internal

processor

Registers

MSG

C/D

I/O

DREQ

DACK

DMBHE

DMA0

ATN

BSY

SEL

RST

Receive MCS buffer

(32 bytes)

Timer

DMD15

to DMD8

UDMDP

DMD7

to DMD0

LDMDP

Phase

controller

Send MCS buffer

(32 bytes)

REQ

ACK

Transfer

controller

Command user

program memory

(256 bytes)

IOWR

IORD

TP

Data register

(32 bytes)

DB7 to DB0

DBP

8

MB86604L

■ BLOCK DESCRIPTION

1. International Processor (Sequencer)

Performs sequence control between the SCSI bus phases.

Information transfer

Bus free phase

phase

Information transfer phase:

• Command phase

• Data phase

• Status phase

• Message phase

Arbitration phase

Selection phase

2. Timer

Manages the SCSI time standards.

Also, conducts the following time managements.

• Time until the REQ or ACK signal is asserted for asychronous transfer data

• Time until selection or reselection is retried

• REQ and ACK timeout time during transfers:

Asychronous transfer case

Target: After the REQ is asserted, the time until the initiator asserts the ACK

Initiator: After the ACK is asserted, the time until the target negates the REQ

Synchronous transfer case

Target: After the REQ is sent, the time until an ACK signal which makes the offset 0 is received from the

initiator

• SPC Timeout

Manages the SPC timeout indicating the SPC busy time longer than the specified time.

3. Phase Controller

Controls the various phases executed by SCSI such as arbitration, selection/reselection, data in/out, command,

status, and message in/out.

4. Transfer Controller

Controls the information (data, command, status, message) transfer phases executed by SCSI.

The following two types of transfer phases are used.

Asychronous transfer: Controls interlock (response confirmation format) between the REQ and ACK signals.

Synchronous transfer: Controls a maximum 32-byte offset value for the data in or data out phase.

The following two modes exist for the data phase.

Program transfer: Uses data register (address 00/01) via the MPU interface

DMA transfer: Uses DREQ and DACK signals via the DMA interface.

The transfer parameter setting values for synchronous transfer (Transfer mode, transfer rate, transfer offset) can be

strobe for individual ID device and are automatically established when the data phase is initiated.

The number of transfer bytes is defined as block length × number of blocks.

9

MB86604L

5. Register

The main registers are listed.

• Command register

Command is specified by an 8-bit code.

Specifies the program head address assigned to the user program memory for user program applications.

• Chip status register

Shows the chip's operating state, nexus counterpart ID, and data register state.

• SCSI bus status register

Shows the SCSI control signal state.

• Interrupt status register

Shows 8-bit code.

• Command step register

Shows 8-bit code indicating the command execution state.

Error analysis can be performed by referring to the information in this register and the interrupt status register.

• Group 6/7 command length setting register

Sets the group 6/7 command length which is undefined by the SCSI standard.

By setting the command length in this register, the SPC can determine the command length.

6. Receive-MCS Buffer

A receive only, 32-byte data buffer which stores information received via SCSI (message, command, status)

M: Message, C: Command, S: Status

7. Send-MCS Buffer

A send only, 32-byte data buffer which stores information sent via SCSI (message, command, status)

8. Command User Program Memory

Program memory used for establishing programmable commands (256 bytes).

9. Data Register

FIFO-type data register which stores data in SCSI data phase (32 bytes).

10

MB86604L

■ ABSOLUTE MAXIMUM RATINGS (See WARNING)

Rating

Parameter

Power supply voltage*

Symbol

Unit

Min.

Max.

V^DD

V^I

VSS – 0.5

6.0

V

Input voltage*

VDD + 0.5

V

Output voltage*

VO

Operating ambient temperature

Storage temperature

Top

Tstg

°C

–25

–40

+85

+125

* : VSS = 0 V

WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded.

Functional operation should be restricted to the conditions as detailed in the operational sections of

this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Power supply voltage *¹

Symbol

Unit

Min.

4.75

3.5

2.2

2.0

—

Typ.

5.0

—

Max.

5.25

—

VDD

V

CLK

“H” level

Except SCSI and CLK pins

SCSI pins

V^IH

V^IL

I^OH

—

V

input voltage *¹

—

V

CLK

—

1.5

V

“L” level

input voltage *¹

Except CLK pin

Except SCSI pins

—

0.8

V

—

–2.0

–8.0

—

mA

°C

“H” level

Three-state

SCSI pins

—

output current *²

Open-drain

—

Except SCSI pins

SCSI pins

—

+3.2

+48

+70

“L” level

I^OL

Ta

output current *²

—

Operating ambient temperature

0

—

*1: VSS = 0 V

*2: SCSI pins are DB7 to DB0, DBP, BSY, SEL, RST, ATN, REQ, ACK, MSG, C/D, I/O

Note: The recommended operating conditions are the values recommended to ensure correct logic operation of

the LSI. The standard values of the electrical characteristics (DC and AC characteristics) are guaranteed

within the range of the recommended operating conditions.

11

MB86604L

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

(VDD = +5 V±5%, VSS = 0 V, Ta = 0°C to +70°C)

Value

Symbol

Parameter

Condition

Unit

Min. Max.

CLK

3.5

2.2

—

V

“H” level

input voltage

Except SCSI and

V^IH

—

CLK pins

SCSI pins

CLK

2.0

—

1.5

0.8

—

V

“L” level

input voltage

V^IL

—

Except CLK pin

—

Input hysteresis of SCSI pins *¹

VHW

0.3

4.2

2.0

—

Except SCSI pins

IOH = –2.0 mA

I^OH= –8.0 mA

VDD

—

“H” level

Three-state

Open-drain

V^OH

output voltage *¹

SCSI

pins

—

Except SCSI pins

SCSI pins

IOL = +3.2 mA

I^OL= +48.0 mA

VSS ≤ VI ≤ VDD

VSS

—

0.4

0.5

“L” level

V^OL

output voltage *¹

Input leakage current

I^LI

–10 +10 µA

Input/output leakage current

I^LOZ

VSS ≤ VI ≤ VDD, See Note below

CLK input = 20 MHz

SPC operating clock = 10 MHz

45

48

55

65

60

70

mA

CLK input = 30 MHz

SPC operating clock = 10 MHz

CLK input = 40 MHz

SPC operating clock = 13.3 MHz

All output

pins

Power supply current

I^DD

—

CLK input = 30 MHz

SPC operating clock = 15 MHz

opened

CLK input = 20 MHz

SPC operating clock = 20 MHz

CLK input = 40 MHz

SPC operating clock = 20 MHz

*1: SCSI pins are DB7 to DB0, DBP, BSY, SEL, RST, ATN, REQ, ACK, MSG, C/D, I/O

Note: Leakage current in the above spec indicates the following currents.

(1) Leakage current at the high-Z state on the three-state output pins.

(2) Leakage current at the output high-Z state (input state) on the bidirectional bus pins.

12

MB86604L

2. I/O Pin Capacitance

(VDD = VI = 0 V, f = 1 MHz, Ta = +25°C)

Value

Unit

Parameter

Symbol

Min.

—

Max.

Input pin capacitance

Output pin capacitance

C^IN

6

pF

C^OUT

—

6

Except SCSI pins

SCSI pins

—

6

I/O pin capacitance

C^I/O

—

25

3. Load Conditions for AC Characteristics

(VDD = +5 V±5%, VSS = 0 V, Ta = 0°C to +70°C)

Non-SCSI pins

Measurement

point

C^L

Pin Symbol

INT, DREQ

60 pF

MB86604L

D15 to D8, UDP, D7 to D0, LDP

DMD15 to DMD8, UDMDP

85 pF

Measurement pin

DMD7 to DMD0, LDMDP

C^L: Load capacitance

C L

SCSI pins

Measurement

point

V DD

R^L1= 110 Ω

R^L2= 165 Ω

R^L= 200 pF

Load resistance

MB86604L

R L1

R L2

Load capacitance

Measurement pin

C L

13

MB86604L

4. AC Characteristics

(1) System clock

Value

Parameter

Symbol

Unit

Position*

Min.

25.0

10.0

—

Max.

50.0

—

Clock cycle time (CLK)

Clock “H” pulse width

Clock “L” pulse width

Clock rise time

t^CLK

twCKH

twCKL

t^CR

A

B

C

D

E

ns

—

10.0

Clock fall time

tCF

—

* : The position number indicates the position in the waveform.

Note: In case that the internal clock frequency and the input clock frequency are the same (i.e. when using the

divided-by-one mode), the clock pulse width (for “H” and “L”) must have at least 20 ns or longer.

B

A

t wCKH

t CLK

E

D

t CR

t CF

3.5 V

1.5 V

CLK

C

t wCKL

(2) System reset

Value

Parameter

Symbol

Unit

Min.

Max.

RESET “L” level pulse width

twRSL

4 tCLK

—

ns

t wRSL

RESET

14

MB86604L

(3) MPU interface (80 series)

• Register write timing

Value

Unit

Parameter

Symbol

Position*

Base signal

WR “L”

WR “H”

WR “L”

WR “H”

—

Min.

Max.

Address (A4 to A0), BHE set up time

Address (A4 to A0), hold time

CS0 set up time

tsuA

thA

A

B

C

D

E

F

40

20

10

70

40

10

—

ns

—

tsuCS0

thCS0

twWRL

tsuD

—

CS0 hold time

—

WR “L” level pulse width

Data set up time

—

WR “H”

—

Data hold time

thD

G

—

* : The position number indicates the position in the waveform.

A4 to A0

BHE

A

B

t

suA

t

hA

CS0

WR

C

D

E

t

hCS0

t

suCS0

t

wWRL

F

G

t

suD

t

hD

D15 to D8, UDP

D7 to D0, LDP

Data

15

MB86604L

• Register read timing

Value

Parameter

Symbol

Unit

Position*

Base signal

RD “L”

RD “H”

RD “L”

RD “H”

—

Min.

40

20

10

70

—

Max.

—

Address (A4 to A0), BHE set up time

Address (A4 to A0), Hold time

CS0 set up time

tsuA

thA

A

B

C

D

E

F

G

H

I

ns

—

tsuCS0

thCS0

twRDL

tvD

—

CS0 hold time

—

RD “L” level pulse width

Data output defined time

Data output disable time

—

RD “L”

RD “H”

RD “L”

RD “H”

70

—

tDZ

10

—

for INT non-hold mode

INT signal

tDL

50

clear time

n tCLK + 50

for INT hold mode

tDL2

—

* : The position number indicates the position in the waveform.

A4 to A0

BHE

B

A

t hA

t suA

CS0

E

C

D

t wRDL

t suCS0

t hCS0

RD

G

F

t vD

t DZ

D15 to D8, UDP

D7 to D0, LDP

Valid data

H

t DL

INT

t DL2*

I

*: t DL2 is determined by a rising edge of the strobe signal which reads the step code for the last interrupt source.

Also, “n” indicates the division ratio.

16

MB86604L

• Register write timing (for external access)

Parameter

Value

Unit

Symbol

Position*

Base signal

WR “L”

WR “H”

WR “L”

WR “H”

WR “L”

WR “H”

—

Min.

Max.

Address (A0), BHE set up time

Address (A0), BHE hold time

CS1 set up time

tsuAE

thAE

A

B

C

D

E

F

40

20

10

—

10

—

ns

—

tsuCS1

thCS1

—

CS1 hold time

—

DMA data bus output delay time

DMA data bus output undefined time

MPU data → DMA data bus output delay time

tvDMD

tWRDMD

t^DDMD

70

—

G

40

* : The position number indicates the position in the waveform.

A0

BHE

A

B

t ^suAE

t hAE

CS1

C

D

t suCS1

t hCS1

WR

E

F

t vDMD

t WRDMD

D15 to D8, UDP

D7 to D0, LDP

Data

G

t DDMD

DMD15 to DMD8, UDMDP

DMD7 to DMD0, LDMDP

Valid data

17

MB86604L

• Register read timing (for external access)

Parameter

Value

Symbol

Unit

Position*

Base signal

RD “L”

RD “H”

RD “L”

RD “H”

RD “L”

RD “H”

—

Min.

40

20

10

—

Max.

—

Address (A0), BHE set up time

Address (A0), BHE hold time

CS1 set up time

tsuAE

thAE

A

B

C

D

E

F

ns

—

tsuCS1

thCS1

tZD

—

CS1 hold time

—

MPU data bus output enable time

MPU data bus output disable time

DMA data → MPU data bus output delay time

70

—

tDZ

10

—

t^DMDD

G

40

* : The position number indicates the position in the waveform.

A0

BHE

A

B

t suAE

t hAE

CS1

D

C

t hCS1

t suCS1

RD

DMD15 to DMD8, UDMDP

DMD7 to DMD0, LDMDP

Data

G

F

t DMDD

t ZD

E

t DZ

D15 to D8, UDP

D7 to D0, LDP

Valid data

18

MB86604L

(4) MPU interface (68 series)

• Register write timing

Value

Unit

Parameter

Symbol

Position*

Base signal

UDS/LDS “L”

UDS/LDS “H”

UDS/LDS “L”

UDS/LDS “H”

UDS/LDS “L”

UDS/LDS “H”

—

Min.

Max.

Address (A4 to A0) set up time

Address (A4 to A0) hold time

CS0 set up time

tsuA

thA

A

B

C

D

E

F

G

H

I

40

20

10

20

70

40

10

—

ns

—

tsuCS0

thCS0

tsuRW

thRW

twDS

tsuD

—

CS0 hold time

—

R/W set up time

—

R/W hold time

—

UDS/LDS “L” level pulse width

Data set up time

—

UDS/LDS “H”

—

Data hold time

thD

—

* : The position number indicates the position in the waveform.

A4 to A0

B

t hA

A

t suA

CS0

D

C

t hCS0

t suCS0

R/W

F

E

t hRW

t suRW

G

t wDS

UDS/LDS

H

I

t suD

t hD

D15 to D8, UDP

D7 to D0, LDP

Data

19

MB86604L

• Register read timing

Value

Parameter

Symbol

Unit

Position*

Base signal

UDS/LDS “L”

UDS/LDS “H”

UDS/LDS “L”

UDS/LDS “H”

UDS/LDS “L”

UDS/LDS “H”

—

Min.

40

20

10

20

70

—

Max.

—

Address (A4 to A0) set up time

Address (A4 to A0) hold time

CS0 set up time

tsuA

thA

A

B

C

D

E

F

G

H

I

ns

—

tsuCS0

thCS0

tsuRW

thRW

twDS

tvD

—

CS0 hold time

—

R/W set up time

—

R/W hold time

—

UDS/LDS “L” level pulse time

Data output confirmation time

Data output disable time

—

UDS/LDS “L”

UDS/LDS “H”

UDS/LDS “L”

UDS/LDS “H”

70

—

tDZ

10

—

for INT non-hold mode

INT signal

tDH

J

50

clear time

for INT hold mode

tDH2

K

—

n tCLK + 50

* : The position number indicates the position in the waveform.

A4 to A0

B

A

t

hA

t

suA

CS0

R/W

D

C

t

hCS0

t

suCS0

F

E

t

hRW

suRW

G

t

wDS

UDS/LDS

I

H

t

DZ

t

vD

D15 to D8, UDP

D7 to D0, LDP

Valid data

J

t

DH

INT

K

*

DH2

t

*: t DH2 is determined by a rising edge of the strobe signal which reads the step code for the last interrupt source.

Also, “n” indicates the division ratio.

20

MB86604L

• Register write timing (for external access)

Parameter

Value

Unit

Symbol

Position*

Base signal

UDS/LDS “L”

UDS/LDS “H”

UDS/LDS “L”

UDS/LDS “H”

UDS/LDS “L”

UDS/LDS “H”

UDS/LDS “L”

UDS/LDS “H”

—

Min.

Max.

Address (A0) set up time

Address (A0) hold time

CS1 set up time

tsuAE

thAE

A

B

C

D

E

F

G

H

I

40

20

10

20

—

10

—

ns

—

tsuCS1

thCS1

tsuRW

thRW

—

CS1 hold time

—

R/W set up time

—

R/W hold time

—

DMA data bus output delay time

DMA data bus output undefined time

MPU data → DMA data bus output delay time

tvDMD

tDSDMD

t^DDMD

70

—

40

* : The position number indicates the position in the waveform.

A0

B

A

t hAE

t suAE

CS1

C

D

t suCS1

t hCS1

R/W

F

E

t hRW

t suRW

UDS/LDS

G

H

t vDMD

t DSDMD

D15 to D8, UDP

Data

D7 to D0, LDP

I

t DDMD

DMD15 to DMD8, UDMDP

DMD7 to DMD0, LDMDP

Valid data

21

MB86604L

• Register read timing (for external access)

Parameter

Value

Symbol

Unit

Position*

Base signal

UDS/LDS “L”

UDS/LDS “H”

UDS/LDS “L”

UDS/LDS “H”

UDS/LDS “L”

UDS/LDS “H”

UDS/LDS “L”

UDS/LDS “H”

—

Min.

40

20

10

20

—

Max.

—

Address (A0) set up time

Address (A0) hold time

CS1 set up time

tsuAE

thAE

A

B

C

D

E

F

G

H

I

ns

—

tsuCS1

thCS1

tsuRW

thRW

tZD

—

CS1 hold time

—

R/W set up time

—

R/W hold time

—

Data output enable time

Data output disable time

DMA data → MPU data bus output delay time

70

—

tDZ

10

—

t^DMDD

40

* : The position number indicates the position in the waveform.

A0

A

B

t suAE

t hAE

CS1

C

D

t suCS1

t hCS1

R/W

E

F

t suRW

t hRW

UDS/LDS

DMD7 to DMD0,

LDMDP

Data

DMD15 to DMD8,

UDMDP

I

t DMDD

H

G

t DZ

t ZD

D15 to D8, UDP

D7 to D0, LDP

Valid data

22

MB86604L

(5) DMA interface

The DMA access timing described in this section is not applicable in the following cases.

During SCSI input, when the data buffer is EMPTY or when one byte is stored

During SCSI output, when the data buffer is FULL or when 31 bytes are stored

When a parity error is detected (target)

When an error which pauses the transfer occurs at the SCSI interface

• 80 series handshake mode

(a) Write timing

Value

Unit

Parameter

DACK “L” assert time

Symbol

Position*

Base signal

DREQ “H”

DACK “L”

DACK “H”

DACK “L”

IOWR “L”

IOWR “H”

—

Min.

Max.

tRQAK

tAKRQ

tAKRQ1

tAKRQ2

tAKWR

tsuDA

A

B

C

D

E

F

G

H

I

0

—

0

—

40

ns

DREQ “L” negate time

DREQ “H” assert time (8 bit)

DREQ “H” assert time (16 bit)

IOWR “L” assert time

50

2 tCLK + 40

—

DMBHE, DMA0 set up time

DMBHE, DMA0 hold time

IOWR “L” level pulse width

20

40

1 tCLK

0

—

thDA

—

twWRL

tWRAK1

tWRAK2

tsuDMD

thDMD

—

IOWR “L”

IOWR “H”

—

DACK “H” negate time

—

Input data set up time

Input data hold time

J

30

5

—

K

—

* : The position number indicates the position in the waveform.

23

MB86604L

DREQ

DACK

A

B

C

t RQAK

t AKRQ

t AKRQ1/2

H

D

t WRAK1

I

t AKWR

t WRAK2

DMBHE

DMA0

E

F

t suDA

t hDA

G

t wWRL

IOWR

K

J

t suDMD

t hDMD

DMD15 to DMD0

UDMDP, LDMDP

Data

24

MB86604L

(b) Read timing

Value

Unit

Parameter

Symbol

Position*

Base signal

DREQ “H”

DACK “L”

DACK “H”

DACK “L”

IORD “L”

IORD “H”

—

Min.

Max.

DACK “L” assert time

tRQAK

tAKRQ

tAKRQ1

tAKRQ2

tAKRD

tsuDA

A

B

C

D

E

F

G

H

I

0

—

40

ns

DREQ “L” negate time

DREQ “H” assert time (8 bit)

DREQ “H” assert time (16 bit)

IORD “L” assert time

—

50

2 tCLK + 40

—

0

DMBHE, DMA0 set up time

DMBHE, DMA0 hold time

IORD “L” level pulse width

20

40

1 tCLK

0

—

thDA

—

twRDL

tRDAK1

tRDAK2

tvDMD

thDMD

—

IORD “L”

IORD “H”

IORD “L”

IORD “H”

—

DACK “H” negate time

—

Data output defined time

Data output hold time

J

—

40

K

10

—

* : The position number indicates the position in the waveform.

DREQ

A

B

C

t RQAK

t AKRQ

t AKRQ1/2

DACK

H

D

t AKRD

t RDAK1

I

t RDAK2

DMBHE

DMA0

E

F

t suDA

t hDA

G

t wRDL

IORD

J

K

t vDMD

t hDMD

DMD15 to DMD0

UDMDP, LDMDP

Valid data

25

MB86604L

• 68 series handshake mode

(a) Write timing

Value

Parameter

Symbol

Unit

Position*

Base signal

DREQ “H”

Min.

0

Max.

—

DACK “L” assert time

tRQAK

tAKRQ

tAKRQ1

tAKRQ2

tAKDS

tsuRW

thRW

A

B

C

D

E

F

G

H

I

ns

DREQ “L” negate time

DACK “L”

—

0

40

DREQ “H” assert time (8 bit)

DREQ “H” assert time (16 bit)

DMUDS/DMLDS “L” assert time

DMR/W set up time

DACK “H”

50

2 tCLK + 40

DACK “H”

DACK “L”

—

DMUDS/DMLDS “L”

DMUDS/DMLDS “H”

—

20

40

1 tCLK

0

DMR/W hold time

DMUDS/DMLDS “L” level pulse width

twDSL

DMUDS/DMLDS “L”

DMUDS/DMLDS “H”

tDSAK1

tDSAK2

tsuDMD

thDMD

DACK “H” negate time

Input data set up time

Input data hold time

J

30

5

K

* : The position number indicates the position in the waveform.

DREQ

A

B

t AKRQ

C

t RQAK

t AKRQ1/2

DACK

H

D

t DSAK1

I

t AKDS

t DSAK2

DMR/W

E

F

t suRW

t hRW

G

t wDSL

DMUDS/DMLDS

J

K

t suDMD

t hDMD

DMD15 to DMD0

UDMDP, LDMDP

Data

26

MB86604L

(b) Read timing

Parameter

Value

Unit

Symbol

Position*

Base signal

DREQ “H”

Min.

Max.

DACK “L” assert time

tRQAK

tAKRQ

tAKRQ1

tAKRQ2

tAKDS

tsuRW

thRW

A

B

C

D

E

F

G

H

I

0

—

40

ns

DREQ “L” negate time

DACK “L”

DREQ “H” assert time (8 bit)

DREQ “H” assert time (16 bit)

DMUDS/DMLDS “L” assert time

DMR/W set up time

DACK “H”

—

50

DACK “H”

—

2 tCLK + 40

—

DACK “L”

0

DMUDS/DMLDS “L”

DMUDS/DMLDS “H”

—

20

40

1 tCLK

0

—

DMR/W hold time

—

DMUDS/DMLDS “L” level pulse width

twDSL

tDSAK1

tDSAK2

tvDMD

thDMD

—

DMUDS/DMLDS “L”

DMUDS/DMLDS “H”

DMUDS/DMLDS “L”

DMUDS/DMLDS “H”

—

DACK “H” negate time

—

Data output defined time

Data output hold time

J

—

40

K

10

—

* : The position number indicates the position in the waveform.

DREQ

A

B

C

t RQAK

t AKRQ

t AKRQ1/2

DACK

H

D

t DSAK1

I

t AKDS

t DSAK2

DMR/W

E

F

t suRW

t hRW

G

t wDSL

DMUDS/DMLDS

J

K

t vDMD

t hDMD

DMD15 to DMD0

UDMDP, LDMDP

Valid data

27

MB86604L

• Burst mode (80 series/68 series common)

(a) Data register access cycle time (8 bit)

Value

Parameter

Symbol

Unit

Position*

Base signal

Min.

tCLK

Max.

—

Data register access cycle time 1

Data register access cycle time 2

Data register access cycle time 3

—

t^DCY1

t^DCY2

tDCY3

A

B

C

ns

3 tCLK

4 tCLK

—

* : The position number indicates the position in the waveform.

IOWR/IORD

DMUDS/DMLDS

A

t DCY1

B

t DCY2

C

t DCY3

(b) Data register access cycle time (16 bit)

Parameter

Value

Symbol

Unit

Position*

Base signal

Min.

4 tCLK

3 tCLK

Max.

—

Data register access cycle time 1

Data register access cycle time 2

—

t^DCY1

A

B

ns

tDCY2

—

* : The position number indicates the position in the waveform.

IOWR/IORD

DMUDS/DMLDS

B

t DCY2

A

t DCY1

28

MB86604L

• 80 series burst mode

(a) Write timing

Value

Unit

Parameter

Symbol

Position*

Base signal

DREQ “H”

IOWR “L”

—

Min.

Max.

DACK “L” assert time

tRQAK

tWRRQ

tRQLH

tAKWR

tsuDA

A

B

C

D

E

F

G

H

I

0

—

0

—

ns

DREQ “L” negate time

DREQ “L” → DREQ “H” return time

IOWR “L” assert time

55

—

DACK “L”

IOWR “L”

IOWR “H”

—

0

—

DMBHE, DMA0 set up time

DMBHE, DMA0 hold time

IOWR “L” level pulse width

DACK “H” negate time

Input data set up time

20

40

0

—

thDA

—

twWRL

tWRAK

tsuDMD

thDMD

—

IOWR “H”

—

30

5

—

Input data hold time

J

—

* : The position number indicates the position in the waveform.

DREQ

C

B

A

t WRRQ

t RQLH

t ^RQAK

DACK

D

H

t AKWR

t WRAK

DMBHE

DMA0

E

F

t suDA

t hDA

G

t wWRL

IOWR

I

J

t suDMD

t hDMD

DMD15 to DMD0

UDMDP, LDMDP

Data

29

MB86604L

(b) Read timing

Value

Parameter

Symbol

Unit

Position*

Base signal

DREQ “H”

IORD “L”

—

Min.

0

Max.

—

DACK “L” assert time

tRQAK

tRDRQ

tRQLH

tAKRD

tsuDA

thDA

A

B

C

D

E

F

G

H

I

ns

DREQ “L” negate time

—

0

55

—

DREQ “L” → DREQ “H” return time

IORD “L” assert time

DACK “L”

IORD “L”

IORD “H”

—

0

—

DMBHE, DMA0 set up time

DMBHE, DMA0 hold time

IORD “L” level pulse width

DACK “H” negate time

20

40

0

—

twRDL

tRDAK

tvDMD

thDMD

—

IORD “H”

IORD “L”

IORD “H”

—

Data output defined time

Data output hold time

—

10

40

—

J

* : The position number indicates the position in the waveform.

DREQ

A

C

B

t RQAK

t RDRQ

t RQLH

DACK

D

H

t AKRD

t RDAK

DMBHE

DMA0

E

F

t suDA

t hDA

G

t wRDL

IORD

I

J

t vDMD

t hDMD

DMD15 to DMD0

UDMDP, LDMDP

Valid data

30

MB86604L

• 68 series burst mode

(a) Write timing

Value

Unit

Parameter

Symbol

Position*

Base signal

DREQ “H”

Min.

Max.

DACK “L” assert time

tRQAK

tDSRQ

tRQLH

tAKDS

tsuRW

thRW

A

B

C

D

E

F

G

H

I

0

—

0

—

ns

DREQ “L” negate time

DMUDS/DMLDS “L”

—

55

—

DREQ “L” → DREQ “H” return time

DMUDS/DMLDS “L” assert time

DMR/W set up time

DACK “L”

0

—

DMUDS/DMLDS “L”

DMUDS/DMLDS “H”

—

20

40

0

—

DMR/W hold time

—

DMUDS/DMLDS “L” level pulse width

DACK “H” negate time

twDSL

tDSAK

tsuDMD

thDMD

—

DMUDS/DMLDS “H”

—

Input data set up time

30

5

—

Input data hold time

J

—

* : The position number indicates the position in the waveform.

DREQ

B

A

C

t RQAK

t DSRQ

t RQLH

DACK

D

H

t AKDS

t DSAK

DMR/W

E

F

t suRW

t hRW

G

t wDSL

DMUDS/DMLDS

I

J

t hDMD

t suDMD

DMD15 to DMD0

UDMDP, LDMDP

Data

31

MB86604L

(b) Read timing

Value

Parameter

Symbol

Unit

Position*

Base signal

DREQ “H”

Min.

0

Max.

—

DACK “L” assert time

tRQAK

tDSRQ

tRQLH

tAKDS

tsuRW

thRW

A

B

C

D

E

F

G

H

I

ns

DREQ “L” negate time

DMUDS/DMLDS “L”

—

0

55

—

DREQ “L” → DREQ “H” return time

DMUDS/DMLDS “L” assert time

DMR/W set up time

DACK “L”

0

—

DMUDS/DMLDS “L”

DMUDS/DMLDS “H”

—

20

40

0

—

DMR/W hold time

—

DMUDS/DMLDS “L” level pulse width

DACK “H” negate time

twDSL

tDSAK

tvDMD

thDMD

—

DMUDS/DMLDS “H”

DMUDS/DMLDS “L”

DMUDS/DMLDS “H”

—

Data output defined time

Data output hold time

—

10

40

—

J

* : The position number indicates the position in the waveform.

DREQ

A

B

C

t RQAK

t DSRQ

t RQLH

DACK

D

H

t AKDS

t DSAK

DMR/W

F

E

t hRW

t suRW

G

t wDSL

DMUDS/DMLDS

I

J

t hDMD

t vDMD

DMD15 to DMD0

UDMDP, LDMDP

Valid data

32

MB86604L

(6) SCSI interface (as initiator)

• Asynchronous transfer mode

(a) Input timing (target → initiator)

Value

Unit

Parameter

Symbol

Base signal

ACK “L”

Position*¹

Min.

Max.

REQ “H” negate time

ACK “H” negate time

REQ “L” assert time

Input data set up time

Input data hold time

ACK “L” assert time 1

ACK “L” assert time 2 *²

tAKRQH

tRQAKH

tAKRQL

tsuDB

A

B

C

D

E

F

0

—

ns

REQ “H”

ACK “H”

REQ “L”

REQ “H”

—

10

20

—

60

—

thDB

—

tRQAK1

tRQAK2

40

3 tCLK + 40

G

*1: The position number indicates the position in the waveform.

*2: The REQ “H” → ACK “L” time (tRQAK2) is compared with (tRQAKH + tAKRQL + tRQAK1) and the longer value is chosen.

Note: The input timing definition is not applied in the following cases.

• When the data register is FULL in the data phase

• When the final byte is being transferred

G

t RQAK2

REQ

A

C

F

B

t AKRQL

t RQAK1

t RQAKH

t AKRQH

ACK

D

E

t suDB

t hDB

DB7 to DB0

DBP

Data

33

MB86604L

(b) Output timing (initiator → target)

Value

Min.

Parameter

Symbol

Unit

Base signal

ACK “L”

Position*¹

Max.

—

REQ “H” negate time

tAKRQH

tRQAKH

tAKRQL

A

B

C

0

ns

ACK “H” negate time

REQ “H”

ACK “H”

—

10

60

REQ “L” assert time

—

Time from output data valid to ACK “L” assert

*

S • tCLK – 10

—

tDBAK

D

—

ns

2

Output data hold time

ACK “L” assert time

REQ “H”

REQ “L”

thDB

E

F

2 tCLK

—

ns

tRQAK1

—

40

*1: The position number indicates the position in the waveform.

*2: “S” value is based on the asychronous set up time setting register (address 17h).

Note: The output timing definitions are not applied when the data register is EMPTY in the data phase.

*

t RQAK2

REQ

A

B

F

C

t AKRQH

t RQAKH

t AKRQL

t RQAK1

ACK

D

E

D

t DBAK

t hDB

t DBAK

DB7 to DB0

DBP

Valid data

*: The REQ “H” → ACK “L” time (t^RQAK2) is defined by either longer of (t^RQAKH+ t^AKRQL+ t^RQAK1) or (t^hDB+

t^DBAK) (see the output timing waveform).

34

MB86604L

• Synchronous transfer mode

(a) REQ/ACK signal period

Value

Unit

Parameter

Symbol

Base signal

Position*¹

Min.

Max.

ACK assert time *²

ACK negate time *²

REQ assert time

A • tCLK – 12

N • tCLK + 2

20

—

tAKAP

tAKNP

A

B

C

D

E

F

—

ns

—

tRQAP

tRQNP

tRQCY1

tRQCY2

—

REQ negate time

20

—

REQ input cycle time 1

REQ input cycle time 2

1 tCLK

—

3 tCLK

—

*1: The position number indicates the position in the waveform.

*2: “A” and “N” values are based on the transfer period register (address 0Dh) setting.

A

B

t AKAP

t AKNP

ACK

REQ

C

D

t RQAP

t RQNP

E

t RQCY1

F

t RQCY2

35

MB86604L

(b) Input timing (target → initiator)

Value

Parameter

Symbol

Unit

Position*

Base signal

REQ “L”

Min.

5

Max.

—

Input data set up time

Input data hold time

tsuDB

thDB

A

B

ns

REQ “L”

15

—

* : The position number indicates the position in the waveform.

REQ

A

B

A

B

t suDB

t hDB

t suDB

t hDB

DB7 to DB0

DBP

Data

(c) Input timing (target → initiator)

Value

Parameter

Symbol

Unit

Base signal

—

Position*¹

Min.

Max.

—

Time from output data valid to ACK “L” assert

tDBAK

thDB

A

B

N • tCLK + 2

A • tCLK – 12

ns

2

*

Output data hold time *²

ACK “L”

—

*1: The position number indicates the position in the waveform.

*2: “A” and “N” values are based on the transfer period register (address 0Dh) setting.

ACK

B

A

B

t DBAK

t hDB

t DBAK

t hDB

DB7 to DB0

DBP

Valid data

36

MB86604L

(7) SCSI interface (as initiator)

• Asynchronous transfer mode

(a) Input timing (initiator → target)

Value

Unit

Parameter

Symbol

Base signal

REQ “L”

ACK “L”

REQ “H”

ACK “L”

ACK “H”

Position*¹

Min.

Max.

ACK “L” assert time

REQ “H” negate time

ACK “H” negate time

Input data set up time

Input data hold time

ACK “L” assert time 1

ACK “L” assert time 2 *²

tRQAKL

tAKRQH

tRQAKH

tsuDB

A

B

C

D

E

F

0

—

ns

—

0

60

—

10

20

—

thDB

—

tAKRQ1

tALRQ2

40

3 tCLK + 40

G

*1: The position number indicates the position in the waveform.

*2: The REQ “L” → REQ “L” time (t^AKRQ2) is compared with (tAKRQH + tRQAKH + tAKRQ1) and the longer value is chosen.

Note: The input timing definition is not applied in the following cases.

• When the data register is FULL in the data phase

• When the final byte is being transferred

G

t AKRQ2

REQ

A

B

C

F

t RQAKH

t RQAKL

t AKRQH

t AKRQ1

ACK

D

E

t suDB

t hDB

DB7 to DB0

DBP

Data

37

MB86604L

(b) Output timing (target → initiator)

Value

Min.

Parameter

Symbol

Unit

Base signal

REQ “L”

Position*¹

Max.

—

ACK “L” assert time

REQ “H” negate time

ACK “H” negate time

tRQAKL

tAKRQH

tRQAKH

A

B

C

0

—

0

ns

ACK “L”

60

REQ “H”

—

Time from output data valid to

REQ “L” assert *²

S • tCLK – 10

—

tDBRQ

D

—

ns

Output data hold time

REQ “L” assert time

ACK “L”

ACK “H”

thDB

E

F

2 tCLK

—

ns

tAKRQ1

—

40

*1: The position number indicates the position in the waveform.

*2: “S” value is based on the asychronous set up time setting register (address 17h).

Note: The output timing definitions are not applied when the data register is EMPTY in the data phase.

*

t AKRQ2

REQ

F

A

B

C

t RQAKH

t AKRQ1

t RQAKL

t AKRQH

ACK

E

D

t hDB

t DBRQ

DB7 to DB0

DBP

Valid data

*: The ACK “L” → REQ “L” time (t^AKRQ2) is defined by either longer of (t^AKRQH+ t^RQAKH+ t^AKRQ1) or (t^hDB+ t^DBRQ).

38

MB86604L

• Synchronous transfer mode

(a) REQ/ACK signal period

Value

Unit

Parameter

Symbol

Position*¹

Min.

Max.

REQ assert time *²

REQ negate time *²

ACK assert time

A • tCLK – 12

N • tCLK + 2

20

tRQAP

tRQNP

tAKAP

A

B

C

D

E

F

—

ns

ACK negate time

tAKNP

tAKCY1

tAKCY2

20

ACK input cycle time 1

ACK input cycle time 2

1 tCLK

3 tCLK

*1: The position number indicates the position in the waveform.

*2: “A” and “N” values are based on the transfer period register (address 0Dh). See (8) for more setting values.

A

B

t ^RQAP

t RQNP

REQ

ACK

C

D

t ^AKAP

t AKNP

E

t AKCY1

F

t AKCY2

39

MB86604L

(b) Input timing (initiator → target)

Value

Parameter

Symbol

Unit

Position*

Base signal

ACK “L”

Min.

5

Max.

—

Input data set up time

Input data hold time

tsuDB

thDB

A

B

ns

ACK “L”

15

—

* : The position number indicates the position in the waveform.

ACK

B

A

B

A

t ^suDB

t hDB

t suDB

t hDB

DB7 to DB0

DBP

Data

(c) Output timing (target → initiator)

Value

Parameter

Symbol

Unit

Base signal

—

Position*¹

Min.

Max.

—

Time from output data valid to

REQ “L” assert *²

tDBRQ

thDB

A

B

N • tCLK + 2

A • tCLK – 12

ns

Output data hold time *²

REQ “L”

—

*1: The position number indicates the position in the waveform.

*2: “A” and “N” values are based on the transfer period register (address 0Dh). See (8) for more setting values.

REQ

A

t DBRQ

B

A

B

t hDB

t DBRQ

t hDB

DB7 to DB0

DBP

Valid data

40

MB86604L

(8) A/N/S values in the SCSI interface timing specification

• Transfer period register (address 0Dh) and A/N values

Transfer period register

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

A

N

A

N

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Prohibit

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

9

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

9

10

11

12

13

14

15

16

Note: The A and N values set in the register are the assert period and the negate period respectively (unit is clock

cycles)

For the AC characteristics, A/N use numerals.

• Asynchronous setup time register (address 17h) setting and the S value.

Asynchronous setup

time register

Asynchronous setup

time register

S

Bit 3 Bit 2 Bit 1 Bit 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

9

10

11

12

13

14

15

16

Note: The S (setup time) value established in the set up time register during asynchronous data transfers indicates

the time from setting data in the data bus until the REQ/ACK signals are asserted.

For the AC characteristics, S uses numerals.

41

MB86604L

■ LIST OF REGISTERS

1. BASIC Control Registers (for write)

Address

Bit assignment

Register name

Hex. A4 A3 A2 A1 A0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8

00

01

02

03

04

05

06

07

08

09

0

1

0

1

0

1

0

1

0

0 Output data register (first)

Output data register (second)

1

0 Direct control register

1 (Reserved)

DC7

0

DO4

0

0 SEL/RESEL ID register

1 Command register

SI7

SI2

SI1

SI0

CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0

BL15 BL14 BL13 BL12 BL11 BL10 BL9 BL8

BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0

BY23 BY22 BY21 BY20 BY19 BY18 BY17 BY16

BY15 BY14 BY13 BY12 BY11 BY10 BY9 BY8

0 Data block register (MSB)

1 Data block register (LSB)

0 Data byte register (MSB)

1 Data byte register

Data byte register (LSB)

0A

0

1

0

1

0

BY7 BY6 BY5 BY4 BY3 BY2 BY1 BY0

MC byte register

0B

0C

0D

0E

0F

0

1

0

1

0

1

1 Diagnostic control register

0 Transfer mode register

1 Transfer period register

0 Transfer offset register

1 Window address register

DG7 DG6 DG5

0

DG3 DG2 DG1 DG0

TM7

0

TP4 TP3 TP2 TP1 TP0

TO4 TO3 TO2 TO1 TO0

WA7 WA6

0

WA3 WA2 WA1 WA0

2. BASIC Control Registers (for read)

Address

Bit assignment

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register name

Hex. A4 A3 A2 A1 A0

00

01

02

03

04

05

06

07

08

09

0

1

0

1

0

1

0

1

0

0 Input data register (first)

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

DI8

1 Input data register (second) DI15 DI14 DI13 DI12 DI11 DI10 DI9

0 SPC status register

SS7 SS6 SS5 SS4

X

SS2 SS1 SS0

NS2 NS1 NS0

1 Nexus status register

0 Interrupt status register

1 Command step register

0 Data block register (MSB)

1 Data block register (LSB)

0 Data byte register (MSB)

1 Data byte register

NS7 NS6 NS5

IS7 IS6 IS5

X

IS4

IS3

IS2

IS1

IS0

CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0

BL15 BL14 BL13 BL12 BL11 BL10 BL9 BL8

BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0

BY23 BY22 BY21 BY20 BY19 BY18 BY17 BY16

BY15 BY14 BY13 BY12 BY11 BY10 BY9 BY8

Data byte register (LSB)

0A

0

1

0

1

0

BY7 BY6 BY5 BY4 BY3 BY2 BY1 BY0

MC byte register

SCSI control signal status register

1

0B

0C

0D

0E

0F

0

1

0

1

0

1

SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0

0 Transfer mode register

1 Transfer period register

0 Transfer offset register

1 Modified byte register

TM7

X

TP4 TP3 TP2 TP1 TP0

TO4 TO3 TO2 TO1 TO0

X

MB5 BM4 MB3 MB2 MB1 MB0

Note: X indicates data is undefined. (0 or 1).

42

MB86604L

3. Initial Setting Window (for read/write)

Address

Bit assignment

Register name

Hex. A4 A3 A2 A1 A0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1F

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0 Clock conversion setting

1 Self ID setting

CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0

0

OI2 OI1 OI0

AM1 AM0

0 Response mode setting

AM7 AM6 AM5 AM4

0

1 Selection/reselection mode setting SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0

0 Selection/reselection retry setting

Selection/reselection timeout setting

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0

RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0

1

0 REQ/ACK timeout setting

1 Asynchronous setup time setting

0 Parity error detection setting

1 Interrupt enable setting

0

AT3 AT2 AT1 AT0

PE7 PE6 PE5 PE4 PE3 PE1 PE0

IE7 IE5 IE4 IE3 IE2 IE1 IE0

0

0 Group 6/7 command length setting GL7 GL6 GL5 GL4 GL3 GL2 GL1 GL0

1 DMA system setting DM5 MD4

0 Automatic operation mode setting OM7 OM6 OM5 OM4 OM3 OM2 OM1 OM0

0

1 SPC Timeout setting

TO7 TO6 TO5 TO4 TO3 TO2 TO1 TO0

RV7 RV6 RV5 RV4 RV3 RV2 RV1 RV0

1 Device revision indication

4. MCS Buffer Window

Address

For write

For read

Hex. A4

A3

0

1

A2

0

1

0

1

A1

0

1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

1

SEND MCS buffer

RECEIVE MCS buffer

43

MB86604L

5. User Program Memory Window

Address

For write

For read

Hex. A4

A3

0

1

A2

0

1

0

1

A1

0

1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

IE

1

User program memory

1F

44

MB86604L

■ LIST OF COMMANDS

SPC commands can be specified in the command register or the user program memory and divided into the following

main groups.

• Sequential commands

Commands that perform a consecutive (including phase transitions) sequence operation. Can only be specified

in the command register (1-byte).

• Discrete commands

Commands which perform operations from disassembled sequential commands. Can be specified in the

command register (1-byte command) or the user program memory (1/2-byte command).

• Special commands

Can only be specified in the user program memory (1/2-byte command).

1. Initiator Commands

(1) Sequential commands

No

1

Command code

Operand (for program)

(not possible)

Command name

Select & CMD

00H

01H

02H

03H

04H

05H

06H

07H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

Select & 1-MSG & CMD

Select & N-Byte-MSG & CMD

Select & 1-MSG

3

4

5

Select & N-Byte-MSG

Send N-Byte-MSG

6

7

Send N-Byte-CMD

8

Receive N-Byte-MSG

45

MB86604L

(2) Discrete commands

No

Command code

Operand (for program)

Command name

9

08H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

—

Select

10 09H

11 0AH

12 0BH

13 0CH

14 0DH

15 10H

16 11H

17 12H

18 13H

19 14H

20 15H

21 16H

22 17H

23 18H

24 19H

25 1AH

26 1BH

27 1CH

Select with ATN

Set ATN

Reset ATN

Set ACK

Reset ACK

Send Data from MPU

Send Data from DMA

Receive Data to MPU

Receive Data to DMA

Send DATA from MPU Padding

Send DATA from DMA Padding

Receive Data to MPU Padding

Receive Data to DMA Padding

Send 1-MSG

0 Address of MSG sent

1 Address of MSG sent

0 SAVE address of MSG

1 Address of CMD sent

Send 1-MSG with ATN

Receive MSG

Send CMD

0 SAVE address of STATUS Receive STATUS

46

MB86604L

2. Target Commands

(1) Sequential commands

No

1

Command code

Operand (for program)

(not possible)

Command name

Reselect & 1-MSG

20H

21H

22H

23H

24H

25H

26H

27H

28H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

Reselect & N-Byte-MSG

Reselect & 1-MSG & Terminate

Reselect & 1-MSG & Link-Terminate

Terminate

3

4

5

6

Link-Terminate

7

Disconnect-Sequence

8

Send N-Byte-MSG

9

Receive N-Byte-CMD

10 29H

11 2AH

12 2BH

13 2CH

Receive N-Byte-MSG

Reselect & N-Byte-MSG & Terminate

Reselect & N-Byte-MSG & Link-Terminate

Disconnect-Sequence 2

47

MB86604L

(2) Discrete commands

No

Command code

Operand (for program)

Command name

14 30H

15 31H

16 32H

17 33H

18 34H

19 35H

20 36H

21 37H

22 38H

23 39H

24 3AH

25 3BH

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

—

Reselect

Set REQ

Reset REQ

Disconnect

Send Data from MPU

Send Data from DMA

Receive Data to MPU

Receive Data to DMA

Send 1 MSG

0 Address of MSG sent

1 SAVE address of MSG

0 Send-status address

1 SAVE address of CDB

Receive MSG

Send Status

Receive CMD

3. Common Commands

No

1

Command code

Operand (for program)

Command name

40H

41H

42H

43H

44H

45H

46H

47H

48H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(not possible)

SOFTWARE RESET

TRANSFER RESET

SCSI RESET

2

3

4

SET UP REG

5

INIT DIAG START

TARG DIAG START

DIAG END

6

7

8

COMMAND PAUSE

SET RST

9

10 49H

RESET RST

48

MB86604L

4. Programmable Commands

The user program is stored in the user program memory and begins operation when the user program head address

is written in the command register.

Programmable commands are composed of discrete and special commands and have a command length of one

(1) or two (2) bytes.

• Command field assign

Command type

Command code (1st byte)

Operand (2nd byte)

Message, command, or status phases

send command

Memory address of the data to be sent.

Message, command, or status phases

receive command

Memory address of received data being

stored.

Discrete commands

Data phase receive/send command or

do not perform transfer command

—

Data for AND operation or memory

address of data for AND operation.

AND command

Data for AND operation or memory

address of data for AND operation.

TEST AND command

Data for COMPARE operation or

memory address of data for COMPARE

operation.

COMPARE command

Special commands

Conditional branch command

MOVE command

Jump head address

Memory address to be moved.

User status code

—

STOP command

NOP command

49

MB86604L

■ SYSTEM CONFIGURATION EXAMPLE

1. 80-Series, Separate Bus Type

MB86604L

Oscillation

circuit

RESET

circuit

CLK

RESET

DB7 to 0

DBP

MODE

INT

MPU

TMOUT

CS0

Address

decoder

ACK

ATN

CS1

A4 to A0

Address bus

REQ

MSG

C/D

I/O

D15 to D0

UDP

LDP

Data bus

BHE

RD

WR

DMD15 to 0

UDMDP

DMA bus

LDMDP

BSY

SEL

RST

DREQ

DACK

DMBHE

IORD

DATA

buffer

memory

DMA

controller

Address

IOWR

DMA0

TP

50

MB86604L

2. 80-Series, Common Bus Type

MB86604L

Oscillation

circuit

RESET

circuit

CLK

RESET

DB7 to 0

MODE

DBP

INT

MPU

TMOUT

CS1

CS0

Address

decoder

ACK

ATN

A4 to A0

Address bus

Data bus

REQ

MSG

C/D

I/O

D15 to D0

UDP

LDP

BHE

RD

WR

DMD15 to 0

UDMDP

DMA bus

LDMDP

BSY

SEL

RST

DREQ

DACK

DMBHE

IORD

DMA

controller

IOWR

DMA0

TP

51

MB86604L

3. 68-Series, Separate Bus Type

Oscillation

circuit

MB86604L

RESET

circuit

CLK

RESET

DB7 to 0

MODE

DBP

INT

MPU

TMOUT

A0

CS0

Address

decoder

ACK

CS1

ATN

A4 to A1

Address bus

REQ

D15 to D0

MSG

UDP

Data bus

LDP

C/D

R/W

I/O

UDS

LDS

DMD15 to 0

UDMDP

DMA bus

LDMDP

BSY

SEL

RST

DREQ

DACK

DATA

buffer

memory

DMA

controller

DMR/W

DMUDS

DMLDS

Address

DMA0

TP

52

MB86604L

4. 68-Series, Common Bus Type

MB86604L

Oscillation

circuit

RESET

circuit

CLK

RESET

DB7 to 0

DBP

MODE

INT

TMOUT

A0

MPU

CS1

CS0

Address

decoder

ACK

ATN

A4 to A1

Address bus

Data bus

REQ

MSG

C/D

I/O

D15 to D0

UDP

LDP

R/W

UDS

LDS

DMD15 to 0

UDMDP

DMA bus

LDMDP

BSY

SEL

RST

DREQ

DACK

DMA

controller

DMR/W

DMUDS

DMLDS

DMA0

TP

53

MB86604L

■ ORDERING INFORMATION

Part number

Package

Remarks

MB86604LPFV

100 pin Plastic LQFP

(FPT-100P-M05)

54

MB86604L

■ PACKAGE DIMENSION

100-pin Plastic LQFP

(FPT-100P-M05)

1.50−⁺0⁰.^.210⁰

.059 −⁺.^.0⁰⁰04⁸

16.00±0.20(.630±.008)SQ

(MOUNTING HEIGHT)

75

51

14.00±0.10(.551±.004)SQ

76

50

12.00

(.472)

REF

15.00

(.591)

NOM

Details of "A" part

0.15(.006)

INDEX

0.15(.006)

100

26

0.15(.006)MAX

0.40(.016)MAX

"B"

1

25

LEAD No.

"A"

0.50(.0197)TYP

0.18−⁺0⁰.^.003⁸

0.127 ⁺−0⁰.^.002⁵

.005−⁺.^.0⁰⁰01²

M

Details of "B" part

0.08(.003)

.007 −⁺.^.0⁰⁰01³

0.10±0.10

(.004±.004)

(STAND OFF)

0.50±0.20(.020±.008)

0.10(.004)

0~10˚

Dimensions in mm (inches)

C

1995 FUJITSU LIMITED F100007S-2C-3

55

MB86604L

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-88, Japan

Tel: (044) 754-3763

Fax: (044) 754-3329

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, U.S.A.

Tel: (408) 922-9000

Fax: (408) 432-9044/9045

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

63303 Dreieich-Buchschlag

Germany

Circuit diagrams utilizing Fujitsu products are included as a

means of illustrating typical semiconductor applications. Com-

plete information sufficient for construction purposes is not nec-

essarily given.

Tel: (06103) 690-0

Fax: (06103) 690-122

The information contained in this document has been carefully

checked and is believed to be reliable. However, Fujitsu as-

sumes no responsibility for inaccuracies.

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LIMITED

#05-08, 151 Lorong Chuan

New Tech Park

The information contained in this document does not convey any

license under the copyrights, patent rights or trademarks claimed

and owned by Fujitsu.

Singapore 556741

Tel: (65) 281-0770

Fax: (65) 281-0220

Fujitsu reserves the right to change products or specifications

without notice.

No part of this publication may be copied or reproduced in any

form or by any means, or transferred to any third party without

prior written consent of Fujitsu.

The information contained in this document are not intended for

use with equipments which require extremely high reliability

such as aerospace equipments, undersea repeaters, nuclear con-

trol systems or medical equipments for life support.

F9702

FUJITSU LIMITED Printed in Japan

56


型号：	MB86604LPFV
厂家：	FUJITSU
描述：	SCSI-II Protocol Controller (with single-ended driver/receiver) SCSI-II协议控制器（与单端驱动器/接收器）驱动器控制器
文件：	总56页 (文件大小：1238K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB86604LPFV [FUJITSU]

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