MB88111 [FUJITSU]
A/D Converter (With 24-Channel Input at 10-bit Resolution); A / D转换器（带24路输入10位分辨率）
| 型号： | MB88111 |
| 厂家： | 
FUJITSU |
| 描述： | A/D Converter (With 24-Channel Input at 10-bit Resolution) |
| 文件： | 总26页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-13106-2E
Linear IC Converter
CMOS
A/D Converter
(With 24-Channel Input at 10-bit Resolution)
MB88111
■ DESCRIPTION
The MB88111 is an analog-to-digital converter that converts its analog input to a 10-bit digital value and outputs it
as serial data.
The MB88111 employs a successive approximation method for A/D conversion. It has 24 input channels to be A/
D converted selectively by setting in an internal register.
Since the MB88111 can input and output 16-bit serial data in synchronization with the clock, it can be easily
connected to the serial I/O port in a 16-bit microcontroller.
■ FEATURES
• 24-channel analog input
• RC-type successive approximation system with a sample-and-hole circuit
• 10-bit resolution
• Conversion speed within 50 µs (at a system clock rate of 1 MHz)
• Digitally converted data output from the MSB
• Digitally converted data output as 16-bit serial data
• Clock-synchronous serial transfer system
• Internal extended serial interface
• Capable of triggering A/D conversion through an external pin
• Capable of input through an 8-channel port
• Serial data output format selectable using an external pin
• 10-bit monotonicity
• No missing code
• Power supply voltage ranging from 3.5 to 5.5 V
(Continued)
■ PACKAGES
44-pin, Plastic QFP
(FPT-44P-M11)
48 pin, Plastic SH-DIP
(DIP-48P-M01)
MB88111
(Continued)
• Operating temperature ranging from –40 to +50°C
• CMOS process
• Package options of 44-pin QFP and 48-pin SH-DIP
■ PIN ASSIGNMENT
(Top view)
33
32
31
30
29
28 27
26
25
24
23
AN7
AN6
AN5
AN4
AN3
34
35
36
37
38
22
21
20
19
18
AN19
AN20
AN21
AN22
AN23
AN2
AN1
39
40
17
16
AGND
AVRL
AN0
AVRH
AV CC
V CC
41
42
43
44
15
14
13
12
V SS
TESTI
N.C.
INDEX
MOD
1
2
3
4
5
6
7
8
9
10
11
(FPT-44P-M11)
(Continued)
2
MB88111
(Continued)
(Top view)
AN1
AN0
1
2
3
4
5
6
48
47
46
45
44
43
AN2
AN3
AN4
AN5
AN6
AN7
INDEX
AVRH
AV CC
V CC
N.C.
RSTX
SCK
7
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C.
8
AN8
CCLK
SIN
9
AN9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
N.C.
ESIN
SOT
ENDC
IRQX
ATGX
CS2X
CS1
N.C.
MOD
N.C.
AN19
AN20
AN21
AN22
AN23
TESTI
V SS
AVRL
AGND
(DIP-48P-M01)
3
MB88111
■ PIN DESCRIPTION
Pin no.
Symbol
I/O Circuit type
Descriptions
QFP
DIP
41 to 26 2 to 1, AN0 to AN15
I
F
Analog input pins. The pin to be subject to conversion
is selected by the command input through the SIN pin.
Also, a series of pins from AN16 to AN23 can be used
as a port input.
48 to 43,
41 to 34
25 to 18 33 to 31, AN16 to
29 to 25 AN23
G
A
12
19
MOD
I
I
Pin for selecting a serial data output mode:
“L”: Mode A for output from the SOT pin in
synchronization with the fall of the SCK signal.
“H”: Mode B for output from the SOT pin in
synchronization with the rise of the SCK signal.
11
10
17
16
CS1
CS2X
A
Input pins for selecting an extended serial interface
mode.
Setting the CS1 level to “H” and the CS2X level to “L”
enables A/D converted data transfer. Setting the CS1
level to “L” or the CS2X level to “H” clears the register
command without affecting A/D conversion. Serial
data input to the external extended serial input pin
ESIN is output to the SOT pin as it is. (See Section 7
“Extended Serial Interface” in “■ OPERATION.”)
4
10
SIN
I
B
Serial data input pin
This pin is a hysteresis input with a filter.
6
3
12
9
SOT
O
I
H
B
Serial data output pin
CCLK
System clock input pin
This pin is a hysteresis input.
2
9
8
SCK
I
I
B
C
Serial data transfer clock input pin
This pin is a hysteresis input with a filter.
15
ATGX
External trigger input pin. This pin incorporates a pull-
up resistor. The ATC command initiates A/D conversion
at the rise of the signal at this pin.
The pin is a hysteresis input.
8
7
14
13
IRQX
O
O
H
H
A/D conversion interrupt signal input pin. The signal
level becomes “L” upon completion of A/D conversion;
it becomes “H” upon reception of data to be converted.
ENDC
A/D conversion completion signal output pin. The
signal level becomes “H” upon completion of A/D
conversion; it becomes “L” upon reception of data to be
converted.
5
1
11
7
ESIN
I
I
A
D
Serial input extension input pin. When the CS1 level is
“L” or the CS2X level is “H,” data input to the ESIN pin
is output to the SOT pin as it is.
RSTX
Reset signal input pin. This pin incorporates a pull-up
resistor. Setting the signal level to “L” initializes the
internal circuit of the device.
This pin is a hysteresis input with a filter.
(Continued)
4
MB88111
(Continued)
Pin no.
Symbol
TESTI
I/O Circuit type
Descriptions
QFP
DIP
14
21
I
E
Test input pin. This pin incorporates a pull-down
resistor. Maintain the pin at “L” level during normal
use.
44
15
43
17
42
16
13
5
22
4
VCC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Digital circuit power supply pin
Digital circuit ground pin
VSS
AVCC
AGND
AVRH
AVRL
Analog circuit power supply pin
Analog circuit ground pin
24
3
Reference (high) voltage input pin
Reference (low) voltage input pin
Non-connection pin
23
6, 18, N.C.
20, 30,
42
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• CMOS input
B
• Hysteresis input
• CMOS input
C
• Input with pull-up resistor
• CMOS input
(Continued)
5
MB88111
(Continued)
Type
Circuit
Remarks
• Input with pull-up resistor
D
• Hysteresis input
• CMOS input
E
• Input with pull-down resistor
• CMOS input
F
• Analog input
G
• Analog input
• Hysteresis input
• CMOS input
H
• CMOS output
6
MB88111
■ BLOCK DIAGRAM
AV CC
AGND
AVRH
AVRL
10-bit D/A converter
AN0
Sample-and-hold
circuit
AN15
AN16
Successive
approximation register
Comparator
AN23
ENDC
IRQX
Control circuit
ATGX
SCK
ESIN
SIN
Command register
Data register
MOD
CS2X
CS1
Output
select
circuit
SOT
RSTX
TESTI
CCLK
V
CC
V
SS
7
MB88111
■ FUNCTIONAL DESCRIPTION
1. SC (Serial Command) Register (Reset status: 0000H)
The SC register contains an A/D converter command and an input channel identification. Accessing this register
after releasing it from the reset status activates the A/D converter.
Note that this register accepts setting even during A/D conversion.
Note also that input of a command to the register must take an interval of at least 4 CCLKs after input of the
previous command.
MSB
bf
LSB
be bd bc bb ba b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Command
Channel
Don't care
(1) Command bits
A string of command bitsselects an A/D converter command such as STOP. Setting a command during execution
of another command cancels the command currently being executed.
bf
be
bd
Command name
Function
Stops A/D conversion (if it is being executed) and
initializes the A/D converter. This command has the same
effect as RSTX.
0
0
0
STOP
Executes A/D conversion of the specified channel once.
(See Section 3 “STC (Standard Conversion) Command.”)
0
0
1
STC
0
0
1
1
0
1
—
—
Unused (*)
Unused (*)
No-op command. Input of this command during A/D
conversion does not affect operation. If followed by this
command, the ATC command can transfer converted data
while holding the NOP command.
1
1
0
0
0
1
NOP
ATC
The basic operation of this command is the same as that
of the STC command. The ATC command can leave the
A/D conversion start timing to the external trigger pin
ATGX. (See Section 4 “ATC (Auto Trigger Conversion)
Command.”)
1
1
1
1
0
1
—
—
Unused (*)
Unused (*)
* : These command settings cause the STOP command to be executed.
8
MB88111
(2) Channel select bits
A string of channel select bits selects the pin to be subject to A/D conversion. This bit string is enabled only for
the STC or ATC command.
bc
bb
ba
b9
b8
Pin to be selected
bc
bb
ba
b9
b8
Pin to be selected
0
0
0
0
0
AN0
1
0
0
0
0
AN16
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
0
0
0
1
AN1
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
AN2
AN3
AN4
1
1
1
0
1
1
1
0
0
1
0
0
1
0
1
AN23
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
0
1
0
Undefined (*1)
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
0
AN11
AN12
AN13
AN14
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
0
Port input AN16 to
AN23 (*2)
0
1
1
1
1
AN15
1
1
1
1
1
*1: These settings of the bit string cause the STOP command to be executed.
*2: This setting is enabled only for the STC command. (See Section 5 “Port Input Command.”)
If this setting is made for the ATC command, the STOP command is executed.
2. Data Output Format
Upon completion of A/D conversion, the ENDC pin level becomes “H” and the IRQX pin level becomes “L.”
Execution of serial transfer at this time outputs data in the format illustrated below. The data output timing can
be selected by the MOD pin between the falling edge (mode A) or rising edge (mode B) of the SCK signal.
When the ENDC pin level is “L,” 0000H is output.
MSB
Bf Be Bd Bc Bb Ba B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Converted data A/D converted pin
LSB
ENDC
ENDC (A/D conversion completion flag): This bit is set to “1” upon completion of A/D conversion. It is set to
“0” upon completion of serial transfer.
Note: SCK input upon low-to-high transition of the ENDC pin level should be avoided. Otherwise, data may not
be output correctly.
9
MB88111
3. STC (Standard Conversion) Command
Input of the STC command executes A/D conversion of the specified channel once.
Impletion of A/D conversion, the ENDC signal rises while the IRQX signal falls. Clock input to the SCK pin after
A/D conversion outputs data to the SOT pin. Upon completion of data output, the ENDC signal falls while the
IRQX signal rises. If the next command is STOP or NOP, the A/D conversion is terminated. If the STC command
is input during A/D conversion, the command currently being executed is cancelled and the STC command is
executed.
• Example of STC command execution (1)
STC command input during A/D conversion cancels the current command and executes A/D conversion of the
new specified channel. Output data at this time is 0000H.
16 Cycle
SCK
AN0
AN1
AN2
SIN
STOP
Data 2
0000H
Data 0
0000H
SOT
ENDC
IRQX
A/D
AN0 conversion
AN1 conversion
AN2 conversion
• Example of STC command execution (2)
NOP command input during A/D conversion does not affect operation. Output data at this time is 0000H. If A/
D conversion is completed during NOP command input, the ENDC and IRQX pin levels become “H” and “L”
respectively upon completion of the NOP command input.
16 Cycle
SCK
SIN
AN3
NOP
NOP
AN4
NOP
STOP
Data 4
SOT
ENDC
IRQX
A/D
0000H
0000H
Data 3
0000H
0000H
AN3 conversion
AN4 conversion
10
MB88111
4. ATC (Auto Trigger Conversion) Command
The ATC command is the same as the STC command in basic operation. This command can initiates A/D
conversion using the external trigger pin ATGX. The external trigger signal is sampled by 1 µs clock and filtered
by 1 clock. The external trigger signal input during A/D conversion is ignored. If the next command is the STOP
command, A/D conversion is terminated. If it is the NOP command, the ATC command is executed continuously.
The channel cannot be changed at this time. To change the channel, input the ATC command to that effect.
• Example of ATC command execution (1)
NOP command input during A/D conversion enables the same channel to be A/D converted.
An attempt to set the ATGX signal low during A/D conversion is ignored.
NOP command input during A/D conversion does not affect operation. Output data at this time is 0000H.
16 Cycle
SCK
SIN
AN5
NOP
AN6
NOP
STOP
Data 6
0000H
Data 5
Data 5
0000H
SOT
ENDC
IRQX
ATGX
AN5 conversion
AN5 conversion
AN6 conversion
A/D
• Example of ATC command execution (2)
Setting the ATGX signal low again after A/D conversion restarts A/D conversion.
In data output mode B, however, do not use the ATC command in this way, or data will not be output correctly.
If A/D conversion is completed during NOP command input, the ENDC and IRQX pin levels become “H” and
“L” respectively upon completion of the NOP command input.
16 Cycle
SCK
SIN
AN7
AN8
NOP
STOP
Data 8
SOT
ENDC
0000H
Data 7
0000H
IRQX
ATGX
AN7
AN7 conversion
AN7 conversion
AN8 conversion
conversion
A/D
11
MB88111
5. Port Input Command
The port input command executes I/O evaluation of 8-channel inputs from the AN16 to AN23 pins at a prescribed
threshold in 10 clock cycles and outputs the results as port input data. The processing sequence is activated
each time port input is selected by the STC command. Port input data is output in the following format:
MSB
Bf Be Bd Bc Bb Ba B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Evaluation data “0” “1”
LSB
ENDC
Evaluation data:
The evaluation values of AN23 to AN16 are output to bits Bf to B8.
Evaluation value
“H”: Vin ≥ 0.8 x Vcc
“L”: Vin ≤ 0.2 x Vcc
ENDC (A/D completion flag):
This bit is set to “1” upon completion of A/D conversion. It is set to “0” upon completion of serial transfer.
• Example of STC command execution (3) (Port input command)
16 Cycle
10 Cycle
16 Cycle
SCK
SIN
CH9
STOP
Data 9
SOT
ENDC
IRQX
0000H
AN16
to
AN23
Evaluation
A/D
12
MB88111
6. Serial Output Select Function
The MB88111 can select the serial data output timing between the rising edge or falling edge of the clock signal
according to the setting of the MOD pin.
Mode A (MOD = “L”)
SCK
MSB
MSB
LSB
Bf Be Bd Bc Bb Ba B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
SOT
SIN
LSB
b4 b3 b2 b1 b0
bf
be bd bc bb ba b9 b8 b7 b6 b5
Serial data is output at the falling edge of the SCK signal.
Note: A/D converted data is not guaranteed if the MOD pin is switched when the ENDC signal is active. Before
changing the output mode, make the ENDC inactive or set the RSTX pin level to “L” after switching the
MOD pin.
Mode B (MOD = “H”)
SCK
MSB
LSB
Bf Be Bd Bc Bb Ba B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
SOT
SIN
MSB
LSB
b4 b3 b2 b1 b0
bf
be bd bc bb ba b9 b8 b7 b6 b5
Serial data is output at the rising edge of the SCK signal.
Note: A/D converted data is not guaranteed if the MOD pin is switched when the ENDC signal is active. Before
changing the output mode, make the ENDC inactive or set the RSTX pin level to “L” after switching the MOD
pin. The first bit is output when the ENDC signal becomes “H.”
7. Extended Serial Interface
The MB88111 can select whether to output A/D converted data or to output data input to the ESIN pin by
controlling the CS1 and CS2X pins.
CS1
H
CS2X
SOT pin
L
L
A/D converted data
L
L
H
H
Connection to the ESIN pin
H
Note: A/D converted data is not guaranteed if the CS1 or CS2X setting is changed during SCK input.
13
MB88111
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AGND = 0 V)
Ratings
Max.
+7.0
Parameter
Symbol
Conditions
Unit
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
—
VCC
AVCC
AVRH
VIN
V
V
Power supply voltage
+7.0*
+7.0*
Based on VSS
(Ta = +25°C)
V
Input voltage
VCC + 0.3
VCC + 0.3
150
V
Output voltage
VOUT
PD
V
Power consumption
Storage temperature
—
—
mW
°C
Tstg
–55
+150
* : VCC ≥ AVCC ≥ AVRH
2. Recommended Operating Conditions
Values
Parameter
Symbol
Unit
Min.
Max.
VCC
AVCC
3.5*
5.5*
0
V
V
VCC
AGND
0
Power supply voltage
AVRH
AVRL
Ta
AVCC × 0.8
AVCC
AVCC × 0.2
+105
V
V
0
Operation temperature
–40
°C
* : VCC ≥ AVCC ≥ AVRH
14
MB88111
3. DC Characteristics
(1) Digital section
(VCC = +3.5 V to +5.5 V, VSS = AGND = 0 V, Ta = –40°C to +105°C)
Value
Parameter
Pin name
Symbol
Conditions
Unit
Min.
Typ.
Max.
Power supply voltage
VCC
—
3.5
5.0
5.5
V
Operation at
CLK = 1 MHz
(with no load)
VCC
Power supply current
ICC
—
0.5
1.5
mA
MOD, CCLK
CS1, CS2X
SCK, ESIN
SIN
IIZL1
VIN = VSS
–2
—
2
µA
µA
Low-level input leakage
current
ATGX
RSTX
VIN = VSS
VCC = 5.0 V
IIZL2
–200
–100
–50
MOD, CCLK
CS1, CS2X
SCK, ESIN
SIN, ATGX
RSTX
High-level input leakage
current
IIZL1
VIN = VCC
–2
—
2
µA
MOD, ESIN
CS1, CS2X
VIL
VILS
VIH
—
—
—
—
VSS − 0.3
VSS − 0.3
0.7 VCC
—
—
—
—
0.3 VCC
0.2 VCC
V
V
V
V
Low-level input voltage
SCK, CCLK
SIN, ATGX
RSTX, *
MOD, ESIN
CS1, CS2X
VCC + 0.3
VCC + 0.3
High-level input voltage
Hysteresis width
SCK, CCLK
SIN, ATGX
RSTX, *
VIHS
0.8 VCC
SCK, CCLK
SIN, ATGX
RSTX, *
VHYS
—
0.02 VCC
—
0.3 VCC
V
Low-level output voltage SOT
IRQX
VOL
VOH
IOL = 2.5 mA
—
—
—
0.4
—
V
V
High-level output voltage
IOH = –400 µA
VCC − 0.4
ENDC
* : AN16 to AN23 (port input mode)
15
MB88111
(2) Analog section
(AVCC, VCC = +3.5 V to +5.5 V (VCC ≥ AVCC), VSS = AGND = 0 V, Ta = –40°C to +105°C)
Value
Parameter
Pin name
Symbol
Conditions
Unit
Min.
—
Typ.
10
Max.
—
Resolution
—
—
—
—
—
—
—
—
—
IA
—
bits
bits
Monotonic increase
Linearity error
—
—
10
—
—
—
—
±1
LSB
LSB
LSB
LSB
LSB
µs
Differential linearity error
Full-scale transition error
Zero-transition error
Total error
AN0 to AN23
—
—
—
±1
—
—
—
±1/2
±1/2
±2
—
—
—
—
—
—
Conversion time
Input clock frequency
Supply current
—
CCLK
AVCC
CCLK = 1 MHz
—
—
50
—
—
800
—
1000
3.0
1200
6.0
KHz
mA
Reference voltage supply
current
AVRH
IR
—
—
150
300
µA
AVRH
AVRL
—
—
—
—
—
—
0.8 AVCC
0
—
—
—
AVCC
0.2 AVCC
AVRH
V
V
V
Analog reference voltage
Analog input voltage
AVRL
AN0 to AN23
Multiplexer OFF-leakage
current
—
—
–200
—
200
nA
• No missing code is guaranteed.
Notes:• If the output impedance of the external input is too high, the analog voltage sampling time may be
insufficient.
• In the power-on sequence, turn the power supply for the digital system first before turning that for the
analog system on.
Analog input equivalent circuit
Analog input
Comparator
R ON1
R ON2
C 0
RON1 =About 1.5 kΩ
RON2 =About 1.5 kΩ
C0 =About 15 pF
Note: The above values are reference values.
16
MB88111
4. AC Characteristics
Parameter
(AVCC, VCC = +3.5 V to +5.5 V (VCC ≥ AVCC), VSS = AGND = 0 V, Ta = –40°C to +105°C)
Values
Symbol
Conditions
Unit
Min.
800
400
400
Max.
1200
—
CCLK clock cycle time
Low-level CCLK clock pulse width
High-level CCLK clock pulse width
CCLK clock rise time
CCLK clock fall time
fCLK
tCKL
tCKH
tCr
fCLK = 1/fCLK
KHz
ns
—
—
—
ns
—
–
10
ns
tCf
SCK clock cycle time
Low-level SCK clock pulse width
High-level SCK clock pulse width
SCK clock rise time
fSCK
tSKL
tSKH
tSr
tSCK = 1/fSCK
400
400
400
1200
—
KHz
ns
—
—
—
ns
—
–
10
ns
SCK clock fall time
tSf
SIN setup time
tSIS
tSIH
tCOM
tENR
tRSH
tRSS
—
50
250
4
—
—
—
1
ns
ns
µs
µs
ns
µs
SIN hold time
—
Command interval
CCLK = 1 MHz
ENDC reset time
See “Load conditions.”
–
RSTX pulse width
—
—
100
1
—
—
RSTX ↑ → SCK ↓ time
SCK ↑ → CS1 ↓ time
SCK ↑ → CS2X ↑ time
tCSS
tCSH
—
—
500
500
—
—
ns
ns
CS1 ↑ → SCK ↓ time
CS2X ↓ → SCK ↓ time
SOT output delay time (mode A)
SOT output delay time (mode B)
ENDC ↑ → SOT output (mode B)
STC command A/D conversion time
ATC command A/D conversion time
ATGX setup time
tSODA
tSODB
tSOHB
tSTC
See “Load conditions.”
See “Load conditions.”
See “Load conditions.”
CCLK = 1 MHz
CCLK = 1 MHz
CCLK = 1 MHz
CCLK = 1 MHz
CCLK = 1 MHz
—
—
—
—
—
—
4
300
300
200
50
ns
ns
ns
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
tSATC
tSATS
tSATH
tPOT
tPTS
50
—
ATGX hold time
2
—
Port input evaluation time
Port input setup time
—
0
10
—
Port input hold time
tPTH
—
0
—
Extended serial HL propagation delay
Extended serial LH propagation delay
Noise filter width
tSHL
See “Load conditions.”
See “Load conditions.”
—
—
—
15
100
100
—
tSLH
tINF
17
MB88111
AC Test Condition
Measurement point
C L = 50 pF
■ TIMING DIAGRAM
1. Input Clock Timing
t CLK
t CKH
CCLK
t Cf
t CKL
t Cr
t SCK
t SKH
SCK
t Sf
t SKL
t Sr
Evaluation levels are 80% and 20% of the VCC.
18
MB88111
2. Serial Data Input Timing
t RSH
RSTX
SCK
t RSS
t COM
t CSS
t CSH
CS1
(CS2X)
t SIS
t SIH
b0
bf
be
SIN
t ENR
ENDC
Evaluation levels are 80% and 20% of the VCC.
3. Serial Data Output Timing
Mode A
SCK
t SODA
SOT
Bf
Be
Evaluation levels are 80% and 20% of the VCC.
SCK
SOT
Mode B
t SODB
Bf
Be
t SOHB
ENDC
Evaluation levels are 80% and 20% of the VCC.
19
MB88111
4. A/D Conversion and Port Input Evaluation
STC command (normal mode)
SCK
SIN
b0
t STC
ENDC
Evaluation levels are 80% and 20% of the VCC.
ATC command
SCK
b0
SIN
t ATS
t ATH
ATGX
t ATC
ENDC
Evaluation levels are 80% and 20% of the VCC.
20
MB88111
STC command (port input mode)
SCK
SOT
b0
t PTS
AN16
to
AN23
t POT
t PTH
ENDC
Evaluation levels are 80% and 20% of the VCC.
5. Extended Serial Interface
ESIN
SOT
t SHL
t SLH
Evaluation levels are 80% and 20% of the VCC.
6. Noise Filter
t INF
t INF
Evaluation levels are 80% and 20% of the VCC.
21
MB88111
■ DEFINITIONS OF A/D CONVERTER TERMS
• Resolution
Analog transition identifiable by the A/D converter
• Linearity error
Deviation of the straight line drawn between the zero transition point (00 0000 0000 ↔ 00 0000 0001) and
the full-scale transition point (11 1111 1110 ↔ 11 1111 1111) of the device from actual conversion charac-
teristics
• Differential linearity error
Deviation from the ideal input voltage required to shift output code by one LSB
• Total error
Difference between actual and logical values. This error is caused by a zero transition error, full-scale transition
error, linearity error, quantum error, and by noise.
Ideal I/O characteristics
Total error
3FF
3FE
3FD
3FF
3FE
3FD
Actual conversion
characteristics
1.5 LSB
{1 LSB×(N–1) +0.5 LSB}
VFST
(Ideal value)
VOT
(Ideal value)
004
003
002
001
004
003
002
001
VNT
'
(Measured value)
Actual conversion
characteristics
1 LSB
Ideal characteristics
(Ideal value)
0.5 LSB
AVRL
AVRH
AVRL
AVRH
Analog input
Analog input
VNT'– {1 LSB × (N–1) +0.5 LSB}
AVRH–AVRL
1024
Total error of
digital output N
=
1 LSB (Ideal value) =
[v]
[v]
1 LSB
V OT (Ideal value) = 0.5 LSB
[v]
V FST (Ideal value) = AVRH - 1.5 LSB
(Continued)
22
MB88111
(Continued)
Zero transition error
Full-scale transition error
Ideal characteristics
004
Actual conversion
characteristics
3FF
3FE
Actual conversion
characteristics
003
002
001
VFST
'
(Measured value)
Actual conversion
characteristics
3FD
3FC
Actual conversion
characteristics
VOT'(Measured value)
AVRL
AVRH
Analog input
Analog input
VOT'–0.5 LSB
1 LSB
VFST' – (AVRH–1.5 LSB)
1 LSB
Zero transition error =
Full scale transition error =
Linearity error
Differential linearity error
Ideal characteristics
3FF
3FE
3FD
Actual conversion
characteristics
N+1
{1 LSB× (N–1)+VOT'}
Actual conversion
characteristics
VFST
'
N
N - 1
N - 2
(Measured
value)
VNT
'
004
003
002
001
(Measured
value)
Actual conversion
characteristics
V(N + 1)T
(Measured
value)
'
VNT
'
(Measured
value)
Ideal characteristics
Actual conversion
characteristics
VOT'(Measured value)
AVRL
AVRH
AVRL
AVRH
Analog input
Analog input
V(N+1)T'–VNT
'
VNT'– {1 LSB'× (N–1)+V OT'}
Linearity error of
digital output N
Differential linearity
error of digital output N
=
=
–1
1 LSB'
1 LSB'
VFST'– VOT
1022
'
1 LSB' =
[V]
23
MB88111
■ ORDERING INFORMATION
Part number
Package
Remarks
44-pin, Plastic QFP
(FPT-44P-M11)
MB88111PFQ
48-pin, Plastic SH-DIP
(DIP-48P-M01)
MB88111P-SH
24
MB88111
■ PACKAGE DIMENSIONS
44-pin, Plastic QFP
(FPT-44P-M11)
14.40±0.40SQ
(.567±.016)
2.35(.093)MAX
(Mounting height)
10.00±0.20SQ
(.394±.008)
0.05(.002)MIN
(STAND OFF)
33
23
Details of "A" part
34
22
0.15(.006)
8.00
(.315)
REF
0.20(.008)
11.60±0.30
(.457±.012)
INDEX
0.18(.007)MAX
0.53(.021)MAX
"A"
44
12
Details of "B" part
1
11
LEAD No.
0.80(.0315)TYP
0.15±0.05
(.006±.002)
0.30±0.10
(.012±.004)
M
0.16(.006)
0~10°
"B"
1.40±0.30
(.055±.012)
0.10(.004)
C
Dimensions in mm (inches).
1994 FUJITSU LIMITED F44018S-1C-1
48-pin, Plastic SH-DIP
(DIP-48P-M01)
+0.20
43.69–0.30
+.008
1.720–.012
INDEX-1
INDEX-2
13.80±0.25
(.543±.010)
0.51(.020)MIN
5.25(.207)
MAX
0.25±0.05
(.010±.002)
3.00(.118)
MIN
+0.50
1.00 –0
0.45±0.10
(.018±.004)
15.24(.600)
+.020
TYP
15°MAX
.039–0
1.778±0.18
(.070±.007)
1.778(.070)
MAX
40.894(1.610)REF
Dimensions in mm (inches).
C
1994 FUJITSU LIMITED D48002S-3C-3
25
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: (044) 754-3329
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9703
FUJITSU LIMITED Printed in Japan
相关型号：
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