GPL169251A-NnnV-C [GENERALPLUS]
16-bIT LCD Controller with 2368 Dots Driver and USB Interface;
| 型号： | GPL169251A-NnnV-C |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 16-bIT LCD Controller with 2368 Dots Driver and USB Interface CD |
| 文件： | 总19页 (文件大小：1721K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-bIT LCD Controller with 2368 Dots
Driver and USB Interface
Dec. 19, 2013
Version 1.3
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPL169251A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3
2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3
3. FEATURES.................................................................................................................................................................................................. 3
4. APPLICATION FIELD.................................................................................................................................................................................. 3
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 4
5.1. PAD ASSIGNMENT .................................................................................................................................................................................. 6
5.2. PIN MAP................................................................................................................................................................................................ 7
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 8
6.1. CPU ..................................................................................................................................................................................................... 8
6.2. MEMORY ............................................................................................................................................................................................... 8
6.3. PLL, CLOCK, POWER MODE................................................................................................................................................................... 8
6.4. POWER SAVING MODE ........................................................................................................................................................................... 8
6.5. LCD CONTROLLER ................................................................................................................................................................................ 8
6.6. USB DEVICE FUNCTION......................................................................................................................................................................... 9
6.7. LOW VOLTAGE DETECTION AND LOW VOLTAGE RESET............................................................................................................................. 9
6.8. INTERRUPT............................................................................................................................................................................................ 9
6.9. I/O........................................................................................................................................................................................................ 9
6.10.ADC (ANALOG TO DIGITAL CONVERTER)............................................................................................................................................... 10
6.11.DAC ................................................................................................................................................................................................... 10
6.12.TIMER/COUNTER ................................................................................................................................................................................. 10
6.13.POWER SAVING, WAKEUP AND WATCHDOG ............................................................................................................................................11
6.14.UART ..................................................................................................................................................................................................11
6.15.SERIAL PERIPHERAL INTERFACE(SPI)................................................................................................................................................... 12
6.16.AUDIO ALGORITHM............................................................................................................................................................................... 12
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 13
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 13
7.2. DC CHARACTERISTICS (TA = 25℃) ...................................................................................................................................................... 13
8. APPLICATION CIRCUITS......................................................................................................................................................................... 15
8.1. APPLICATION CIRCUIT - (1)................................................................................................................................................................... 15
9. PACKAGE/ORDERING INFORMATION................................................................................................................................................... 16
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 16
9.2. PACKAGE INFORMATION ....................................................................................................................................................................... 16
10.DISCLAIMER............................................................................................................................................................................................. 18
11. REVISION HISTORY ................................................................................................................................................................................. 19
© Generalplus Technology Inc.
Proprietary & Confidential
2
Dec. 19, 2013
Version: 1.3
GPL169251A
16-BIT LCD CONTROLLER WITH
2368 DOTS DRIVER AND USB
INTERFACE
1. GENERAL DESCRIPTION
3. FEATURES
The GPL169251A, a 16-bit architecture LCD controller product,
carries the Sunplus’ newest 16-bit microprocessor, μ’nSP
(pronounced as micro-n-SP) and also has LCD driver built-in.
The high processing speed assures the μ’nSP™ is capable of
handling complex digital signal processes easily and rapidly. The
GPL169251A is applicable to the areas of digital sound processing.
In addition, Liquid Crystal Display (LCD) capability strengthens the
GPL169251A to be used in variety of visual applications. The
memory capacity includes 4K-word SRAM for system usage and
592-word SRAM for LCD frame buffer and 256K-word flash. The
GPL169251A offers the single-chip solution with built-in driver in
which the resolution can be up to 32 x 74. The USB device
function is also supported to provide high-speed interface. Other
features include 8 programmable multi-functional I/Os, three 16-bit
timers/counters, 32768Hz Real Time Clock, Low Voltage
Reset/Detection and many others.
Built-in 16-bit μ’nSP 1.3 microprocessor
─ 256K-word flash
─ 4K-word SRAM
─ 592-word SRAM for LCD frame buffer
─ CPU clock: Max. 48MHz
─ 19 INT sources can be selected as IRQ or FIQ
Three power saving modes:
Standby mode/Halt mode/Wait mode
Max. 20μA @ 3.6V in Standby mode
Max. 30μA @ 3.6V in Halt mode(without LCD display)
Max. 180μA @ 3.6V in Halt mode(with mono LCD display)
Max. 2mA @ 3.6V in Wait mode
Supports USB 2.0 full-speed (12MHz) compliant device with
built-in transceiver
Programmable LCD driver
─ Up to 74 segments, up to 32 commons, maximum 2368 dots
Unused commons and segments can be set as I/O
─ 1/3~1/7 bias, 1/4, 1/6, 1/8,1/12, 1/16, 1/18, 1/32 duty
─ Adjustable LCD voltage (32 level)
2. BLOCK DIAGRAM
─ 592 words dedicated LCD RAM
─ Selectable black/white or 16-gray display
592W
SRAM
4KW
SRAM
16-bit
u'nSP
and
ICE
controller
Built-in 12-bit ADC with AGC
LCD Controller
Driver
COM0~3
SEG0~47
ICECLK
ICESDA
256KW
FLASH
Asynchronous serial interface (UART)
Supports SPI interface
Memory
Controller
SPI
Three 16-bit timers/counters
VCOIN
X32I
CPU
Clock
RTC
PLL
Two-channel 16-bit DAC audio outputs
Maximum up to 37 general I/Os (8 dedicate I/Os, 29 shared
with commons/segments)
X32O
Timer/Counter
USBON
IOA[7:0]
IOB[2:0]
IOC[15:0]
IOD[9:0]
ROSC
GPIO
UART/IrDA
DAC
Key wakeup/interrupt function
AUDA
AUDB
DP
DN
PLL feature for system clock
USB Interface
12-bit ADC
32768Hz Real Time Clock (RTC)
Low voltage reset and low voltage detection
Watchdog, system bus/address error reset
Software-based audio processing
LVD/LVR
WatchDog
ADINA
ADINB
Int. Controller
NOTE: PB[2:0] shared with VMIC/ADINA/ADINB; PC[15:0] shared with
COM[31:16]; PD[9:0] shared with COM[73:64]
4. APPLICATION FIELD
Advanced educational toys or ELAs
Handheld LCD game with sound synthesizer
© Generalplus Technology Inc.
Proprietary & Confidential
3
Dec. 19, 2013
Version: 1.3
GPL169251A
5. SIGNAL DESCRIPTIONS
Mnemonic
Pin No.
LQFP216 Type
Pin No.
Description
SEG[15:0]
156-131
191-176
O
LCD driver segment output
Can be shared with key scan port
LCD driver segment output
SEG[47:16]
17-2,
172-157
33-18
22-7,
207-192
38-23
O
SEG[63:48]
SEG[73:64]
O
O
LCD driver segment output
LCD driver segment output
34-43
48-39
SEG[73:64] also shared pins with PD[9:0]
LCD driver common output
COM[31:0]
IOA[7:0]
47-78
67-98
O
COM[31:16] also shared pins with PC[15:0]
IOA[7:0]: bi-directional I/O ports
79-82,
99-102,
150-153
I/O
118-121
IOA[7:0] can be software programmed to wakeup I/O pins and key strobe inputs
IOA[7] can be selected as Timer clock input or external interrupt input
IOA[6] can be selected as Timer input/output of CCP function
IOA[5:4] can be selected as UART RX/TX pins
IOA[3:1] can be selected as SPI interface signals SCK/SDO/SDI
External reset pin
RESETB
X6MON
127
130
172
175
I
I
This pin will control the ON/OFF of the 6MHz crystal and must be connected as
VDD or GND.
ICECLK
ICESDA
AUDA
129
128
84
174
173
I
I/O
O
O
I
ICE clock input pin
ICE data pin
116
Audio DAC output
AUDB
87
119
Audio DAC output
X32I
114
146
32768Hz crystal input
X32O
115
147
O
I
32768Hz crystal output
TEST
126
99, 100
102, 101
103
104
108
107
106
105
46, 173
1, 45
110
171
Test pin
CAP1P, CAP1N
CAP2P, CAP2N
VPP
131, 132
134, 133
135
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
O
O
A
LCD voltage generation. Charge pump capacitor interconnection pins
LCD voltage generation. Charge pump capacitor interconnection pins
LCD voltage generation
VLCD
136
VLCD highest voltage
V1
140
LCD bias voltage
V2
139
LCD bias voltage
V3
138
LCD bias voltage
V4
137
LCD bias voltage
VDDIO_33
VSSIO
66, 208
209, 65
142
Power supply voltage input
Ground reference
VDDANA_33
VSSANA
VDDAUD_33
VSSAUD
VDDC_33
VSSC
Power supply voltage input for analog circuit
Ground reference for analog circuit
Power supply voltage input for DAC
Ground reference for DAC
109
83
141
115
86
118
111
143
Power supply voltage input for core
Ground reference for core
113
145
VDDO_25
AVREF_DAC
MICP
112
144
Regulator output voltage for core
DAC reference voltage pin
85
117
93
125
Microphone differential input (positive)
© Generalplus Technology Inc.
Proprietary & Confidential
4
Dec. 19, 2013
Version: 1.3
GPL169251A
Mnemonic
Pin No.
LQFP216 Type
Pin No.
Description
MICN
92
98
124
130
A
Microphone differential input (negative)
VMIC
I/O
Output VDDADC when microphone enabled or used as GPIO
VMIC also shared pins with PB[2]
Microphone 1st amplifier output
Microphone 2nd amplifier input
AGC control pin
MICOUT
OPI
91
90
89
94
95
123
122
121
126
127
A
A
AGC
A
VADREF
ADINA
A
ADC reference pin
A/I
ADC input
ADINA also shared pins with PB[1]
ADC input
ADINB
96
128
A/I
ADINB also shared pins with PB[0]
Power supply voltage input for ADC
Ground reference for ADC
6MHz crystal input or RC filter connection for PLL
6MHz crystal output
VDDADC_33
VSSADC
X6MI
97
88
129
120
149
148
155
169
154
170
P
P
117
I
X6MO
116
O
I/O
I/O
P
DP
123
DP pin of USBPHY
DN
124
DN pin of USBPHY
VDDUSB_33
VSSUSB
NC
122
Power supply voltage input for USB
Ground reference for USB
Unused pin for user
125
P
44, 132,
134, 136,
138-139,
141, 143,
145-146,
148
Legend: I = Input, O = Output, P = Power
Total 163 pins
© Generalplus Technology Inc.
Proprietary & Confidential
5
Dec. 19, 2013
Version: 1.3
GPL169251A
5.1. Pad Assignment
Note1: To ensure the IC functions properly, please bond all of VDD and VSS pins.
Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible.
© Generalplus Technology Inc.
Proprietary & Confidential
6
Dec. 19, 2013
Version: 1.3
GPL169251A
5.2. Pin Map
NC
NC
1
2
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
NC
NC
NC
3
NC
NC
4
NC
NC
5
NC
6
NC
NC
7
NC
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
8
DP
9
VDDUSB_33
10
11
12
13
14
15
16
17
IOA0
IOA1
IOA2
IOA3
X6MI
X6MO
X32O
SEG40
SEG41
SEG42
SEG43
X32I
VSSC
VDDO_25
VDDC_33
VDDANA_33
VSSANA
V1
18
19
20
21
22
23
24
25
26
27
28
29
30
31
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
GPL169251A
V2
LQFP 216
V3
V4
VLCD
VPP
CAP2P
CAP2N
CAP1N
CAP1P
32
33
VMIC
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
VDDADC_33
ADINB
ADINA
VADREF
MICP
MICN
MICOUT
OPI
SEG65
SEG66
AGC
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
NC
VSSADC
AUDB
VSSAUD
AVREF_DAC
AUDA
VDDAUD_33
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
© Generalplus Technology Inc.
Proprietary & Confidential
7
Dec. 19, 2013
Version: 1.3
GPL169251A
6. FUNCTIONAL DESCRIPTIONS
6.1. CPU
6.3.1.2. 32768Hz RTC
The RTC, Real Time Clock, is normally used in watch, clock or
other time related products. A 2Hz-RTC (0.5 seconds) function is
featured in GPL169251A. The RTC counts the timing as well as
to wake CPU up whenever RTC occurs. The timing can be
traced by number of RTC occurrence. In addition, GPL169251A
supports 32768Hz oscillator in strong mode and auto mode. In
strong mode, 32768Hz OSC always runs at the highest power
consumption. In auto mode, however, it runs in strong mode for
the first 7.5 seconds and switches back to weak mode
automatically to save powers.
The GPL169251A is equipped with a 16-bit μ’nSP™, the newest
16-bit microprocessor by SUNPLUS and pronounced as
micro-n-SP. Eight registers are involved in μ’nSP™: R1 ~ R4
(General-purpose registers), PC (Program Counter), SP (Stack
Pointer), Base Pointer (BP) and SR (Segment Register). The
new version of μ’nSP™ 1.3 contains four secondary registers and
supports many DSP functions and bit-operation instructions.
The interrupts include three FIQs (Fast Interrupt Request) and
eight IRQs (Interrupt Request), plus one software-interrupt,
BREAK. Moreover, a high performance hardware multiplier with
the capability of FIR filter is also built in to reduce the software
multiplication loading. Besides, nested IRQ is also supported.
6.4. Power Saving Mode
The GPL169251A features three power saving modes: WAIT
mode, HALT mode, and STANDBY mode.
Wait
OFF
ON
Halt
OFF
OFF
ON
Standby
OFF
Phase Lock Loop
CPU
PLL
RTC
CPU Clock
32768Hz X'tal
(PLL)
OFF
6M/5.997MHz(default)
12M/11.993MHz
18M/17.990MHz
24M/23.986MHz
30M/29.983MHz
36M/35.979MHz
42M/41.976MHz
48M/47.972MHz
System Clock generator
ON
OFF
6.4.1. Wait mode
S2
S1
S0
In WAIT mode, only CPU is disabled. The PLL and RTC are still
active to keep LCD display function. After GPL169251A is
awakened from wait mode, the CPU will continue to execute the
program from the previous state.
System clock frequency selection
6.2. Memory
The GPL169251A contains 4KW SRAM, and also 592W dual-port
SRAM dedicated to support LCD display. The frame buffer is
capable of supporting maximum 32 x 74 16-gray display.
6.4.2. Halt mode
In HALT mode, both CPU and PLL are OFF and only RTC is
keeping active. After GPL169251A is awakened form Halt mode,
the CPU will execute the program from reset state.
6.3. PLL, Clock, Power Mode
6.3.1. PLL (Phase Lock Loop)
6.4.3. Standby mode
There are two PLLs built in GPL169251A to provide system clock.
If the USB function is enable, the 6MHz crystal must be connected
to provide the accurate 48MHz system clock and the slow PLL can
be disabled. The slow PLL generates the 5.997MHz clock from
32768Hz crystal and can be the clock source of the fast PLL.
While in STANDY mode, all modules are OFF to have the lowest
power consumption. In such mode, RAM and I/Os remain in the
previous states till CPU being awakened. The wakeup sources in
GPL169251A can be IOA/IOB/IOC/IOD. After GPL169251A is
awakened from standby mode, the CPU will execute the program
from reset state.
6.3.1.1. System clock
Basically, the system clock is provided by PLL to determine the
system clock frequency. The clock source could be selected
from 6MHz crystal or 32KHz crystal. The default CPU clock is
around 6MHz after reset. The CPU clock can be adjusted to
desired CPU clock by software.
6.5. LCD Controller
The GPL169251A contains a powerful LCD controller, which can
supports up to 16 gray levels for monochrome STN. With built-in
LCD driver function, GPL169251A provides a single-chip solution,
which supports maximum resolution to 32x74 with 16 gray levels.
© Generalplus Technology Inc.
Proprietary & Confidential
8
Dec. 19, 2013
Version: 1.3
GPL169251A
6.5.1. LCD Voltage Generation
32768HZ
To achieve highly integrated circuit and save external components
as possible, the GPL169251A has built-in charge pump circuit and
operational amplifiers to generate LCD’s bias voltages VLCD, V4,
V3, V2 and V1. The charge pump circuit can generate VPP
approx. to 8V. With VPP as power source, an operational
amplifier is further to provide LCD panel’s power supply, VLCD.
The level of VLCD can be adjusted by software. It is suggested
that VLCD must be higher than VDD by 0.7V; otherwise, abnormal
function will occur.
VDD
2.4V
Tw
RESET
Reset
Tw=32768HZ x 4 cycle
6.8. Interrupt
6.6. USB Device Function
The GPL169251A has 19 interrupt sources.
Some of the
The GPL169251A provides the device function which is
interrupt sources could be programmed as FIQ (Fast Interrupt
Request) or IRQ (Interrupt Request) individually. The priority of
FIQ is higher than IRQ. FIQ is the high-priority interrupt while
compatible with USB 2.0 full-speed standard.
An USB
transceiver is also built-in. There are five SRAMs in which sizes
are 64x8 for data transfer. The DMA is also supported for bulk-in
and bulk-out transfer to maximize the transfer performance.
IRQ is the low-priority one.
When IRQ and FIQ happen
simultaneous, IRQ has the lower priority than FIQ. So do
IRQ7~IRQ0. IRQ7 is the lowest priority interrupt.
Supports USB 2.0 full-speed (12MHz) compliant device with
built-in transceiver.
Interrupt Source
Audio ChannelA
Audio ChannelB
EXT1
Interrupt Group
FIQ/IRQ0
FIQ/IRQ0
FIQ/IRQ2
FIQ/IRQ3
FIQ/IRQ3
FIQ/IRQ3
FIQ/IRQ3
FIQ/IRQ4
FIQ/IRQ4
FIQ/IRQ4
FIQ/IRQ5
FIQ/IRQ5
FIQ/IRQ6
IRQ6
Priority
Highest
Highest
High
6.7. Low Voltage Detection and Low Voltage Reset
6.7.1. Low Voltage Detection (LVD)
The Low Voltage Detection (LVD) reports the circumstance of
present voltage. There are four LVD levels to be selected: 2.2V,
2.4V, 2.6V and 2.8V. Those levels can be programmed via
0x7009 (W). As an example, suppose LVD 2.8V is given. When
voltage drops below 2.8V, the b15 of 0x7009 is read as HIGH. In
such state, program can be designed to react this condition.
USB
High
DMA
High
UART
High
SPI
High
TimerC
High
TimerB
High
TimerA
High
6.7.2. Low Voltage Reset (LVR)
LCD Frame Pulse
Key Change
LVD
High
In addition to the LVD, the GPL169251A offers another important
feature, Low Voltage Reset (LVR). The level of LVR voltage is
2.4V. The LVR detects whether the power input of regulator is
below the voltage. With the LVR function, a reset signal is
generated to reset system when the operating voltage drops
below pre-determined voltage for four consecutive clock cycles.
Without LVR, the CPU becomes unstable and malfunctions when
the operating voltage drops below 2.4V. Using LVR, it will reset
all functions to the initial operational (stable) states when the
voltage drops below 2.4V. A LVR timing diagram is given as
follows:
High
High
Schedule
Time Base C
Time Base B
Time Base A
Alarm
Low
IRQ6
Low
IRQ7
Lowest
Lowest
Lowest
Lowest
IRQ7
IRQ7
RTC
IRQ7
6.9. I/O
Maximum four I/O ports are provided in GPL169251A: IOA, IOB,
IOC and IOD. In addition to regular IO function, all the I/Os are
shared with special function pins. The following diagram is an I/O
schematic.
© Generalplus Technology Inc.
Proprietary & Confidential
9
Dec. 19, 2013
Version: 1.3
GPL169251A
Clock of Source A Clock of Source B Clock of Source C
Buffer(R)
8192Hz
4096Hz
TMBB
8192Hz
Port_Data(W)
Port_Buffer(W)
Port_DIR(R/W)
Port_ATTR(R/W)
TMBA
4096Hz
Register
pull high
pull low
1
0
1
0
1
Pin pad
TimerB overflow
EXTA
0
Control
logic
EXTA
PWM service rate
PWM service rate
Data(R)
TimerA and TimerB can operate in timer mode, counter mode,
capture mode, compare mode and PWM mode. TimerC can
operate in timer mode and counter mode.
Although data can be written into the same register through
Port_Data and Port_Buffer, they can be read from different places,
Buffer (R) and Data (R). The IOA is software programmable for
key wakeup capability. To activate key wakeup function, latch
data on PORT_IOA_RL and enable the key wakeup function.
Wakeup is triggered when the IOA state is different from at the
time latched.
6.12.1. Timer mode
Initially, write a value of N into a timer and select a desired clock
source, timer will start counting from N, N+1, N+2…, through FFFF.
An INT (TimerA/ TimerB/ TimerC) signal is generated at the next
clock after reaching “FFFF” and the INT signal is transmitted to
INT controller for further processing. At the same time, N will be
reloaded into timer and start all over again. The clock source A is
a high frequency source and in contrast, clock source B is a low
frequency source. The combination of clock source A and B
forms a variety of speeds to TimerA. A “1” represents pass signal
and not gating. In contrast, “0” indicates deactivating timer.
6.10. ADC (Analog to Digital Converter)
The GPL169251A has three 12-bit A/D (Analog to Digital
Converter) channels; one is the microphone input channel and two
are line-in channels. The function of an A/D converter is to
convert analog quality signal, e.g. a voltage, into a digital word.
Or convert from an input source which can be line-in from
ADINA/ADINB or microphone input through amplifier and AGC
controller. The MIC amplifier circuit is capable of reducing
common mode noise by transmitting signals through MIC’s fully
differential input. Moreover, an external resistor can be applied to
adjust microphone gain and time of AGC operating. The AD
needs to select source of line-in before conversion. The ADC
chooses internal power (=AVDD) as top reference voltage.
6.12.2. Counter mode
The EXTA is the external clock source (shared with IOA[7]). The
external clock source can be divided by 1, 4 or 16 pre-scaler
divider and capable of selecting clock edge.
6.12.3. Capture mode
In capture mode, the content of timer/counter is stored in register
at the selected edge of pins CCP (special function of IOA[6]) by
the selected rate. It can be used to detect the pulse width of
CCP.
6.11. DAC
The GPL169251A features two 16-bit DACs and therefore superior
sound effect can be generated with less distortion.
6.12. Timer/Counter
6.12.4. Comparison mode
The GPL169251A has three 16-bit timers/counters: TimerA,
TimerB and TimerC. The clock source of TimerA comes from the
combination of clock source A and clock source B. In TimerB and
TimerC, the clock source is given from source C. When timer
overflows, an INT signal is sent to CPU to generate a time-out
signal.
In comparison mode, CCP will be programmed as output
automatically. The initial value is loaded from pre-load register
and after count to the pre-set value, hardware will set or clear
CCP or leave it unaffected. When timer/counter overflows, initial
value will not be reloaded but interrupt flag will be generated.
Clock of Source A Clock of Source B Clock of Source C
SYSCLK/2
SYSCLK/256
32768Hz
2048Hz
1024Hz
256Hz
SYSCLK/2
SYSCLK/256
32768Hz
© Generalplus Technology Inc.
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GPL169251A
6.12.5. PWM mode
TMBB, and TMBC. TMBA and TMBB can be clock source for
TimerA (clock source B). The TMBA and TMBB are the sources
for Interrupt (IRQ7) whereas TMBC is the source for interrupt
(IRQ6).
In PWM mode, the operation is similar to comparison mode except
that the initial value will reloaded whenever timer/counter overflow
is.
TMBC
128Hz
TMBB
8Hz
TMB1
Reserved
1Hz
Generally, the clock source A and C are fast clock sources and
source B comes from RTC system (32768Hz). Therefore, clock
source B can be utilized as a precise counter for time tracking,
e.g., the 2Hz clock can be used for real time tracking application.
256Hz
16Hz
512Hz
32Hz
2Hz
1024Hz
64Hz
4Hz
Default: 128Hz
Default: 8Hz
Default: 2Hz
6.12.6. Timebase
Timebase, generated by 32768Hz, is a combination of frequency
selections. The outputs of timebase module are named TMBA,
6.13. Power Saving, Wakeup and Watchdog
6.13.1. Power saving and Wakeup
6.13.2. Watchdog
1). Power saving: In GPL169251A, CPU has three power saving
mode, Wait/Halt/Standby mode. After reset, IC starts running
until a power saving signal occurs.
The purpose of watchdog is to monitor if the system operates
normally. Within a certain period of time, watchdog must be
cleared. If watchdog is not cleared, CPU assumes the program
has been running into an abnormal condition. As a result, system
or CPU will be reset according to register setting and the program
will be executed all over again. The watchdog function can be
disabled by software. In GPL169251A, the clear period can be
programmed from 62.5ms to 2 seconds (default). If watchdog is
cleared within the given time, the system or CPU will not be reset.
2). Wakeup: If any interrupt occurs, GPL169251A is awakened.
3). The following diagram shows the three conditions:
SYSTEM
RESET
Write
5xx5
to
To
clear
watchdog,
simply
write
“Axx5(h)”
to
$700C
Port_Watchdog_Clear(W).
The watchdog function remains
Wait
Normal
enabled during wait mode and halt mode where the 32768Hz is
still turned on.
Wakeup
Write
AxxA
to
Write
5xxA
to
$700E
6.14. UART
$700D
Halt
Standby
The UART module provides a full-duplex standard interface that is
able to communicate with other devices. With this interface,
GPL169251A can transmit and receive data simultaneously. The
maximum baud-rate can be up to 115200bps. This function can
be accomplished by using IOA and Interrupt (UART IRQ). The
Rx and Tx of UART are shared with IOA[5] and IOA[4]. The
UART has two 16-byte FIFOs to store transmitted and received
data. The UART status register will indicate if the FIFOs are
empty, half-full or full.
Wakeup
Wakeup
CPU
Reset
Note1: When GPL169251A enters Wait mode, any interrupt will wake up
GPL169251A. After GPL169251A is awakened, CPU continues to
execute next instruction.
Note2: When GPL169251A enters Halt or Standby mode, any interrupt will
awake GPL169251A. After GPL169251A is awakened, CPU will be
reset to initial state.
start
bit
parity
bit
stop
bit
D0
D1
D2
D3
D4
D5
D6
D7
1-bit Start
8-bit data
1-bit Stop
can be enabled/disable;
also even/odd check
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GPL169251A
6.15. Serial Peripheral Interface(SPI)
6.16. Audio Algorithm
The SPI interface is
a
master/slave interface that enables
The following speech types can be used in GPL169251A: PCM,
synchronous serial communication with peripherals. Two 16-byte
FIFOs are used for transmit and receive. Four modes with
programmable phase and polarity of master clock are also
supported.
LOG
PCM,
SACM_A1600,
SACM_S530,
SACM_1601,
SACM_S720,
SACM_S200,
SACM_S320,
SACM_S480,
SACM_S880,
SACM_DVR1800,
SACM_DVR520,
SACM_DVR1600, SACM_DVR4800, and SACM_DVR3200. For
melody synthesis, the GPL169251A provides a SACM_MS01 (FM
synthesizer) and SACM_MS02 wave-table synthesizer.
© Generalplus Technology Inc.
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Version: 1.3
GPL169251A
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
VDD
VIN
< 3.6V
Input Voltage Range
Operating Temperature
Storage Temperature
-0.5V to VDD + 0.5V
0℃ to +70℃
TA
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions
see AC/DC Electrical Characteristics.
7.2. DC Characteristics (TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
VDD
2.7
-
3.6
V
VDD = 3.6V, FOSC = 47.9232MHz,
The wait cycle of internal flash is 1
($704c.b3~b0)
Operating Current
IOP
-
-
40
-
-
mA
VDD = 3.6V, 32K X’tal ON,
The wait cycle of internal flash is 1
($704c.b3~b0), clock source OSC
1.2MHz.
Wait Current
IWAIT1
600
μA
LCD ON, FR=200Hz, no LCD panel
PLL OFF
VDD = 3.6V, 32K X’tal & RTC ON,
LCD OFF
Halt Current 1
IHALT1
-
-
20
-
-
μA
μA
VDD = 3.6V, 32K X’tal & RTC ON,
mono LCD ON
Halt Current 2
IHALT2
ISTB
100
Standby Current
-
3.00
3.19
3.48
0.7 VDD
-
-
-
-
-
-
-
20
6.0
μA
V
VDD = 3.6V, all off
VDD = 3.0V, 1/5 bias, no load
VDD = 3.0V, 1/6 bias, no load
VDD = 3.0V, 1/7 bias, no load
VDD = 3.0V
LCD Driver Voltage
VLCD
6.6
V
7.2
V
Input High Level
Input Low Level
VIH
VIL
-
V
0.3 VDD
V
VDD = 3.0V
VDD = 3.0V, VOH = 2.4V
IOA[7:0]
Output High Current
Output Low Current
IOH2
IOL2
RPL
RPH
-2.0
-
-
-
-
-
mA
mA
KΩ
KΩ
VDD = 3.0V, VOL = 0.8V
IOA[7:0]
-2.0
-
Input Pull-Low Resistor
(IOA)
VDD = 3.0V
-
-
100
100
V
IN = 3.0V
Input Pull-High Resistor
(IOA)
VDD = 3.0V
VIN = VSS
© Generalplus Technology Inc.
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GPL169251A
7.2.1. PLL Characteristics (TA = 25℃, VDD=3.0V, 6MHz crystal disable)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
VCO Operating Frequency
Input Reference Clock Freq
Output Clock Freq
Start-up Time
Fvco
Fref
11.993
-
95.945
MHz
Hz
-
32768
-
5.997
-
-
47.972
MHz
ms
ms
%
-
-
-
-
5
5
-
Lock-in Time
-
Jitter (cycle-cycle)
Duty Cycle
1.5
50
-
%
7.2.2. ADC Characteristics (TA = 25℃, VDD=3.0V)
Limit
Typ.
-
Characteristics
ADC Resolution
Symbol
Unit
Test Condition
Min.
Max.
RESO
SINDR
@fin=1KHz
VIN
-
12
Bits
dB
Signal-to-noise Ratio
+distortion
-
-
57
ADC Input Voltage
VSS
-
VDD
V
±4.0
INL(Integral Non-linearity)
DNL(Differential Non-linearity)
No Missing Code
INL
-
-
-
LSB
LSB
Bits
KHz
±0.8
DNL
-
10
-
11
-
-
AD Conversion Rate
FCONV
FCPU/512
7.2.3. DAC Characteristics (TA = 25℃, VDD=3.0V)
Limit
Characteristics
Resolution
Symbol
Unit
Test Condition
Min.
Typ.
Max.
-
-
16
-
192
0.8
-
Bits
KHz
Vdd
ohm
%
Input Data Sampling Freq.
Output Range
-
0.2
125
-
-
Output Loading
RLOAD
-
THD+N at FS
0.1(-60dB)
80
-
Dynamic Range
-
-
dB
7.2.4. OSC Characteristics (TA = 25℃, VDD=3.0V)
Limit
Typ.
32768
-
Characteristics
Symbol
Unit
Test Condition
Min.
-
Max.
Output Clock Frequency
Duty Cycle
CLK32768
-
Hz
%
40
50
10000x
T32768
Start-up Time
-
-
μs
© Generalplus Technology Inc.
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Version: 1.3
GPL169251A
8. APPLICATION CIRCUITS
8.1. Application Circuit - (1)
20pF*1
X32I
X32O
20pF*1
0.1
F
V4
V3
V2
V1
0.1
F
0.1
F
GPL169251A
0.1
F
RESETB
0.1
F
100K
VDDIO_33
F
F
F
F
F
F
47
47
47
47
VSSIO
*2
VDDUSB_33
0.1
0.1
0.1
0.1
0.1
F
F
F
F
F
VSSUSB
VDDC_33
VSSC
VDDO_25
VSSC
VDDAUD_33
0.47
47
VSSAUD
VDDANA_33
VSSANA
Note*1: These capacitor values are for design guidance only. We recommend user select the ESR < 35K as well as CL1=CL=20~30pF(including PCB
parasitic loading). Note that the environment humidity may affect the equivalent resistances on the two end points. To avoid the humidity effect, we
recommend user to apply 20pF(assume PCB parasitic loading is 6pF) on XI and XO. Note that a larger CL capacitance will cause a longer time for XTAL to
oscillate.
Note*2: These capacitor values are for design guidance only. The ratio of capacitance of CVPP to the capacitance of CAP1 and CAP2 is recommended to be
ten or more
© Generalplus Technology Inc.
Proprietary & Confidential
15
Dec. 19, 2013
Version: 1.3
GPL169251A
9. PACKAGE/ORDERING INFORMATION
9.1. Ordering Information
Product Number
Package Type
GPL169251A-NnnV-C
Chip form
GPL169251A-NnnV-QL17n
Halogen Free Package
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Note3: QL17n, QL17 is assigned for LQFP216, n is assigned for customer.
9.2. Package Information
9.2.1. LQFP216
Dimension in Millimeter
Symbol
Min.
Nom.
Max.
1.60
0.15
A
-
-
-
A1
0.05
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Version: 1.3
GPL169251A
Dimension in Millimeter
Nom.
Symbol
Min.
1.35
0.13
0.09
Max.
1.45
0.23
0.20
A2
b
1.40
0.18
c
-
D1
E1
24.00 BSC
24.00 BSC
0.40 BSC
26.00 BSC
26.00 BSC
0.60
e
□
D
E
L
0.45
0.75
L1
Y
1.00 REF
0.08
θ°
0°
3.5°
7°
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Version: 1.3
GPL169251A
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
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Dec. 19, 2013
Version: 1.3
GPL169251A
11. REVISION HISTORY
Date
Revision #
Description
Page
15
15
15
3
Dec. 19, 2013
Oct. 08, 2012
Oct. 04, 2011
1.3
1.2
1.1
Modify 8.1.Application Circuit.
Modify 8.1.Application Circuit.
Modify 8.1.Application Circuit and add notes.
1. Add description “USB 2.0 full-speed (12MHz) compliant device”
2. Add LQFP216 pin number and package information.
3. Modify LVR level.
7, 16
9
AUG. 21, 2008
1.0
4. Modify wait mode and halt mode current spec. and condition.
1. Modify section 2. BLOCK DIAGRAM.
2. Add IHALT2 to section 7.2 DC Characteristics.
Original
13
4
MAR. 13, 2008
NOV. 02, 2007
0.2
0.1
13
18
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