GPR25L25605F-HS12x [GENERALPLUS]
256M-bit [x 1/x 2/x 4] CMOS Serial Flash;
| 型号： | GPR25L25605F-HS12x |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 256M-bit [x 1/x 2/x 4] CMOS Serial Flash |
| 文件： | 总61页 (文件大小：1810K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPR25L25605F
256M-bit [x 1/x 2/x 4] CMOS Serial
Flash
Jan 21, 2013
Version 1.0
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPR25L25605F
Table of Contents
PAGE
1. FEATURES.................................................................................................................................................................................................. 4
1.1. GENERAL .............................................................................................................................................................................................. 4
1.2. SOFTWARE FEATURES ........................................................................................................................................................................... 4
1.3. HARDWARE FEATURES .......................................................................................................................................................................... 4
2. GENERAL DESCRIPTION.......................................................................................................................................................................... 4
3. PIN CONFIGURATIONS ............................................................................................................................................................................. 5
3.1. 8-PIN SOP (200MIL) ............................................................................................................................................................................. 5
4. PIN DESCRIPTION...................................................................................................................................................................................... 5
5. BLOCK DIAGRAM ...................................................................................................................................................................................... 6
6. DATA PROTECTION................................................................................................................................................................................... 7
7. MEMORY ORGANIZATION......................................................................................................................................................................... 9
8. DEVICE OPERATION................................................................................................................................................................................ 10
8.1. 256MB ADDRESS PROTOCOL ................................................................................................................................................................11
8.2. QUAD PERIPHERAL INTERFACE (QPI) READ MODE................................................................................................................................ 12
9. COMMAND DESCRIPTION ...................................................................................................................................................................... 13
9.1. COMMAND SET(TABLE 5) ..................................................................................................................................................................... 13
9.1.1. Read/Write Array Commands ................................................................................................................................................. 13
9.1.2. Read/Write Array Commands (4 Byte Address Command Set).............................................................................................. 14
9.1.3. Register/Setting Commands................................................................................................................................................... 14
9.1.4. ID/Security Commands........................................................................................................................................................... 16
9.1.5. Reset Commands ................................................................................................................................................................... 17
9.2. WRITE ENABLE (WREN)...................................................................................................................................................................... 17
9.3. WRITE DISABLE (WRDI) ...................................................................................................................................................................... 17
9.4. READ IDENTIFICATION (RDID) .............................................................................................................................................................. 18
9.5. RELEASE FROM DEEP POWER-DOWN (RDP), READ ELECTRONIC SIGNATURE (RES) ............................................................................. 18
9.6. READ ELECTRONIC MANUFACTURER ID & DEVICE ID (REMS) .............................................................................................................. 19
9.7. QPI ID READ (QPIID).......................................................................................................................................................................... 19
9.8. READ STATUS REGISTER (RDSR) ........................................................................................................................................................ 20
9.9. READ CONFIGURATION REGISTER (RDCR)........................................................................................................................................... 20
9.10.WRITE STATUS REGISTER (WRSR)...................................................................................................................................................... 25
9.11.ENTER 4-BYTE MODE (EN4B)............................................................................................................................................................... 27
9.12.EXIT 4-BYTE MODE (EX4B) .................................................................................................................................................................. 27
9.13.READ DATA BYTES (READ).................................................................................................................................................................. 27
9.14.READ DATA BYTES AT HIGHER SPEED (FAST_READ)........................................................................................................................... 27
9.15.DUAL OUTPUT READ MODE (DREAD).................................................................................................................................................. 28
9.16.2 X I/O READ MODE (2READ).............................................................................................................................................................. 28
9.17.QUAD READ MODE (QREAD) .............................................................................................................................................................. 28
9.18.4 X I/O READ MODE (4READ).............................................................................................................................................................. 29
9.19.4 BYTE ADDRESS COMMAND SET ......................................................................................................................................................... 29
9.20.BURST READ ....................................................................................................................................................................................... 30
9.21.PERFORMANCE ENHANCE MODE.......................................................................................................................................................... 30
9.22.PERFORMANCE ENHANCE MODE RESET............................................................................................................................................... 31
© Generalplus Technology Inc.
Proprietary & Confidential
2
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.23.FAST BOOT.......................................................................................................................................................................................... 32
9.24.SECTOR ERASE (SE)........................................................................................................................................................................... 33
9.25.BLOCK ERASE (BE32K)....................................................................................................................................................................... 33
9.26.BLOCK ERASE (BE) ............................................................................................................................................................................. 34
9.27.CHIP ERASE (CE)................................................................................................................................................................................ 34
9.28.PAGE PROGRAM (PP) .......................................................................................................................................................................... 35
9.29.4 X I/O PAGE PROGRAM (4PP)............................................................................................................................................................. 35
9.30.DEEP POWER-DOWN (DP) ................................................................................................................................................................... 36
9.31.ENTER SECURED OTP (ENSO) ........................................................................................................................................................... 36
9.32.EXIT SECURED OTP (EXSO)............................................................................................................................................................... 36
9.33.READ SECURITY REGISTER (RDSCUR) ............................................................................................................................................... 36
9.34.WRITE SECURITY REGISTER (WRSCUR) ............................................................................................................................................. 36
9.35.WRITE PROTECTION SELECTION (WPSEL)........................................................................................................................................... 37
9.36.ADVANCED SECTOR PROTECTION......................................................................................................................................................... 39
9.36.1. Lock Register...................................................................................................................................................................... 40
9.36.2. SPB Lock Bit (SPBLB)........................................................................................................................................................ 40
9.36.3. Solid Protection Bits ........................................................................................................................................................... 40
9.36.4. Dynamic Write Protection Bits............................................................................................................................................ 41
9.36.5. Gang Block Lock/Unlock (GBLK/GBULK).......................................................................................................................... 41
9.36.6. Sector Protection States Summary Table........................................................................................................................... 42
9.36.7. Password Protection Mode................................................................................................................................................. 42
9.37.PROGRAM/ERASE SUSPEND/RESUME................................................................................................................................................... 43
9.38.ERASE SUSPEND ................................................................................................................................................................................. 43
9.39.WRITE-RESUME................................................................................................................................................................................... 43
9.40.NO OPERATION (NOP)......................................................................................................................................................................... 43
9.41.SOFTWARE RESET (RESET-ENABLE (RSTEN) AND RESET (RST))......................................................................................................... 43
9.42.READ SFDP MODE (RDSFDP)............................................................................................................................................................ 44
10.RESET....................................................................................................................................................................................................... 49
11. POWER-ON STATE................................................................................................................................................................................... 50
12.ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 51
12.1.TABLE 13. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................. 51
12.2.TABLE14 CAPACITANCE TA = 25°C, F = 1.0 MHZ................................................................................................................................... 51
12.3.TABLE 15. DC CHARACTERISTICS................................................................................................................................................... 53
12.4.TABLE 16. AC CHARACTERISTICS ................................................................................................................................................... 54
13.OPERATING CONDITIONS ...................................................................................................................................................................... 55
13.1.INITIAL DELIVERY STATE ....................................................................................................................................................................... 56
14.ERASE AND PROGRAMMING PERFORMANCE.................................................................................................................................... 57
15.DATA RETENTION ................................................................................................................................................................................... 57
16.LATCH-UP CHARACTERISTICS ............................................................................................................................................................. 57
17.ORDERING INFORMATION ..................................................................................................................................................................... 58
18.PACKAGE INFORMATION....................................................................................................................................................................... 59
18.1.TITLE: PACKAGE OUTLINE FOR SOP 8L 200MIL (OFFICIAL NAME-209 MIL)............................................................................................. 59
18.1.1. Dimensions (Inch dimensions are derived from the original mm dimensions) ................................................................... 59
19.DISCLAIMER............................................................................................................................................................................................. 60
20.REVISION HISTORY................................................................................................................................................................................. 61
© Generalplus Technology Inc.
Proprietary & Confidential
3
Jan 21, 2013
Version: 1.0
GPR25L25605F
256M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH
1. FEATURES
1.1. General
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and 1-byte device
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• Single Power Supply Operation
ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
- 2.7 to 3.6 volt for read, erase, and program operations
• 256Mb: 268,435,456 x 1 bit structure or 134,217,728 x 2 bits (two
I/O mode) structure or 67,108,864 x 4 bits (four I/O mode)
structure
1.3. Hardware Features
• SCLK Input
• Protocol Support
- Serial clock input
- Single I/O, Dual I/O and Quad I/O
• SI/SIO0
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 2.3V to 2.5V
• Fast read for SPI mode
- Serial Data Input or Serial Data Input/Output for 2 x I/O read
mode and 4 x I/O read mode
• SO/SIO1
- Support clock frequency up to 133MHz for all protocols
- Serial Data Output or Serial Data Input/Output for 2 x I/O read
-
Support Fast Read, 2READ, DREAD, 4READ, QREAD
mode and 4 x I/O read mode
instructions.
• WP#/SIO2
- Configurable dummy cycle number for fast read operation
• Quad Peripheral Interface (QPI) available
• Equal Sectors with 4K byte each, or Equal Blocks with 32K byte
each or Equal Blocks with 64K byte each
- Any Block can be erased individually
• Programming:
- Hardware write protection or serial data Input/Output for 4 x I/O
read mode
• RESET#/SIO3
- Hardware Reset pin or Serial input & Output for 4 x I/O read
mode
• PACKAGE
- 256byte page buffer
-16-pin SOP (300mil)
- Quad Input/Output page program(4PP) to enhance program
performance
2. GENERAL DESCRIPTION
• Typical 100,000 erase/program cycles
• 20 years data retention
GPR25L25605F is 256Mb bits serial Flash memory, which is
configured as 33,554,432 x 8 internally. When it is in two or four
• GPR25L25605F is compatible with MX25L25635F
I/O mode, the structure becomes 134,217,728 bits
x 2 or
1.2. Software Features
67,108,864 bits x 4. GPR25L25605F feature a serial peripheral
interface and software protocol allowing operation on a simple
3-wire bus while it is in single I/O mode. The three bus signals
are a clock input (SCLK), a serial data input (SI), and a serial data
output (SO). Serial access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become
SIO0 pin and SIO1 pin for address/dummy bits input and data
output. When it is in four I/O read mode, the SI pin, SO pin, WP#
and RESET# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3
pin for address/dummy bits input and data output.
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bits define the size of the area to
be protected against program and erase instructions
- Advanced sector protection function (Solid and Password
Protect)
• Additional 4K bit security OTP
- Features unique identifier
The GPR25L25605F provides sequential read operation on whole
chip.
- factory locked identifiable, and customer lockable
• Command Reset
After program/erase command is issued, auto program/ erase
algorithms which program/ erase and verify the specified page or
sector/block locations will be executed. Program command is
executed on byte basis, or page (256 bytes) basis, or word basis
• Program/Erase Suspend and Resume operation
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
© Generalplus Technology Inc.
Proprietary & Confidential
4
Jan 21, 2013
Version: 1.0
GPR25L25605F
for erase command is executed on sector (4K-byte), block
(32K-byte), or block (64K-byte), or whole chip basis.
functions, please see security features section for more details.
When the device is not in operation and CS# is high, it is put in
standby mode.
To provide user with ease of interface, a status register is included
to indicate the status of the chip. The status read command can
be issued to detect completion status of a program or erase
operation via WIP bit.
The GPR25L25605F utilizes proprietary memory cell, which
reliably stores memory contents even after 100,000 program and
erase cycles.
Advanced security features enhance the protection and security
Table 1. Read Performance Comparison
Numbers
of Fast Read (MHz)
Dual Output Fast Quad Output Fast Dual IO Fast Read
Quad
IO
Fast
Dummy Cycles
Read (MHz)
Read (MHz)
(MHz)
Read (MHz)
4
6
-
-
-
84*
104
104
133
70
104
104*
133
104
104*
133
84
84*
104
133
8
104*
133
10
Note: *means default status
3. PIN CONFIGURATIONS
3.1. 16-PIN SOP (300mil)
4. PIN DESCRIPTION
Symbol
CS#
Description
Chip Select
SI/SIO0
Serial Data Input (for 1 x I/O)/ Serial Data
Input & Output (for 2xI/O or 4xI/ O read mode)
Serial Data Output (for 1 x I/O)/ Serial Data
Input & Output (for 2xI/O or 4xI/ O read mode)
Clock Input
SO/SIO1
SCLK
WP#/SIO2
Write protection: connect to GND or Serial
Data Input & Output (for 4xI/O read mode)
No Connection or Serial Data Input &
Output (for 4xI/O read mode)
NC/SIO3
RESET#*
VCC
Hardware Reset Pin Active low
+ 3V Power Supply
GND
Ground
NC
No Connection
Note: RESET# pin has internal pull up.
© Generalplus Technology Inc.
Proprietary & Confidential
5
Jan 21, 2013
Version: 1.0
GPR25L25605F
5. BLOCK DIAGRAM
© Generalplus Technology Inc.
Proprietary & Confidential
6
Jan 21, 2013
Version: 1.0
GPR25L25605F
6. DATA PROTECTION
During power transition, there may be some false system level
signals which result in inadvertent erasure or programming. The
device is designed to protect itself from these accidental write
cycles.
except Release from deep power down mode command (RDP)
and Read Electronic Signature command (RES), Erase/Program
suspend command, Erase/Program resume command and
softreset command.
The state machine will be reset as standby mode automatically
during power up. In addition, the control register architecture of
the device constrains that the memory contents can only be
changed after specific command sequences have completed
successfully.
• Advanced Security Features: there are some protection and
security features which protect content from inadvertent write and
hostile access.
I. Block lock protection
In the following, there are several features to protect the system
from the accidental write cycles during VCC power-up and
power-down or from system noise.
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0
and T/B) bits to allow part of memory to be protected as read
only. The protected area definition is shown as Table 2
Protected Area Sizes, the protected areas are more flexible
which may protect various area by setting value of BP0-BP3 bits.
- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect
the (BP3, BP2, BP1, BP0) bits and Status Register Write Protect
bit.
• Valid command length checking: The command length will be
checked whether it is at byte base and completed on byte
boundary.
• Write Enable (WREN) command: WREN command is required to
set the Write Enable Latch bit (WEL) before other command to
change data. The WEL bit will return to reset stage under
following situation:
- In four I/O and QPI mode, the feature of HPM will be disabled.
- Power-up
Table2. Protected Area Sizes
- Reset# pin driven low
Protected Area Sizes (TB bit = 0)
- WRDI command completion
Status bit
Protect Level
256Mb
- WRSR command completion
BP3 BP2 BP1 BP0
- PP/PP4B command completion
0
0
0
0
0
0
0
0
1
0
1
0
0 (none)
1 (1 block, protected block 511st)
(2 blocks, protected block
510th~511st)
- 4PP/4PP4B command completion
- SE/SE4B command completion
2
- BE32K/BE32K4B command completion
- BE/BE4B command completion
0
0
1
1
3
(4 blocks, protected block
- CE command completion
508th~511st)
- PGM/ERS Suspend command completion
- Softreset command completion
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
4
(8 blocks, protected block
504th~511st)
- WRSCUR command completion
5
(16 blocks, protected block
- WPSEL command completion
496th~511st)
- GBLK command completion
6
(32 blocks, protected block
- GBULK command completion
480th~511st)
- WREAR command completion
7
(64 blocks, protected block
- WRLR command completion
448th~511st)
- WRPASS command completion
8
(128 blocks, protected block
- RDPASS command completion
384th~511st)
- SPBLK command completion
9
(256 blocks, protected block
- WRSPB command completion
256th~511st)
- ESSPB command completion
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
10 (512 blocks, protected all)
11 (512 blocks, protected all)
12 (512 blocks, protected all)
13 (512 blocks, protected all)
14 (512 blocks, protected all)
15 (512 blocks, protected all)
- WRDPB command completion
- WRFBR command completion
- ESFBR command completion
• Deep Power Down Mode: By entering deep power down mode,
the flash device also is under protected from writing all commands
© Generalplus Technology Inc.
Proprietary & Confidential
7
Jan 21, 2013
Version: 1.0
GPR25L25605F
Protected Area Sizes (TB bit = 1)
Status bit
II. Additional 4K-bit secured OTP for unique identifier: to
provide 4K-bit one-time program area for setting device unique
serial number - Which may be set by factory or system customer.
- Security register bit 0 indicates whether the chip is locked by
factory or not.
Protect Level
256Mb
BP3 BP2 BP1 BP0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0 (none)
1 (1 block, protected block 0th)
- To program the 4K-bit secured OTP by entering 4K-bit
secured OTP mode (with Enter Security OTP command), and
going through normal program procedure, and then exiting
4K-bit secured OTP mode by writing Exit Security OTP
command.
2 (2 blocks, protected block 0th~1th)
3 (4 blocks, protected block 0th~3rd)
4 (8 blocks, protected block 0th~7th)
5
(16 blocks, protected block
0th~15th)
- Customer may lock-down the customer lockable secured OTP
by writing WRSCUR(write security register) command to set
customer lock-down bit1 as "1". Please refer to "Table 8.
Security Register Definition" for security register bit definition
and "Table 3. 4K-bit Secured OTP Definition" for address range
definition.
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
6
(32 blocks, protected block
0th~31st)
7
(64 blocks, protected block
0th~63rd)
8
(128 blocks, protected block
0th~127th)
- Note: Once lock-down whatever by factory or customer, it
cannot be changed any more. While in 4K-bit secured OTP
mode, array access is not allowed.
9
(256 blocks, protected block
0th~255th)
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
10 (512 blocks, protected all)
11 (512 blocks, protected all)
12 (512 blocks, protected all)
13 (512 blocks, protected all)
14 (512 blocks, protected all)
15 (512 blocks, protected all)
Table 3. 4K-bit Secured OTP Definition
Address range
Size
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
xxx000~xxx00F
128-bit
3968-bit
Determined by customer
xxx010~xxx1FF
© Generalplus Technology Inc.
Proprietary & Confidential
8
Jan 21, 2013
Version: 1.0
GPR25L25605F
7. MEMORY ORGANIZATION
Table 4. Memory Organization
© Generalplus Technology Inc.
Proprietary & Confidential
9
Jan 21, 2013
Version: 1.0
GPR25L25605F
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked
to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this device, this device
becomes standby mode and keeps the standby mode until next
CS# falling edge. In standby mode, SO pin of this device
should be High-Z.
QREAD/QREAD4B, RDSFDP, RES, REMS, QPIID, RDDPB,
RDSPB, RDPASS, RDLR, RDEAR, RDFBR, RDSPBLK, RDCR,
the shifted-in instruction sequence is followed by a data-out
sequence. After any bit of data being shifted out, the CS# can
be high. For the following instructions: WREN, WRDI, WRSR,
SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, PP/PP4B,
4PP/4PP4B, DP, ENSO, EXSO, WRSCUR, EN4B, EX4B,
WPSEL, GBLK, GBULK, SPBLK, SUSPEND, RESUME, NOP,
RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at
the byte boundary; otherwise, the instruction will be rejected and
not executed.
3. When correct command is inputted to this device, this device
becomes active mode and keeps the active mode until next CS#
rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK)
and data shifts out on the falling edge of SCLK. The difference
of Serial mode 0 and mode 3 is shown as "Serial Modes
Supported".
6. During the progress of Write Status Register, Program, Erase
operation, to access the memory array is neglected and not
affect the current operation of Write Status Register, Program,
Erase.
5. For the following instructions: RDID, RDSR, RDSCUR,
READ/READ4B,
FAST_READ/FAST_READ4B,
2READ/2READ4B, DREAD/DREAD4B, 4READ/4READ4B,
Figure1. SPI Modes Supported
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase.
The combination of CPOL bit and CPHA bit decides which Serial mode is supported.
Figure 2. Serial Input Timing
© Generalplus Technology Inc.
Proprietary & Confidential
10
Jan 21, 2013
Version: 1.0
GPR25L25605F
Figure 3. Output Timing
8.1. 256Mb Address Protocol
For the read operation, the whole array data can be continually
read out with one command. Data output starts from the selected
top or bottom 128Mb, but it can cross the boundary. When the
last byte of the segment is reached, the next byte (in a continuous
reading) is the first byte of the next segment. However, the EAR
The original 24 bit address protocol of serial Flash can only access
density size below 128Mb. For the memory device of 256Mb and
above, the 32bit address is requested for access higher memory
size. The GPR25L25605F provides three different methods to
access the whole 256Mb density:
(Extended Address Register) value does not change.
The
random access reading can only be operated in the selected
segment.
(1)Command entry 4-byte address mode: Issue Enter 4-Byte
mode command to set up the 4BYTE bit in Configuration Register
bit. After 4BYTE bit has been set, the number of address cycle
become 32-bit.
The Chip erase command will erase the whole chip and is not
limited by EAR selected segment.
(2)Extended Address Register (EAR): configure the memory
device into two 128Mb segments to select which one is active
through the EAR bit “0”.
Extended Address Register (EAR)
Bit 7
A31
Bit 6
A30
Bit 5
A29
Bit 4
A28
Bit 3
A27
Bit 2
A26
Bit 1
A25
Bit 0
A24
(3)4-byte Address Command Set: When issuing 4-byte address
command set, 4-byte address (A31-A0) is requested after the
instruction code. Please note that it is not necessary to issue
EN4B command before issuing any of 4-byte command set.
For the GPR25L25605F the A31 to A25 are Don't Care. During
EAR, reading these bits will read as 0. The bit 0 is default as "0".
Figure 4. Top and Bottom 128M bits
Enter 4-Byte Address Mode
In 4-byte Address mode, all instructions are 32-bits address clock
cycles. Two dedicated instructions are available to enter/exit this
modality:
● Enter 4-byte address mode (EN4B)
When under EAR mode, Read, Program, Erase operates in the
selected segment by using 3-byte address mode.
● Exit 4-byte address mode (EX4B)
When 4-byte address mode is enabled, the EAR<0> becomes
"don't care" for all instructions requiring 4-byte address.
For the read operation, the whole array data can be continually
read out with one command. Data output starts from the selected
top or bottom 128Mb, but it can cross the boundary. When the
last byte of the segment is reached, the next byte (in a continuous
reading) is the first byte of the next segment. However, the EAR
Extended Address Register (Configurable)
The device provides an 8-bit volatile register for extended Address
Register: it identifies the extended address (A31~A24) above
128Mb density by using original 3-byte address.
(Extended Address Register) value does not change.
The
random access reading can only be operated in the selected
segment.
When under EAR mode, Read, Program, Erase operates in the
selected segment by using 3-byte address mode.
The Chip erase command will erase the whole chip and is not
© Generalplus Technology Inc.
Proprietary & Confidential
11
Jan 21, 2013
Version: 1.0
GPR25L25605F
limited by EAR selected segment.
Reset QPI (RSTQIO)
To reset the QPI mode, the RSTQIO (F5H) command is required.
After the RSTQIO command is issued, the device returns from QPI
mode (4 I/O interface in command cycles) to SPI mode (1 I/O
8.2. Quad Peripheral Interface (QPI) Read Mode
QPI protocol enables user to take full advantage of Quad I/O
Serial Flash by providing the Quad I/O interface in command
cycles, address cycles and as well as data output cycles.
interface in command cycles).
Note: For EQIO and RSTQIO commands, CS# high width has to follow
"write spec" tSHSL for next instruction.
Enable QPI mode
Figure 6. Reset QPI Mode
By issuing 35H command, the QPI mode is enable.
Figure 5. Enable QPI Sequence
© Generalplus Technology Inc.
Proprietary & Confidential
12
Jan 21, 2013
Version: 1.0
GPR25L25605F
9. COMMAND DESCRIPTION
9.1. Command Set(Table 5)
9.1.1. Read/Write Array Commands
Command
(byte)
READ
FAST READ
2READ
DREAD
4READ
4READ
QREAD
(normal read) (fast read data) (2
x
I/O read (1I 2O read)
(4 I/O read start (4 I/O read start (1I 4O read)
command)
from
bottom from
128Mb)
SPI/QPI
Top
128Mb)
Mode
SPI
3/4
SPI
3/4
SPI
3/4
SPI
3/4
SPI/QPI
SPI
3/4
Address Bytes
1st byte
3/4
3/4
03 (hex)
ADD1
ADD2
ADD3
0B (hex)
ADD1
ADD2
ADD3
Dummy*
BB (hex)
ADD1
ADD2
ADD3
Dummy*
3B (hex)
ADD1
ADD2
ADD3
Dummy*
EB (hex)
ADD1
EA (hex)
ADD1
6B (hex)
ADD1
ADD2
ADD3
Dummy*
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
ADD2
ADD2
ADD3
ADD3
Dummy*
Dummy*
n bytes read out n bytes read out n bytes read out n bytes read out Quad I/O read Quad I/O read n bytes read out
until CS# goes until CS# goes by 2 x I/O until by Dual output for bottom for Top 128Mb by Quad output
high
high
CS# goes high until CS# goes 128Mb with 6 with
6
dummy until CS# goes
high
high
dummy cycles cycles
Command
(byte)
PP
4PP
SE
BE 32K
BE
erase (block
64KB)
CE
erase (chip erase)
(page program) (quad
program)
page (sector erase) (block
32KB)
Mode
SPI/QPI
3/4
SPI
3/4
SPI/QPI
3/4
SPI/QPI
3/4
SPI/QPI
SPI/QPI
0
Address Bytes
1st byte
3/4
02 (hex)
38 (hex)
ADD1
ADD2
ADD3
20 (hex)
ADD1
ADD2
ADD3
52 (hex)
ADD1
ADD2
ADD3
D8 (hex)
ADD1
ADD2
ADD3
60 or C7 (hex)
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
1-256
1-256
to program the quad input to to erase the to erase the to erase the to erase whole
selected page program
the selected sector selected
block
32K selected block chip
selected page
* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register.
© Generalplus Technology Inc.
Proprietary & Confidential
13
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.1.2. Read/Write Array Commands (4 Byte Address Command Set)
Command (byte)
Mode
READ4B
SPI
FAST READ4B
SPI
2READ4B
SPI
DREAD4B
SPI
4READ4B
SPI/QPI
4
QREAD4B
SPI
Address Bytes
1st byte
4
4
4
4
4
13 (hex)
ADD1
ADD2
ADD3
ADD4
0C (hex)
ADD1
BC (hex)
ADD1
ADD2
ADD3
ADD4
Dummy
3C (hex)
ADD1
ADD2
ADD3
ADD4
Dummy
EC (hex)
ADD1
6C (hex)
ADD1
ADD2
ADD3
ADD4
Dummy
2nd byte
3rd byte
ADD2
ADD2
4th byte
ADD3
ADD3
5th byte
ADD4
ADD4
6th byte
Dummy
Dummy
Data Cycles
Action
read data byte by read data byte by read data byte by Read data byte by read data byte by Read data byte by
4 byte address
4 byte address
2 x I/O with 4 byte Dual Output with 4 4 x I/O with 4 byte Quad Output with
address
byte address
address
4 byte address
Command (byte)
PP4B
4PP4B
BE4B
BE32K4B
(block erase
32KB)
SE4B
(block erase
64KB)
(Sector erase
4KB)
Mode
SPI/QPI
4
SPI
4
SPI/QPI
4
SPI/QPI
4
SPI/QPI
4
Address Bytes
1st byte
12 (hex)
ADD1
ADD2
ADD3
ADD4
3E (hex)
ADD1
ADD2
ADD3
ADD4
DC (hex)
ADD1
ADD2
ADD3
ADD4
5C (hex)
ADD1
ADD2
ADD3
ADD4
21 (hex)
ADD1
ADD2
ADD3
ADD4
2nd byte
3rd byte
4th byte
5th byte
6th byte
Data Cycles
Action
1-256
1-256
to program the Quad
input
to to
erase
the to
erase
the to
erase
the
(4KB)
selected page with program
the selected
(64KB) selected
(32KB) selected
4byte address
selected page with block with 4byte block with 4byte sector with 4byte
4byte address
address
address
address
9.1.3. Register/Setting Commands
Command (byte) WREN
(write enable) (write disable) (read
register)
WRDI
RDSR
RDCR
status (read
configuration configuration address
register) register) register)
WRSR (write RDEAR
WREAR
status/
(read extended (write
extended
address
register)
Mode
SPI/QPI
06 (hex)
SPI/QPI
04 (hex)
SPI/QPI
05 (hex)
SPI/QPI
15 (hex)
SPI/QPI
SPI/QPI
C8 (hex)
SPI/QPI
C5 (hex)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
01 (hex)
Values
Values
1-2
1
© Generalplus Technology Inc.
Proprietary & Confidential
14
Jan 21, 2013
Version: 1.0
GPR25L25605F
Command (byte) WREN
(write enable) (write disable) (read
register)
WRDI
RDSR
RDCR
WRSR (write RDEAR
WREAR
status (read
status/ (read extended (write
configuration configuration address
register) register) register)
extended
address
register)
Action
sets the (WEL) resets
the to read out the to read out the to write new read extended write extended
write values of the values of the values of the address register address register
write
enable (WEL)
enable latch bit status register configuration
latch bit
status/
register
configuration
register
Command (byte) WPSEL
EQIO
RSTQIO (Reset EN4B
EX4B
PGM/ERS
PGM/ERS
Resume
(Resumes
Program/
Erase)
(Write Protect (Enable QPI)
Selection)
QPI)
(enter 4-byte (exit
mode) mode)
4-byte Suspend
(Suspends
Program/
Erase)
Mode
SPI/QPI
68 (hex)
SPI
QPI
F5 (hex)
SPI/QPI
B7 (hex)
SPI/QPI
E9 (hex)
SPI/QPI
B0 (hex)
SPI/QPI
30 (hex)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
35 (hex)
to enter and Entering
the Exiting the QPI to enter 4-byte to exit 4-byte
enable
QPI mode
mode
mode and set mode and clear
4BYTE bit as 4BYTE bit to be
individual block
protect mode
"1"
"0"
Command
(byte)
DP
(Deep RDP
SBL
(Set
RDFBR
WRFBR
ESFBR
power down) (Release
from
Burst (read
boot
fast (write
boot
fast (erase fast
boot
deep Length)
power down)
SPI/QPI
AB (hex)
register)
register)
SPI
17(hex)
register)
Mode
SPI/QPI
B9 (hex)
SPI/QPI
C0 (hex)
SPI
SPI
1st byte
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
16(hex)
18(hex)
1-4
4
enters deep release from to set Burst
power down deep power length
mode
down mode
© Generalplus Technology Inc.
Proprietary & Confidential
15
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.1.4. ID/Security Commands
Command (byte) RDID
(read
RES
REMS
(read
QPIID
RDSFDP
ENSO
(enter secured (exit secured
OTP) OTP)
EXSO
(read
(QPI ID Read)
identification) electronic ID) electronic
manufacturer
& device ID)
Mode
SPI
0
SPI/QPI
SPI
QPI
0
SPI/QPI
SPI/QPI
SPI/QPI
Address Bytes
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
0
0
3
0
0
9F (hex)
AB (hex)
90 (hex)
AF (hex)
5A (hex)
ADD1
B1 (hex)
C1 (hex)
x
x
x
x
ADD2
ADD1 (Note 1)
ADD3
Dummy (8)
outputs JEDEC to read out output
ID:
the ID
in
QPI n bytes read out to enter the to
exit
the
1-byte 1-byte Device Manufacturer ID interface
until CS# goes 4K-bit secured 4K-bit secured
Manufacturer ID ID
& 2-byte Device
ID
& Device ID
high
OTP mode
OTP mode
Command
(byte)
RDSCUR
WRSCUR
(write
GBLK
GBULK
WRLR
RDLR
Lock (read
register)
WRPASS
Lock (write
password
RDPASS
(read
(read
(gang block (gang block (write
security
register)
security
register)
lock)
unlock)
register)
password
register)
register)
Mode
SPI/QPI
SPI/QPI
0
SPI/QPI
SPI/QPI
SPI
0
SPI
0
SPI
0
SPI
0
Address Bytes
1st byte
0
0
0
2B (hex)
2F (hex)
7E (hex)
98 (hex)
2C (hex)
2D (hex)
28 (hex)
27 (hex)
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
2
2
1-8
1-8
to read value to set the whole
chip whole
chip
of security lock-down bit write protect unprotect
register
as "1" (once
lock-down,
cannot
be
updated)
Command
(byte)
PASSULK
(password
unlock)
WRSPB
(SPB
ESSPB
bit (all SPB bit (read
erase) status)
SPI SPI
RDSPB
SPBLK
RDSPBLK
WRDPB
RDDPB
SPB (SPB
set)
lock (SPB
lock (write
DPB (read
DPB
program)
register read) register)
register)
Mode
SPI
0
SPI
4
SPI
0
SPI
0
SPI
4
SPI
4
Address Bytes
1st byte
0
4
29 (hex)
E3 (hex)
ADD1
ADD2
E4 (hex)
E2 (hex)
ADD1
ADD2
A6 (hex)
A7 (hex)
E1 (hex)
ADD1
ADD2
E0 (hex)
2nd byte
3rd byte
ADD1
ADD2
© Generalplus Technology Inc.
Proprietary & Confidential
16
Jan 21, 2013
Version: 1.0
GPR25L25605F
Command
(byte)
PASSULK
(password
unlock)
WRSPB
(SPB
ESSPB
bit (all SPB bit (read
erase) status)
ADD3
RDSPB
SPBLK
SPB (SPB
set)
RDSPBLK
WRDPB
RDDPB
DPB (read
register)
lock (SPB lock (write
DPB
program)
register read) register)
4th byte
5th byte
Data Cycles
Action
ADD3
ADD4
ADD3
ADD4
ADD3
ADD4
1
ADD4
1
8
2
1
9.1.5. Reset Commands
Command
(byte)
NOP
RSTEN
RST
(No
(Reset
(Reset
Memory)
Operation)
Enable)
Mode
SPI/QPI
00 (hex)
SPI/QPI
66 (hex)
SPI/QPI
99 (hex)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SO/SIO1 which is different from 1 x I/O condition.
Note 2: ADD=00H will output the manufacturer ID first and AD=01H will output device ID first.
Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.
Note 4: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the reset operation will be disabled.
Note 5: The number in parentheses after "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)" represents there are 8 clock cycles
for the data in. Please note the number after "ADD" are based on 3-byte address mode, for 4-byte address mode, which will be increased.
9.2. Write Enable (WREN)
9.3. Write Disable (WRDI)
The Write Enable (WREN) instruction is for setting Write Enable
Latch (WEL) bit.
For those instructions like PP/ PP4B,
The Write Disable (WRDI) instruction is to reset Write Enable
Latch (WEL) bit.
4PP/4PP4B, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, and
WRSR, which are intended to change the device content WEL bit
should be set every time after the WREN instruction setting the
WEL bit.
The sequence of issuing WRDI instruction is: CS# goes
low→sending WRDI instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care in SPI mode.
The WEL bit is reset by following situations:
- Power-up
The sequence of issuing WREN instruction is: CS# goes
low→sending WREN instruction code→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care in SPI mode.
Figure 7. Write Enable (WREN) Sequence (SPI Mode)
- Reset# pin driven low
- WRDI command completion
- WRSR command completion
- PP/PP4B command completion
- 4PP/4PP4B command completion
- SE/SE4B command completion
- BE32K/BE32K4B command completion
- BE/BE4B command completion
Figure 8. Write Enable (WREN) Sequence (QPI Mode)
- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
© Generalplus Technology Inc.
Proprietary & Confidential
17
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.5. Release from Deep Power-down (RDP), Read
Electronic Signature (RES)
- WPSEL command completion
- GBLK command completion
- GBULK command completion
- WREAR command completion
- WRLR command completion
- WRPASS command completion
- RDPASS command completion
- SPBLK command completion
- WRSPB command completion
- ESSPB command completion
- WRDPB command completion
- WRFBR command completion
- ESFBR command completion
The Release from Deep Power-down (RDP) instruction is
completed by driving Chip Select (CS#) High. When Chip Select
(CS#) is driven High, the device is put in the Stand-by Power mode.
If the device was not previously in the Deep Power-down mode,
the transition to the Stand-by Power mode is immediate. If the
device was previously in the Deep Power-down mode, though, the
transition to the Stand-by Power mode is delayed by tRES2, and
Chip Select (CS#) must remain High for at least tRES2(max), as
specified in Table 16 AC Characteristics. Once in the Stand-by
Power mode, the device waits to be selected, so that it can receive,
decode and execute instructions. The RDP instruction is only for
releasing from Deep Power Down Mode. Reset# pin goes low
will release the Flash from deep power down mode.
Figure 9. Write Disable (WRDI) Sequence (SPI Mode)
RES instruction is for reading out the old style of 8-bit Electronic
Signature, whose values are shown as Table 6 ID Definitions.
This is not the same as RDID instruction. It is not recommended
to use for new design. For new design, please use RDID
instruction.
Even in Deep power-down mode, the RDP and RES are also
allowed to be executed, only except the device is in progress of
program/erase/write cycle; there's no effect on the current
program/erase/write cycle in progress.
Figure 10. Write Disable (WRDI) Sequence (QPI Mode)
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
9.4. Read Identification (RDID)
The RES instruction is ended by CS# goes high after the ID been
read out at least once. The ID outputs repeatedly if continuously
send the additional clock cycles on SCLK while CS# is at low. If
the device was not previously in Deep Power-down mode, the
device transition to standby mode is immediate. If the device was
previously in Deep Power-down mode, there's a delay of tRES2 to
transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be
selected, so it can be receive, decode, and execute instruction.
The RDID instruction is for reading the manufacturer ID of 1-byte
and followed by Device ID of 2-byte. The Manufacturer ID and
Device ID are listed as Table 6 ID Definitions.
The sequence of issuing RDID instruction is: CS# goes low→
sending RDID instruction code→24-bits ID data out on SO→ to
end RDID operation can drive CS# to high at any time during data
out.
While Program/Erase operation is in progress, it will not decode
the RDID instruction, therefore there's no effect on the cycle of
program/erase operation which is currently in progress. When
CS# goes high, the device is at standby stage.
Figure 12. Read Electronic Signature (RES) Sequence (SPI Mode)
Figure 11. Read Identification (RDID) Sequence (SPI mode only)
© Generalplus Technology Inc.
Proprietary & Confidential
18
Jan 21, 2013
Version: 1.0
GPR25L25605F
Figure 13. Read Electronic Signature (RES) Sequence (QPI
Mode)
shifted out on the falling edge of SCLK with most significant bit
(MSB) first. The Device ID values are listed in Table 6 of ID
Definitions. If the one-byte address is initially set to 01h, then the
device ID will be read first and then followed by the Manufacturer
ID. The Manufacturer and Device IDs can be read continuously,
alternating from one to the other. The instruction is completed by
driving CS# high.
Figure 16. Read Electronic Manufacturer & Device ID (REMS)
Sequence (SPI Mode only)
Figure 14. Release from Deep Power-down (RDP) Sequence (SPI
Mode)
Figure 15. Release from Deep Power-down (RDP) Sequence (QPI
Mode)
Note:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output
device ID first.
9.7. QPI ID Read (QPIID)
9.6. Read Electronic Manufacturer ID & Device ID
(REMS)
User can execute this QPIID Read instruction to identify the
Device ID and Manufacturer ID. The sequence of issue QPIID
instruction is CS# goes low→sending QPI ID instruction→Data out
on SO→CS# goes high. Most significant bit (MSB) first.
After the command cycle, the device will immediately output data
on the falling edge of SCLK. The manufacturer ID, memory type,
and device ID data byte will be output continuously, until the CS#
goes high.
The REMS instruction is an alternative to the Release from
Power-down/Device ID instruction that provides both the JEDEC
assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from
Power-down/Device ID instruction. The instruction is initiated by
driving the CS# pin low and shift the instruction code "90h"
followed by two dummy bytes and one bytes address (A7~A0).
After which, the Manufacturer ID for (C2h) and the Device ID are
Table 6. ID Definitions
Command Type
GPR25L25605F
Manufactory ID
C2
Memory type
Memory density
19
RDID
RES
9Fh
ABh
90h
AFh
20
Electronic ID
18
Manufactory ID
Device ID
18
REMS
QPIID
C2
Manufactory ID
C2
Memory type
20
Memory density
19
© Generalplus Technology Inc.
Proprietary & Confidential
19
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.8. Read Status Register (RDSR)
9.9. Read Configuration Register (RDCR)
The RDSR instruction is for reading Status Register Bits. The
Read Status Register can be read at any time (even in
program/erase/write status register condition). It is recommended
to check the Write in Progress (WIP) bit before sending a new
The RDCR instruction is for reading Configuration Register Bits.
The Read Configuration Register can be read at any time (even in
program/erase/write configuration register condition).
It is
recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write
configuration register operation is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→
sending RDCR instruction code→ Configuration Register data out
on SO.
instruction when
a program, erase, or write status register
operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→
sending RDSR instruction code→ Status Register data out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
Figure 17. Read Status Register (RDSR) Sequence (SPI Mode)
Figure 19. Read Configuration Register (RDCR) Sequence (SPI
Mode)
Figure 18. Read Status Register (RDSR) Sequence (QPI Mode)
Figure 20. Read Configuration Register (RDCR) Sequence (QPI
Mode)
© Generalplus Technology Inc.
Proprietary & Confidential
20
Jan 21, 2013
Version: 1.0
GPR25L25605F
For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:
Figure 21. Program/Erase flow with read array data
© Generalplus Technology Inc.
Proprietary & Confidential
21
Jan 21, 2013
Version: 1.0
GPR25L25605F
Figure 22. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
© Generalplus Technology Inc.
Proprietary & Confidential
22
Jan 21, 2013
Version: 1.0
GPR25L25605F
Status Register
without hardware protection mode being set. To write the Block
Protect (BP3, BP2, BP1, BP0) bits requires the Write Status
Register (WRSR) instruction to be executed. Those bits define
the protected area of the memory to against Page Program (PP),
Sector Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE)
and Chip Erase (CE) instructions (only if Block Protect bits
(BP3:BP0) set to 0, the CE instruction can be executed). The
BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-protected.
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0"
(factory default), it performs non-Quad and WP#, RESET# are
enable. While QE is "1", it performs Quad I/O mode and WP#,
RESET# are disabled. In the other word, if the system goes into
four I/O mode (QE=1), the feature of HPM and RESET will be
disabled.
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates
whether the device is busy in program/erase/write status register
progress. When WIP bit sets to 1, which means the device is
busy in program/erase/write status register progress. When WIP
bit sets to 0, which means the device is not in progress of
program/erase/write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates
whether the device is set to internal write enable latch. When
WEL bit sets to 1, which means the internal write enable latch is
set, the device can accept program/ erase/write status register
instruction. When WEL bit sets to 0, which means no internal
write enable latch; the device will not accept program/erase/write
status register instruction. The program/erase command will be
ignored if it is applied to a protected memory area. To ensure
both WIP bit & WEL bit are both set to 0 and available for next
program/erase/operations, WIP bit needs to be confirm to be 0
before polling WEL bit. After WIP bit confirmed, WEL bit needs to
be confirm to be 0.
SRWD bit. The Status Register Write Disable (SRWD) bit,
non-volatile bit, is operated together with Write Protection
(WP#/SIO2) pin for providing hardware protection mode. The
hardware protection mode requires SRWD sets to
1 and
WP#/SIO2 pin signal is low stage. In the hardware protection
mode, the Write Status Register (WRSR) instruction is no longer
accepted for execution and the SRWD bit and Block Protect bits
(BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to
be "0".
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1,
BP0) bits, non-volatile bits, indicate the protected area (as defined
in Table 2) of the device to against the program/erase instruction
Status Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SRWD (status QE
(Quad BP3 (level of BP2 (level of BP1 (level of BP0 (level of WEL
(write WIP (write in
register
protect)
1=status
register
disable
write Enable)
protected block) protected block) protected block) protected block) enable latch)
progress bit)
1=Quad Enable (note 1)
write 0=not Quad
Enable
(note 1)
(note 1)
(note 1)
1=write enable 1=write
0=not
write operation
enable
0=not in write
operation
Non-volatile bit Non-volatile bit Non-volatile bit
Non-volatile bit Non-volatile bit Non-volatile bit volatile bit
volatile bit
Note 1: see the Table 2 "Protected Area Size".
Configuration Register
Top/Bottom (TB) bit is used to configure the Block Protect area by
BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the
memory array. The TB bit is defaulted as “0”, which means Top
area protect. When it is set as “1”, the protect area will change to
Bottom area of the memory device. To write the TB bits requires
the Write Status Register (WRSR) instruction to be executed.
4BYTE Indicator bit
The Configuration Register is able to change the default status of
Flash memory. Flash memory will be configured after the CR bit
is set.
ODS bit
The output driver strength (ODS2, ODS1, ODS0) bits are volatile
bits, which indicate the output driver level (as defined in Output
Driver Strength Table) of the device. The Output Driver Strength
is defaulted as 30 Ohms when delivered from factory. To write
the ODS bits requires the Write Status Register (WRSR)
instruction to be executed.
By writing EN4B instruction, the 4BYTE bit may be set as "1" to
access the address length of 32-bit for memory area of higher
density (large than 128Mb). The default state is "0" as the 24-bit
address mode. The 4BYTE bit may be cleared by power-off or
writing EX4B instruction to reset the state to be "0".
TB bit
The Top/Bottom (TB) bit is
a
non-volatile OTP bit.
The
© Generalplus Technology Inc.
Proprietary & Confidential
23
Jan 21, 2013
Version: 1.0
GPR25L25605F
Configuration Register
bit7
bit6
bit5
bit4
Reserved TB
(top/bottom
selected)
0=Top area protect (note 1)
bit3
bit2
bit1
bit0
DC1
DC0
4 BYTE
ODS 2
ODS 1
ODS 0
(Dummy cycle 1) (Dummy cycle 0)
(output driver (output driver (output driver
strength)
strength)
(note 1)
strength)
(note 1)
(note 2)
(note 2)
0=3-byte address mode
1=4-byte address mode
(Default=0)
x
1=Bottom
protect
area
(Default=0)
OTP
volatile bit
volatile bit
volatile bit
x
volatile bit
volatile bit
volatile bit
Note 1: see "Output Driver Strength Table"
Note 2: see "Dummy Cycle and Frequency Table (MHz)"
Output Driver Strength Table
ODS2
ODS1
ODS0
Description
Reserved
Note
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
90 Ohms
60 Ohms
45 Ohms
Impedance at VCC/2
Reserved
20 Ohms
15 Ohms
30 Ohms (Default)
Dummy Cycle and Frequency Table (MHz)
Numbers of Dummy
Quad Output Fast
Read
DC[1:0]
Fast Read
Dual Output Fast Read
clock cycles
00 (default)
8
6
104
104
104
133
104
104
104
133
104
84
01
10
11
8
104
133
10
Numbers of Dummy
clock cycles
DC[1:0]
Dual IO Fast Read
00 (default)
4
6
84
01
10
11
104
104
133
8
10
Numbers of Dummy
clock cycles
DC[1:0]
Quad IO Fast Read
00 (default)
6
4
84
70
01
10
11
8
104
133
10
© Generalplus Technology Inc.
Proprietary & Confidential
24
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.10. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status
Register Bits and Configuration Register Bits. Before sending
WRSR instruction, the Write Enable (WREN) instruction must be
decoded and executed to set the Write Enable Latch (WEL) bit in
advance. The WRSR instruction can change the value of Block
Protect (BP3, BP2, BP1, BP0) bits to define the protected area of
memory (as shown in Table 2). The WRSR also can set or reset
the Quad enable (QE) bit and set or reset the Status Register
Write Disable (SRWD) bit in accordance with Write Protection
(WP#/ SIO2) pin signal, but has no effect on bit1(WEL) and bit0
(WIP) of the status register. The WRSR instruction cannot be
executed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→
sending WRSR instruction code→ Status Register data on
SI→CS# goes high.
Figure 24. Write Status Register (WRSR) Sequence (QPI Mode)
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the
WREN instruction may set the WEL bit and can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is
defined by BP3, BP2, BP1, BP0 and T/B bit, is at software
protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction
may set the WEL bit can change the values of SRWD, BP3, BP2,
BP1, BP0. The protected area, which is defined by BP3, BP2,
The CS# must go high exactly at the 8 bits or 16 bits data
boundary; otherwise, the instruction will be rejected and not
executed. The self-timed Write Status Register cycle time (tW) is
initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Write Status
Register cycle is in progress. The WIP sets 1 during the tW
timing, and sets 0 when Write Status Register Cycle is completed,
and the Write Enable Latch (WEL) bit is reset.
BP1, BP0 and T/B bit, is at software protected mode (SPM)
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status
Register even if the WEL bit has previously been set. It is rejected to write
the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is
low before SRWD bit=1), it enters the hardware protected mode
(HPM). The data of the protected area is protected by software
protected mode by BP3, BP2, BP1, BP0 and T/B bit and hardware
Figure 23. Write Status Register (WRSR) Sequence (SPI Mode)
protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once
the hardware protected mode is entered. If the WP#/SIO2 pin is
permanently connected to high, the hardware protected mode can never be
entered; only can use software protected mode via BP3, BP2, BP1, BP0 and
T/B bit.
Note: The CS# must go high exactly at 8 bits or 16 bits data boundary to
If the system enter QPI or set QE=1, the feature of HPM will be disabled.
completed the write register command.
Table 7. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Software
(SPM)
protection
mode Status register can be written in WP#=1 and SRWD bit=0, or The protected area cannot be
(WEL bit is set to "1") and the WP#=0 and SRWD bit=0, or program or erase.
SRWD, BP0-BP3 bits can be WP#=1 and SRWD=1
changed
Hardware protection mode The SRWD, BP0-BP3 of status WP#=0, SRWD bit=1
(HPM) register bits cannot be changed
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.
The protected area cannot be
program or erase.
© Generalplus Technology Inc.
Proprietary & Confidential
25
Jan 21, 2013
Version: 1.0
GPR25L25605F
Figure 25. WRSR flow
Figure 26. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
© Generalplus Technology Inc.
Proprietary & Confidential
26
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.11. Enter 4-byte mode (EN4B)
Figure 27. Read Data Bytes (READ) Sequence (SPI Mode only)
The EN4B instruction enables accessing the address length of
32-bit for the memory area of higher density (larger than 128Mb).
The device default is in 24-bit address mode; after sending out the
EN4B instruction, the bit5 (4BYTE bit) of security register will be
automatically set to "1" to indicate the 4-byte address mode has
been enabled. Once the 4-byte address mode is enabled, the
address length becomes 32-bit instead of the default 24-bit.
There are three methods to exit the 4-byte mode: writing exit
4-byte mode (EX4B) instruction, Reset or power-off.
Note: Please note the address cycles above are based on 3-byte address
mode. For 4-byte address mode, the address cycles will be increased.
9.14. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The
address is latched on rising edge of SCLK, and data of each bit
shifts out on the falling edge of SCLK at a maximum frequency fC.
The first address byte can be at any location. The address is
automatically increased to the next higher address after each byte
data is shifted out, so the whole memory can be read out at a
single FAST_READ instruction. The address counter rolls over to
0 when the highest address has been reached.
All instructions are accepted normally, and just the address bit is
changed from 24-bit to 32-bit.
The following command don't support 4bye address: 4READ for
top 128Mb (EAh), RDSFDP, RES and REMS.
The sequence of issuing EN4B instruction is: CS# goes low →
sending EN4B instruction to enter 4-byte mode( automatically set
4BYTE bit as "1") → CS# goes high.
9.12. Exit 4-byte mode (EX4B)
The default read mode is 3-byte address, to access higher
address (4-byte address) which requires to enter the 4-byte
address read mode or to define EAR bit. To enter the 4-byte
mode, please refer to the enter 4-byte mode (EN4B) Mode section.
Read on SPI Mode The sequence of issuing FAST_READ
instruction is: CS# goes low→ sending FAST_READ instruction
code→ 3-byte or 4-byte address on SI→ 8 dummy cycles
(default)→ data out on SO→ to end FAST_ READ operation can
use CS# to high at any time during data out.
The EX4B instruction is executed to exit the 4-byte address mode
and return to the default 3-bytes address mode. After sending
out the EX4B instruction, the bit5 (4BYTE bit) of Configuration
register will be cleared to be "0" to indicate the exit of the 4-byte
address mode. Once exiting the 4-byte address mode, the
address length will return to 24-bit.
The sequence of issuing EX4B instruction is: CS# goes low →
sending EX4B instruction to exit 4-byte mode (automatically clear
the 4BYTE bit to be "0") → CS# goes high.
In the performance-enhancing mode, P[7:4] must be toggling with
P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode
continue and reduce the next 4READ instruction. Once P[7:4] is
no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h
and afterwards CS# is raised and then lowered, the system then
will escape from performance enhance mode and return to normal
operation.
9.13. Read Data Bytes (READ)
The read instruction is for reading data out. The address is
latched on rising edge of SCLK, and data shifts out on the falling
edge of SCLK at a maximum frequency fR. The first address
byte can be at any location. The address is automatically
increased to the next higher address after each byte data is shifted
out, so the whole memory can be read out at a single READ
instruction. The address counter rolls over to 0 when the highest
address has been reached.
While Program/Erase/Write Status Register cycle is in progress,
FAST_READ instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
The default read mode is 3-byte address, to access higher
address (4-byte address) which requires to enter the 4-byte
address read mode or to define EAR bit. To enter the 4-byte
mode, please refer to the enter 4-byte mode (EN4B) Mode section.
The sequence of issuing READ instruction is: CS# goes
low→sending READ instruction code→ 3-byte or 4-byte address
on SI→ data out on SO→to end READ operation can use CS# to
high at any time during data out.
© Generalplus Technology Inc.
Proprietary & Confidential
27
Jan 21, 2013
Version: 1.0
GPR25L25605F
Figure 28. Read at Higher Speed (FAST_READ) Sequence (SPI
Mode)
Figure 29. Dual Read Mode Sequence
Note: Please note the above address cycles are base on 3-byte address
mode, for 4-byte address mode, the address cycles will be increased.
9.16. 2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial Flash in
read mode. The address is latched on rising edge of SCLK, and
data of every two bits (interleave on 2 I/O pins) shift out on the
falling edge of SCLK at a maximum frequency fT. The first
Note: Please note the address cycles above are based on 3-byte address
mode. For 4-byte address mode, the address cycles will be increased.
address byte can be at any location.
The address is
9.15. Dual Output Read Mode (DREAD)
automatically increased to the next higher address after each byte
data is shifted out, so the whole memory can be read out at a
single 2READ instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing
2READ instruction, the following address/dummy/data out will
perform as 2-bit instead of previous 1-bit.
The DREAD instruction enable double throughput of Serial Flash
in read mode. The address is latched on rising edge of SCLK,
and data of every two bits (interleave on 2 I/O pins) shift out on the
falling edge of SCLK at a maximum frequency fT. The first
address byte can be at any location.
The address is
automatically increased to the next higher address after each byte
data is shifted out, so the whole memory can be read out at a
single DREAD instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing
DREAD instruction, the following data out will perform as 2-bit
instead of previous 1-bit.
The default read mode is 3-byte address, to access higher
address (4-byte address) which requires to enter the 4-byte
address read mode or to define EAR bit. To enter the 4-byte
mode, please refer to the enter 4-byte mode (EN4B) Mode section.
The sequence of issuing 2READ instruction is: CS# goes low→
sending 2READ instruction→ 3-byte or 4-byte address interleave
on SIO1 & SIO0→ 4 dummy cycles (default) on SIO1 & SIO0→
data out interleave on SIO1 & SIO0→ to end 2READ operation
can use CS# to high at any time during data out.
The default read mode is 3-byte address, to access higher
address (4-byte address) which requires to enter the 4-byte
address read mode or to define EAR bit. To enter the 4-byte
mode, please refer to the enter 4-byte mode (EN4B) Mode section.
The sequence of issuing DREAD instruction is: CS# goes low→
sending DREAD instruction→3-byte or 4-byte address on SIO0→
8 dummy cycles (default) on SIO0→ data out interleave on SIO1 &
SIO0→ to end DREAD operation can use CS# to high at any time
during data out.
While Program/Erase/Write Status Register cycle is in progress,
2READ instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
Figure 30. 2 x I/O Read Mode Sequence (SPI Mode only)
While Program/Erase/Write Status Register cycle is in progress,
DREAD instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
Note: Please note the address cycles above are based on 3-byte address
mode. For 4-byte address mode, the address cycles will be increased.
9.17. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in
read mode. The address is latched on rising edge of SCLK, and
data of every four bits (interleave on 4 I/O pins) shift out on the
falling edge of SCLK at a maximum frequency fQ. The first
© Generalplus Technology Inc.
Proprietary & Confidential
28
Jan 21, 2013
Version: 1.0
GPR25L25605F
address byte can be at any location.
The address is
address read mode or to define EAR bit. To enter the 4-byte
mode, please refer to the enter 4-byte mode (EN4B) Mode section.
4 x I/O Read on SPI Mode (4READ) The sequence of issuing
4READ instruction is: CS# goes low→ sending 4READ
instruction→ 3-byte or 4-byte address interleave on SIO3, SIO2,
SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on
SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS#
to high at any time during data out.
automatically increased to the next higher address after each byte
data is shifted out, so the whole memory can be read out at a
single QREAD instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing
QREAD instruction, the following data out will perform as 4-bit
instead of previous 1-bit.
The default read mode is 3-byte address, to access higher
address (4-byte address) which requires to enter the 4-byte
address read mode or to define EAR bit. To enter the 4-byte
mode, please refer to the enter 4-byte mode (EN4B) Mode section.
The sequence of issuing QREAD instruction is: CS# goes low→
sending QREAD instruction → 3-byte or 4-byte address on SI → 8
dummy cycle (Default) → data out interleave on SO3, SO2, SO1 &
SO0→ to end QREAD operation can use CS# to high at any time
during data out.
4 x I/O Read on QPI Mode (4READ) The 4READ instruction also
support on QPI command mode. The sequence of issuing
4READ instruction QPI mode is: CS# goes low→ sending 4READ
instruction→ 3-byte or 4-byte address interleave on SIO3, SIO2,
SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on
SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS#
to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress,
4READ instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
While Program/Erase/Write Status Register cycle is in progress,
QREAD instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
Figure 32. 4 x I/O Read Mode Sequence (SPI Mode)
Figure 31. Quad Read Mode Sequence
Notes:
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. Configuration Dummy cycle numbers will be different depending on the
bit6 & bit 7 (DC0 & DC1) setting in configuration register.
4. Please note the address cycles above are based on 3-byte address mode.
For 4-byte address mode, the address cycles will be increased.
1. Please note the above address cycles are base on 3-byte address mode,
for 4-byte address mode, the address cycles will be increased.
9.18. 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in
read mode. A Quad Enable (QE) bit of status Register must be
set to "1" before sending the 4READ instruction. The address is
latched on rising edge of SCLK, and data of every four bits
(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any
location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole
memory can be read out at a single 4READ instruction. The
address counter rolls over to 0 when the highest address has been
Figure 33. 4 x I/O Read Mode Sequence (QPI Mode)
Note: Please note the address cycles above are based on 3-byte address
mode. For 4-byte address mode, the address cycles will be increased.
9.19. 4 Byte Address Command Set
reached.
Once writing 4READ instruction, the following
The operation of 4-byte address command set was very similar to
original 3-byte address command set. The only different is all the
4-byte command set request 4-byte address (A31-A0) followed by
instruction code. The command set support 4-byte address
address/dummy/data out will perform as 4-bit instead of previous
1-bit.
The default read mode is 3-byte address, to access higher
address (4-byte address) which requires to enter the 4-byte
© Generalplus Technology Inc.
Proprietary & Confidential
29
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.20. Burst Read
including: READ4B, Fast_Read4B, DREAD4B, 2READ4B,
QREAD4B, 4READ4B, PP4B, 4PP4B, SE4B, BE32K4B, BE4B.
Please note that it is not necessary to issue EN4B command
before issuing any of 4-byte command set.
This device supports Burst Read in both SPI and QPI mode.
To set the Burst length, following command operation is required to
issue command: “C0h” in the first Byte (8-clocks), following 4
clocks defining wrap around enable with “0h” and disable with“1h”.
The next 4 clocks are to define wrap around depth. Their
definitions are as the following table:
Figure 34. Read Data Bytes using 4 Byte Address Sequence
(READ4B)
Data
00h
01h
02h
03h
1xh
Wrap Around
Wrap Depth
8-byte
Yes
Yes
Yes
Yes
No
16-byte
32-byte
64-byte
X
Figure 35. Read Data Bytes at Higher Speed using 4 Byte Address
Sequence (FASTREAD4B)
The wrap around unit is defined within the 256Byte page, with
random initial address. It is defined as “wrap-around mode
disable” for the default state of the device. To exit wrap around, it
is required to issue another “C0” command in which data=‘1xh”.
Otherwise, wrap around status will be retained until power down or
reset command. To change wrap around depth, it is requried to
issue another “C0” command in which data=“0xh”. QPI “EAh”
“EBh” and SPI "EAh" “EBh” support wrap around feature after
wrap around is enabled. Burst read is supported in both SPI and
QPI mode. The device is default without Burst read.
Figure 38. SPI Mode
Figure 36. 2 x I/O Fast Read using 4 Byte Address Sequence
(2READ4B)
Figure 39. QPI Mode
Note: MSB=Most Significant Bit
Figure 37. 4 I/O Fast Read using 4 Byte Address sequence
(4READ4B)
LSB=Least Significant Bit
9.21. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle
bits after address cycle toggles.
Performance enhance mode is supported in both SPI and QPI
mode.
In QPI mode, “EAh” “EBh” "ECh" and SPI "EAh" “EBh” "ECh"
commands support enhance mode. The performance enhance
mode is not supported in dual I/O mode.
To enter performance-enhancing mode, P[7:4] must be toggling
with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this
© Generalplus Technology Inc.
Proprietary & Confidential
30
Jan 21, 2013
Version: 1.0
GPR25L25605F
mode continue and skip the next 4READ instruction. To leave
enhance mode, P[7:4] is no longer toggling with P[3:0]; likewise
P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised
and then lowered. Issuing ”FFh” data cycle can also exit enhance
mode. The system then will leave performance enhance mode
and return to normal operation.
Figure 41. 4 x I/O Read enhance performance Mode Sequence
(QPI Mode)
After entering enhance mode, following CS# go high, the device
will stay in the read mode and treat CS# go low of the first clock as
address instead of command cycle.
Another sequence of issuing 4READ instruction especially useful
in random access is: CS# goes low→sending
4 READ
instruction→3-bytes or 4-bytes address interleave on SIO3, SIO2,
SIO1 & SIO0 →performance enhance toggling bit P[7:0]→ 4
dummy cycles (Default) →data out still CS# goes high → CS#
goes low (reduce 4 Read instruction) → 3-bytes or 4-bytes random
access address.
Notes:
1. Configuration Dummy cycle numbers will be different depending on the
bit6 & bit 7 (DC0 & DC1) setting in configuration register.
2. Please note the address cycles above are based on 3-byte address mode.
For 4-byte address mode, the address cycles will be increased.
9.22. Performance Enhance Mode Reset
Figure 40. 4 x I/O Read enhance performance Mode Sequence
(SPI Mode)
To conduct the Performance Enhance Mode Reset operation in
SPI mode, FFh data cycle(8 clocks in 3-byte address mode)/3FFh
data cycle(10 clocks in 4-byte address mode), should be issued in
1I/O sequence. In QPI Mode, FFFFFFFFh data cycle(8 clocks in
3-byte address mode)/FFFFFFFFFFh data cycle (10 clocks in
4-byte address mode), in 4I/O should be issued.
If the system controller is being Reset during operation, the flash
device will return to the standard SPI operation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
Figure 42. Performance Enhance Mode Reset for Fast Read Quad
I/O (SPI Mode)
Notes:
1. If not using performance enhance recommend to keep 1 or 0 in
performance enhance indicator.
2. Configuration Dummy cycle numbers will be different depending on the
bit6 & bit 7 (DC0 & DC1) setting in configuration register.
3. Please note the address cycles above are based on 3-byte address mode.
For 4-byte address mode, the address cycles will be increased.
Figure 43. Performance Enhance Mode Reset for Fast Read Quad
I/O (QPI Mode)
© Generalplus Technology Inc.
Proprietary & Confidential
31
Jan 21, 2013
Version: 1.0
GPR25L25605F
Figure 44. Performance Enhance Mode Reset for Fast Read Quad
I/O using 4Byte Address Sequence (SPI Mode)
Fast Boot function and also define the number of delay cycles and
start address (where boot code being transferred). Instruction
WRFBR (write fast boot register) and ESFBR (erase fast boot
register) can be used for the status configuration or alternation of
the Fast Boot Register bit. RDFBR (read fast boot register) can
be used to verify the program state of the Fast Boot Register.
The default number of delay cycles is 12 cycles (11h), and there is
a 8bytes boundary address for the start of boot code access.
When CS# starts to go low, data begins to output from default
address after the delay cycles (default as 12 cycles). After CS#
returns to go high, the device will go back to standard SPI mode
and user can start to input command. In the fast boot data out
process from CS# goes low to CS# goes high, a minimum of one
byte must be output.
Figure 45. Performance Enhance Mode Reset for Fast Read Quad
I/O using 4Byte Address Sequence (QPI Mode)
Once Fast Boot feature has been enabled, the device will
automatically start a read operation after power on cycle, reset
command, or hardware reset operation.
9.23. Fast Boot
The fast Boot feature can support Single I/O and Quad I/O
interface. If the QE bit of Status Register is “0”, the data is output
by Single I/O interface. If the QE bit of Status Register is set to
“1”, the data is output by Quad I/O interface.
The Fast Boot Feature provides the ability to automatically execute
read operation after power on cycle or reset without any read
instruction.
A Fast Boot Register is provided on this device. It can enable the
Fast Boot Register (FBR)
Bits
Description
Bit Status
Default State
Type
31 to 4
FBSA (FastBoot Start Address)
16 bytes boundary address for the FFFFFFF
Non- Volatile
start of boot code access.
1
3
x
Non- Volatile
Non- Volatile
2 to 1
FBSD (FastBoot Start Delay Cycle)
00: 6 delay cycles
11
01: 8 delay cycles
10: 10 delay cycles
11: 12 delay cycles
0=FastBoot is enabled.
1=FastBoot is not enabled.
0
FBE (FastBoot Enable)
1
Non- Volatile
Note: If FBSD = 11, the maximum clock frequency is 133 MHz
If FBSD = 10, the maximum clock frequency is 104 MHz
If FBSD = 01, the maximum clock frequency is 84 MHz
If FBSD = 00, the maximum clock frequency is 70 MHz
Figure 46. Fast Boot Sequence (QE=0)
Figure 47. Fast Boot Sequence (QE=1)
© Generalplus Technology Inc.
Proprietary & Confidential
32
Jan 21, 2013
Version: 1.0
GPR25L25605F
Figure 48. Read Fast Boot Register (RDFBR) Sequence
cleared. If the Block is protected by BP bits (WPSEL=0; Block
Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect
Mode), the Sector Erase (SE) instruction will not be executed on
the block.
Figure 51. Sector Erase (SE) Sequence (SPI Mode)
Figure 49. Write Fast Boot Register (WRFBR) Sequence
Note: Please note the address cycles above are based on 3-byte address
mode. For 4-byte address mode, the address cycles will be increased.
Figure 52. Sector Erase (SE) Sequence (QPI Mode)
Figure 50. Erase Fast Boot Register (ESFBR) Sequence
Note: Please note the address cycles above are based on 3-byte address
mode. For 4-byte address mode, the address cycles will be increased.
9.25. Block Erase (BE32K)
9.24. Sector Erase (SE)
The Block Erase (BE32K) instruction is for erasing the data of the
chosen block to be "1". The instruction is used for 32K-byte block
erase operation. A Write Enable (WREN) instruction be executed
to set the Write Enable Latch (WEL) bit before sending the Block
Erase (BE32K). Any address of the block (see "Table 4. Memory
The Sector Erase (SE) instruction is for erasing the data of the
chosen sector to be "1". The instruction is used for any 4K-byte
sector. A Write Enable (WREN) instruction must execute to set
the Write Enable Latch (WEL) bit before sending the Sector Erase
Organization") is
a valid address for Block Erase (BE32K)
(SE).
Any address of the sector (see "Table 4. Memory
instruction. The CS# must go high exactly at the byte boundary
(the least significant bit of address byte been latched-in); otherwise,
the instruction will be rejected and not executed.
Organization") is a valid address for Sector Erase (SE) instruction.
The CS# must go high exactly at the byte boundary (the least
significant bit of the address byte been latched-in); otherwise, the
instruction will be rejected and not executed.
Address bits [Am-A15] (Am is the most significant address) select
the 32KB block address. The default read mode is 3-byte
address, to access higher address (4-byte address) which requires
to enter the 4-byte address read mode or to define EAR bit. To
enter the 4-byte address mode, please refer to the enter 4-byte
mode (EN4B) Mode section.
The default read mode is 3-byte address, to access higher
address (4-byte address) which requires to enter the 4-byte
address read mode or to define EAR bit. Address bits [Am-A12]
(Am is the most significant address) select the sector address.
To enter the 4-byte address mode, please refer to the enter 4-byte
mode (EN4B) Mode section.
The sequence of issuing BE32K instruction is: CS# goes low→
sending BE32K instruction code→ 3-byte or 4-byte address on
SI→CS# goes high.
The sequence of issuing SE instruction is: CS# goes low→
sending SE instruction code→ 3-byte or 4-byte address on SI→
CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The self-timed Block Erase Cycle time (tBE32K) is initiated as
soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be checked while during the Block Erase cycle is
in progress. The WIP sets during the tBE32K timing, and clears
when Block Erase Cycle is completed, and the Write Enable Latch
(WEL) bit is cleared. If the Block is protected by BP bits
The self-timed Sector Erase Cycle time (tSE) is initiated as soon
as Chip Select (CS#) goes high. The Write in Progress (WIP) bit
still can be checked while the Sector Erase cycle is in progress.
The WIP sets 1 during the tSE timing, and clears when Sector
Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
© Generalplus Technology Inc.
Proprietary & Confidential
33
Jan 21, 2013
Version: 1.0
GPR25L25605F
(WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1;
Advanced Sector Protect Mode), the Block Erase (BE32K)
instruction will not be executed on the block.
Figure 55. Block Erase (BE) Sequence (SPI Mode)
Figure 53. Block Erase 32KB (BE32K) Sequence (SPI Mode)
Note: Please note the address cycles above are based on 3-byte address
mode. For 4-byte address mode, the address cycles will be increased.
Figure 56. Block Erase (BE) Sequence (QPI Mode)
Note: Please note the address cycles above are based on 3-byte address
mode. For 4-byte address mode, the address cycles will be increased.
Figure 54. Block Erase 32KB (BE32K) Sequence (QPI Mode)
Note: Please note the address cycles above are based on 3-byte address
mode. For 4-byte address mode, the address cycles will be increased.
Note: Please note the address cycles above are based on 3-byte address
9.27. Chip Erase (CE)
mode. For 4-byte address mode, the address cycles will be increased.
The Chip Erase (CE) instruction is for erasing the data of the
whole chip to be "1". A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit before sending
the Chip Erase (CE). The CS# must go high exactly at the byte
boundary, otherwise the instruction will be rejected and not
executed.
9.26. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the
chosen block to be "1". The instruction is used for 64K-byte block
erase operation. A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit before sending
the Block Erase (BE). Any address of the block (Please refer to
"Table 4. Memory Organization") is a valid address for Block Erase
(BE) instruction. The CS# must go high exactly at the byte
boundary (the least significant bit of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
The default read mode is 3-byte address, to access higher
address (4-byte address) which requires to enter the 4-byte
address read mode or to define EAR bit. To enter the 4-byte
address mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
The sequence of issuing CE instruction is: CS# goes low→sending
CE instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as
Chip Select (CS#) goes high. The Write in Progress (WIP) bit still
can be checked while the Chip Erase cycle is in progress. The
WIP sets during the tCE timing, and clears when Chip Erase Cycle
is completed, and the Write Enable Latch (WEL) bit is cleared.
When the chip is under "Block protect (BP) Mode" (WPSEL=0).
The Chip Erase (CE) instruction will not be executed, if one (or
more) sector is protected by BP3-BP0 bits. It will be only
executed when BP3-BP0 all set to "0".
The sequence of issuing BE instruction is: CS# goes low→
sending BE instruction code→ 3-byte or 4-byte address on SI→
CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
When the chip is under "Advances Sector Protect Mode"
(WPSEL=1). The Chip Erase (CE) instruction will be executed on
unprotected block. The protected Block will be skipped. If one
(or more) 4K byte sector was protected in top or bottom 64K byte
block, the protected block will also skip the chip erase command.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as
Chip Select (CS#) goes high. The Write in Progress (WIP) bit still
can be checked while the Block Erase cycle is in progress. The
WIP sets during the tBE timing, and clears when Block Erase
Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
If the Block is protected by BP bits (WPSEL=0; Block Protect
Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode),
the Block Erase (BE) instruction will not be executed on the block.
Figure 57. Chip Erase (CE) Sequence (SPI Mode)
© Generalplus Technology Inc.
Proprietary & Confidential
34
Jan 21, 2013
Version: 1.0
GPR25L25605F
Figure 58. Chip Erase (CE) Sequence (QPI Mode)
Figure 59. Page Program (PP) Sequence (SPI Mode)
9.28. Page Program (PP)
The Page Program (PP) instruction is for programming the
memory to be "0". A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit before sending
the Page Program (PP). The device programs only the last 256
data bytes sent to the device. If the entire 256 data bytes are
going to be programmed, A7-A0 (The eight least significant
address bits) should be set to 0. If the eight least significant
address bits (A7-A0) are not all 0, all transmitted data going
beyond the end of the current page are programmed from the start
address of the same page (from the address A7-A0 are all 0). If
more than 256 bytes are sent to the device, the data of the last
256-byte is programmed at the requested page and previous data
will be disregarded. If less than 256 bytes are sent to the device,
the data is programmed at the requested address of the page
without effect on other address of the same page.
Note: Please note the address cycles above are based on 3-byte address
mode. For 4-byte address mode, the address cycles will be increased.
Figure 60. Page Program (PP) Sequence (QPI Mode)
Note: Please note the address cycles above are based on 3-byte address
mode. For 4-byte address mode, the address cycles will be increased.
9.29. 4 x I/O Page Program (4PP)
The default read mode is 3-byte address, to access higher
address (4-byte address) which requires to enter the 4-byte
address read mode or to define EAR bit. To enter the 4-byte
address mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
The Quad Page Program (4PP) instruction is for programming the
memory to be "0". A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit and Quad
Enable (QE) bit must be set to "1" before sending the Quad Page
Program (4PP). The Quad Page Programming takes four pins:
SIO0, SIO1, SIO2, and SIO3 as address and data input, which can
improve programmer performance and the effectiveness of
application. The other function descriptions are as same as
standard page program.
The sequence of issuing PP instruction is: CS# goes low→
sending PP instruction code→ 3-byte or 4-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program
cycle; The CS# must go high exactly at the byte boundary( the
latest eighth bit of data being latched in), otherwise the instruction
will be rejected and will not be executed.
The default read mode is 3-byte address, to access higher
address (4-byte address) which requires to enter the 4-byte
address read mode or to define EAR bit. To enter the 4-byte
address mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
The self-timed Page Program Cycle time (tPP) is initiated as soon
as Chip Select (CS#) goes high. The Write in Progress (WIP) bit
still can be checked while the Page Program cycle is in progress.
The WIP sets during the tPP timing, and clears when Page
Program Cycle is completed, and the Write Enable Latch (WEL) bit
is cleared. If the page is protected by BP bits (WPSEL=0; Block
Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect
Mode), the Page Program (PP) instruction will not be executed.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The sequence of issuing 4PP instruction is: CS# goes low→
sending 4PP instruction code→ 3-byte or 4-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.
If the page is protected by BP bits (WPSEL=0; Block Protect Mode)
or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode), the
Quad Page Program (4PP) instruction will not be executed.
© Generalplus Technology Inc.
Proprietary & Confidential
35
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.31. Enter Secured OTP (ENSO)
Figure 61. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)
The ENSO instruction is for entering the additional 4K-bit secured
OTP mode. While device is in 4K-bit secured OTP mode, main
array access is not available. The additional 4K-bit secured OTP
is independent from main array and may be used to store unique
serial number for system identifier. After entering the Secured
OTP mode, follow standard read or program procedure to read out
the data or update data. The Secured OTP data cannot be
updated again once it is lock-down.
Note: Please note the address cycles above are based on 3-byte address
mode. For 4-byte address mode, the address cycles will be increased.
The sequence of issuing ENSO instruction is: CS# goes low→
sending ENSO instruction to enter Secured OTP mode→ CS#
goes high.
9.30. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to
minimum power consumption (the standby current is reduced from
ISB1 to ISB2). The Deep Power-down mode requires the Deep
Power-down (DP) instruction to enter, during the Deep
Power-down mode, the device is not active and all
Write/Program/Erase instruction are ignored. When CS# goes
high, it's only in deep power-down mode not standby mode. It's
different from Standby mode.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
Please note that after issuing ENSO command user can only
access secure OTP region with standard read or program
procedure. Furthermore, once security OTP is lock down, only
read related commands are valid.
9.32. Exit Secured OTP (EXSO)
The sequence of issuing DP instruction is: CS# goes low→sending
DP instruction code→CS# goes high.
The EXSO instruction is for exiting the additional 4K-bit secured
OTP mode.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The sequence of issuing EXSO instruction is: CS# goes low→
sending EXSO instruction to exit Secured OTP mode→ CS# goes
high.
Once the DP instruction is set, all instruction will be ignored except
the Release from Deep Power-down mode (RDP) and Read
Electronic Signature (RES) instruction and softreset command.
(those instructions allow the ID being reading out). When
Power-down, or software reset command the deep power-down
mode automatically stops, and when power-up, the device
automatically is in standby mode. For DP instruction the CS#
must go high exactly at the byte boundary (the latest eighth bit of
instruction code been latched-in); otherwise, the instruction will not
executed. As soon as Chip Select (CS#) goes high, a delay of
tDP is required before entering the Deep Power-down mode.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
9.33. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security
Register bits. The Read Security Register can be read at any
time (even in program/erase/write status register/write security
register condition) and continuously.
The sequence of issuing RDSCUR instruction is: CS# goes
low→sending RDSCUR instruction→Security Register data out on
SO→ CS# goes high.
Figure 62. Deep Power-down (DP) Sequence (SPI Mode)
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
9.34. Write Security Register (WRSCUR)
Figure 63. Deep Power-down (DP) Sequence (QPI Mode)
The WRSCUR instruction is for changing the values of Security
Register Bits. The WREN (Write Enable) instruction is required
before issuing WRSCUR instruction. The WRSCUR instruction
may change the values of bit1 (LDSO bit) for customer to
lock-down the 4K-bit Secured OTP area. Once the LDSO bit is
© Generalplus Technology Inc.
Proprietary & Confidential
36
Jan 21, 2013
Version: 1.0
GPR25L25605F
set to "1", the Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is: CS# goes low→
sending WRSCUR instruction → CS# goes high.
it will not interrupt or stop any operation in the flash memory.
Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status
of Erase Suspend operation. Users may use ESB to identify the
state of flash memory. After the flash memory is suspended by
Erase Suspend command, ESB is set to "1". ESB is cleared to
"0" after erase operation resumes.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The CS# must go high exactly at the boundary; otherwise, the
instruction will be rejected and not executed.
Program Suspend bit. Program Suspend Bit (PSB) indicates the
status of Program Suspend operation. Users may use PSB to
identify the state of flash memory. After the flash memory is
suspended by Program Suspend command, PSB is set to "1".
PSB is cleared to "0" after program operation resumes.
Security Register
The definition of the Security Register bits is as below:
Write Protection Selection bit. Please reference to "Write
Protection Selection bit".
Secured OTP Indicator bit. The Secured OTP indicator bit shows
the chip is locked by factory or not. When it is "0", it indicates
non-factory lock; "1" indicates factory-lock.
Erase Fail bit. The Erase Fail bit is a status flag, which shows the
status of last Erase operation. It will be set to "1", if the erase
operation fails or the erase region is protected. It will be set to "0",
if the last operation is success. Please note that it will not
interrupt or stop any operation in the flash memory.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR
instruction, the LDSO bit may be set to "1" for customer lock-down
purpose. However, once the bit is set to "1" (lock-down), the
LDSO bit and the 4K-bit Secured OTP area cannot be updated
any more. While it is in 4K-bit secured OTP mode, main array
access is not allowed.
Program Fail bit. The Program Fail bit is a status flag, which
shows the status of last Program operation. It will be set to "1", if
the program operation fails or the program region is protected. It
will be set to "0", if the last operation is success. Please note that
Table 8. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
WPSEL
E_FAIL
P_FAIL
Reserved ESB
PSB
LDSO
Secured OTP
indicator bit
(Erase Suspend (Program
bit) Suspend bit)
(indicate if
lock-down)
0=normal
mode
WP 0=normal Erase 0=normal
-
0=Erase is not 0=Program is 0 = not lock-down 0 = non-factory
succeed
Program succeed
suspended
1=
not suspended
Erase 1= Program (cannot program/ 1 = factory lock
suspended
(default=0)
Volatile bit
1
=
lock-down lock
1=individual
mode
1=individual
Erase failed
(default=0)
1=indicate
Program failed
(default=0)
Volatile bit
suspended
(default=0)
erase OTP)
(default=0)
Non-volatile bit Volatile bit
(OTP)
Volatile bit Volatile bit
Non-volatile bit
(OTP)
Non-volatile bit
(OTP)
9.35. Write Protection Selection (WPSEL)
There are two write protection methods provided on this device, (1)
Block Lock (BP) protection mode (2) Advanced Sector protection
mode. If WPSEL=0, flash is under BP protection mode. If
WPSEL=1, flash is under Advanced Sector protection mode. The
default value of WPSEL is “0”. WPSEL command can be used to
set WPSEL=1. Please note that WPSEL is an OTP bit. Once
WPSEL is set to 1, there is no chance to recovery WPSEL
back to “0”. If the flash is put on BP mode, the Advanced Sector
sectors will be write protected by Dynamic Protected Bit (DPB)
in default. User may only unlock the blocks or sectors via
GBULK instruction. Program or erase functions can only be
operated after the Unlock instruction is conducted.
When WPSEL = 0: Block Lock (BP) protection mode,
Array is protected by BP3~BP0 and BP bits are protected by
“SRWD=1 and WP#=0”, where SRWD is bit 7 of status register
that can be set by WRSR command.
protection mode is disabled.
Contrarily, if flash is on the
When WPSEL =1: Advanced Sector protection mode,
Advanced Sector protection mode, the BP mode is disabled.
Every time after the system is powered-on, and the Security
Register bit 7 is checked to be WPSEL=1, all the blocks or
Blocks are individually protected by their own SPB or DPB lock
bits which are set to “1” after power up. When the system
accepts and executes WPSEL instruction, the bit 7 in security
© Generalplus Technology Inc.
Proprietary & Confidential
37
Jan 21, 2013
Version: 1.0
GPR25L25605F
register will be set. It will activate WRLR, RDLR, WRPASS,
RDPASS, PASSULK, WRSPB, ESSPB, SPBLK, RDSPBLK,
WRDPB, RDDPB, GBLK, GBULK etc instructions to conduct block
lock protection and replace the original Software Protect Mode
(SPM) use (BP3~BP0) indicated block methods. Under the
Advanced Sector protection mode (WPSEL=1), hardware
protection is performed by driving WP#=0. Once WP#=0 all array
blocks/sectors are protected regardless of the contents of SPB or
DPB lock bits.
mode → CS# goes high.
Write Protection Selection
The sequence of issuing WPSEL instruction is: CS# goes low →
sending WPSEL instruction to enter the individual block protect
Figure 64. WPSEL Flow
© Generalplus Technology Inc.
Proprietary & Confidential
38
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.36. Advanced Sector Protection
There are two ways to implement software Advanced Sector
Protection on this device: Password method or Solid method.
Through these two protection methods, user can disable or enable
the programming or erasing operation to any individual sector or
all sectors.
sectors is protected from programming or erasing operation when
the bit is set.
The figure below helps describing an overview of these methods.
The device is default to the Solid mode when shipped from factory.
The detail algorithm of advance sector protection is shown as
follows:
There is a non-volatile (SPB) and volatile (DPB) protection bit
related to the single sector in main flash array. Each of the
Figure 65. Advanced Sector Protection Overview
© Generalplus Technology Inc.
Proprietary & Confidential
39
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.36.1. Lock Register
User can choose favorite sector protecting method via setting Lock
Register bits 1 and 2. Lock Register is a 16- bit one-time
programmable register. Once bit 1 or bit2 has been programming
(set to "0"), they will be locked in that mode and the others will be
disabled permanently. bit1 and bit2 can not be programmed at
the same time, otherwise the device will abort the operation.
If user selects Password Protection mode, the password setting is
required. User can set password by issuing password program
command.
There is no software command sequence requested to unlocks
this bit, unless the device is in the password protection mode. To
clear the SPB lock bit, just take the device through a reset or a
power-up cycle. In order to prevent modified, the SPB Lock Bit
must be set after all SPBs are setting the desired status.
SPB Lock Register
Bit
7-1
0
Description Bit Status Default
Type
Reserved
SPBLK
X
0000000
0= SPB bit Solid
protected
Volatile
Volatile
Lock Register
(Lock SPB protected
Bit 15-3
Bit 2
Bit 1
Bit0
Bit)
1=SPB bit Mode=1
unprotected Password
Protected
Reserved
Password
Solid
Protection Reserved
Protection Mode Mode Lock Bit
Lock Bit
Mode=0
x
0=Password
0=Solid Protection x
Protection Mode Mode Enable
Figure 68. SPB Lock Bit Set (SPBLK) Sequence
Enable
1= Solid
1= Password
Protection Mode
Protection Mode not enable
not enable
(Default =1)
OTP
(Default =1)
OTP
Figure 69. Read SPB Lock Register (RDSPBLK) Sequence
OTP
OTP
Notes:
1.while bit2 or bit1 has been "0" status, other bit can't be changed any more.
If set lock register program mode, program fail will be set to "1".
2. While bit2 and bit 1 is "1" status, other bits can be programed, program
fail will be set to "1".
Figure 66. Read Lock Register (RDLR) Sequence
Figure 67. Write Lock Register (WRLR) Sequence (SPI Mode)
9.36.2. SPB Lock Bit (SPBLB)
9.36.3. Solid Protection Bits
The Solid write Protection bit (SPB) is a nonvolatile bit with the
same endurances as the Flash memory. It is assigned to each
sector individually.
The SPB is Preprogramming, and its
verification prior to erasure are managed by the device, so system
monitoring is not necessary.
When a SPB is set to “1”, the associated sector is protected,
preventing any program or erase operation on this sector. The
SPB bits are set individually by SPB program command.
However, it cannot be cleared individually.
Issuing the All SPB Erase command will erase all SPB in the same
time.
If one of the protected sector need to be unprotected
(corresponding SPB clear to “0”), a few more steps are required.
First, the SPB lock bit must be cleared by PASSWD unlock
command if lock register bit2 is set to "1" or by a power-on cycle or
hardware reset if lock register bit1 is set to "1". The SPBs can
then be changed to reflect the desired settings. Setting the SPB
Lock Bit once again locks the SPBs, and the device operates
The Solid Protection Bit Lock Bit (SPBLB) is assigned to control all
SPB status. It is a unique and volatile.
The default status of this register is determined by Lock Register
bit 1 and bit 2 status. Refer to SPB Lock Register for more SPB
Lock information.
© Generalplus Technology Inc.
Proprietary & Confidential
40
Jan 21, 2013
Version: 1.0
GPR25L25605F
normally again.
Program command, then placing each sector in the protected or
unprotected state separately. After the DPB state is set to “0”, the
sector may be modified depending on the SPB state of that sector.
The DPBs are protected (FFh) upon power up or reset. Program
or erase function can only be operated after the unlock instruction
is conducted.
To verify the programming state of the SPB for a given sector,
issuing a SPB Read Command to the device is required.
Note:
1. Once SPB Lock Bit is set, its Program or erase command will not be
executed and times-out without programming or erasing the SPB.
DPB Register (DPBR)
Bit
Description
DPB (Dynamic 00h= DPB for the FFh
protected Bit) sector address
unprotected
FFh=DPB for the
Bit Status
Default Type
SPB Register (SPBR)
7 to 0
Volatile
Bit Description
7 to 0 SPB (Solid 00h= SPB for the 00h
protected Bit) sector address
unprotected
FFh= SPB for the
Bit Status
Default
Type
Non-vo
latile
sector
address
protected
sector
address
protected
Figure 73. Read DPB Register (RDDPB) Sequence
Figure 70. Read SPB Status (RDSPB) Sequence
Figure 74. Write DPB Register (WRDPB) Sequence
Figure 71. SPB Erase (ESSPB) Sequence
9.36.5. Gang Block Lock/Unlock (GBLK/GBULK)
Figure 72. SPB Program (WRSPB) Sequence
These instructions are only effective after WPSEL was executed.
The GBLK/GBULK instruction is
a chip-based protected or
unprotected operation. It can enable or disable all DPB.
The WREN (Write Enable) instruction is required before issuing
GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes
low → send GBLK/GBULK (7Eh/98h) instruction →CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
9.36.4. Dynamic Write Protection Bits
The Dynamic Protection allows the software application to easily
protect sectors against inadvertent change. However, the
protection can be easily disabled when changes are necessary.
All Dynamic Protection bits (DPB) are volatile and assigned to
each sector. They can be modified individually. DPBs provide
the protection scheme only for unprotected sectors that have their
SPBs cleared. To modify the DPB status by issuing the DPB
The CS# must go high exactly at the byte boundary, otherwise, the
instruction will be rejected and not be executed.
© Generalplus Technology Inc.
Proprietary & Confidential
41
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.36.6. Sector Protection States Summary Table
Protection Status
Sector State
DPB bit
Unprotect
Unprotect
Unprotect
Unprotect
Protect
SPB bit
Unprotect
Unprotect
Protect
SPB Lock bit
lock
Unprotect – SPB is unchangeable
un-lock
lock
Unprotect – SPB is changeable
Protect – SPB is unchangeable
Protect – SPB is changeable
Protect – SPB is unchangeable
Protect – SPB is changeable
Protect – SPB is unchangeable
Protect – SPB is changeable
Protect
un-lock
lock
Unprotect
Unprotect
Protect
Protect
un-lock
lock
Protect
Protect
Protect
un-lock
9.36.7. Password Protection Mode
All 64-bit password combinations are valid as a password. No
special address is required for programming the password. The
password is no longer readable after the Password Protection
mode is selected by programming Lock register bit 2 to "0".
Once sector under protected status, device will ignores the
program/erase command, enable status polling and returns to read
mode without contents change. The DPB, SPB and SPB lock bit
status of each sector can be verified by issuing DPB, SPB and
SPB Lock bit read commands.
The security level of Password Protection Method is higher than
the Solid protection mode. The 64 bit password is requested
before modify SPB lock bit status. When device is under
password protection mode, the SPB lock bit is set “0”, after a
power-up cycle or Reset Command.
A correct password is required for password Unlock command, to
unlock the SPB lock bit. Await 2us is necessary to unlocked the
device after valid password is given. After that, the SPB bits are
allows to be changed. The Password Unlock command are
issued slower than 2 μs every time, to prevent hacker from trying
all the 64-bit password combinations.
● The unlock operation may fail if the password provided by
password unlock command does not match the previously entered
password. It causes the same result when a programming
operation is performed on a protected sector. The P_ERR bit is
set to 1 and the WIP Bit remains set.
To place the device in password protection mode, a few more
steps are required.
First, prior to entering the password
● It is not allowed to execute the Password Unlock command
faster than every 100us ± 20us. The reason behind it is to make
it impossible to hack into the system by running through all the
combinations of a set of 64-bit password (58 million years). To
verify if the device has completed the password unlock command
and is available to process a new password command, the Read
Status Register command is needed to read the WIP bit. When a
valid password is provided the password unlock command does
not insert the 100us delay before returning the WIP bit to zero.
● It is not feasible to set the SPB Lock bit if the password is
missing after the Password Mode is selected.
protection mode, it is necessary to set a 64-bit password to verify it.
Password verification is only allowed during the password
programming operation. Second, the password protection mode
is then activated by programming the Password Protection Mode
Lock Bit to”0”. This operation is not reversible. Once the bit is
programmed, it cannot be erased, and the device remains
permanently in password protection mode, and the 64-bit
password can neither be retrieved nor reprogrammed. Moreover,
all commands to the address where the password is stored are
disabled.
The password is all “1”s when shipped from the factory, it is only
capable of programming "0"s under password program command.
Password Register (PASS)
Bits
Field Name
Function
Type
Default State
FFFFFFFFFFFFFFFFh
Description
63 to 0
PWD
Hidden Password
OTP
Non-volatile OTP storage of 64 bit password.
The password is no longer readable after the
password protection mode is selected by
programming Lock register bit 2 to zero.
© Generalplus Technology Inc.
Proprietary & Confidential
42
Jan 21, 2013
Version: 1.0
GPR25L25605F
9.37. Program/Erase Suspend/Resume
9.39. Write-Resume
The device allow the interruption of Sector-Erase, Block-Erase or
Page-Program operations and conduct other operations.
After issue suspend command, the system can determine if the
device has entered the Erase-Suspended mode through Bit2 (PSB)
and Bit3 (ESB) of security register. (please refer to "Table 8.
Security Register Definition")
The Write operation is being resumed when Write-Resume
instruction issued. ESB or PSB (suspend status bit) in Status
register will be changed back to “0”
The operation of Write-Resume is as follows: CS# drives low →
send write resume command cycle (30H) → drive CS# high. By
polling Busy Bit in status register, the internal write operation
status could be checked to be completed or not. The user may
also wait the time lag of TSE, TBE, TPP for Sector-erase,
Block-erase or Page-programming. WREN (command "06" is not
required to issue before resume. Resume to another suspend
operation requires latency time of 1ms.
The latency time of erase operation:
Suspend to suspend ready timing: 20us.
Resume to another suspend timing: 1ms.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
Please note that, if "performance enhance mode" is executed
during suspend operation, the device can not be resume. To
restart the write command, disable the "performance enhance
mode" is required. After the "performance enhance mode" is
disable, the write-resume command is effective.
9.38. Erase Suspend
Erase suspend allow the interruption of all erase operations.
After the device has entered Erase-Suspended mode, the system
can read any sector(s) or Block(s) except those being erased by
the suspended erase operation. Reading the sector or Block
being erase suspended is invalid.
9.40. No Operation (NOP)
The “No Operation” command is only able to terminate the Reset
Enable (RSTEN) command and will not affect any other command.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
After erase suspend, WEL bit will be clear, only read related,
resume and reset command can be accepted. (including: 03h, 0Bh,
3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h,
ABh, 90h, 02h, 38h, B1h, C1h, B0h, 30h, 66h, 99h, 00h, 35h, F5h,
15h, 2Dh, 27h, A7h, E2h, E0h, 16h)
9.41. Software Reset (Reset-Enable (RSTEN) and
Reset (RST))
If the system issues an Erase Suspend command after the sector
erase operation has already begun, the device will not enter
Erase-Suspended mode until 20us time has elapsed.
The Software Reset operation combines two instructions:
Reset-Enable (RSTEN) command and Reset (RST) command. It
returns the device to standby mode. All the volatile bits and
settings will be cleared then, which makes the device return to the
default status as power on.
Erase Suspend Bit (ESB) indicates the status of Erase Suspend
operation. Users may use ESB to identify the state of flash
memory. After the flash memory is suspended by Erase Suspend
command, ESB is set to "1". ESB is cleared to "0" after erase
operation resumes.
To execute Reset command (RST), the Reset-Enable (RSTEN)
command must be executed first to perform the Reset operation.
If there is any other command to interrupt after the Reset-Enable
command, the Reset-Enable will be invalid.
Figure 75. Suspend to Read Latency
Figure 76. Resume to Read Latency
Figure 77. Resume to Suspend Latency
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
If the Reset command is executed during program or erase
operation, the operation will be disabled, the data under
processing could be damaged or lost.
The reset time is different depending on the last operation. For
details, please refer to "Table 12. Reset Timing" for tRHSL timing.
© Generalplus Technology Inc.
Proprietary & Confidential
43
Jan 21, 2013
Version: 1.0
GPR25L25605F
Figure 78. Software Reset Recovery
needed to accommodate divergent features from multiple vendors.
The concept is similar to the one found in the Introduction of
JEDEC Standard, JESD68 on CFI.
The sequence of issuing RDSFDP instruction is CS# goes
low→send RDSFDP instruction (5Ah)→send 3 address bytes on
SI pin→send 1 dummy byte on SI pin→read SFDP code on
SO→to end RDSFDP operation can use CS# to high at any time
during data out.
Note: Refer to "Table 12. Reset Timing" for tRHSL data.
Figure 79. Reset Sequence (SPI mode)
SFDP is a JEDEC standard, JESD216.
Figure 81. Read Serial Flash Discoverable Parameter (RDSFDP)
Sequence
Figure 80. Reset Sequence (QPI mode)
9.42. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard
provides a consistent method of describing the functional and
feature capabilities of serial flash devices in a standard set of
internal parameter tables.
These parameter tables can be
interrogated by host system software to enable adjustments
© Generalplus Technology Inc.
Proprietary & Confidential
44
Jan 21, 2013
Version: 1.0
GPR25L25605F
Table 9. Signature and Parameter Identification Data Values
Description
Comment
Add (h)
(Byte)
DW Add
(Bit)
Data
Data
(h)
(h/b) note1
SFDP Signature
Fixed: 50444653h
00h
01h
02h
03h
07:00
15:08
23:16
31:24
53h
46h
44h
50h
53h
46h
44h
50h
SFDP
Minor
Major
of
Revision Start from 00h
Revision Start from 01h
04h
05h
06h
07:00
15:08
23:16
00h
01h
01h
00h
01h
01h
Number
SFDP
Number
Number
Headers
Unused
Parameter This number is 0-based. Therefore,
indicates 1 parameter header.
0
07h
08h
31:24
07:00
FFh
00h
FFh
00h
ID number (JEDEC)
00h: it indicates a JEDEC specified header.
Parameter Table Minor Start from 00h
Revision Number
09h
0Ah
0Bh
15:08
23:16
31:24
00h
01h
09h
00h
01h
09h
Parameter Table Major Start from 01h
Revision Number
Parameter Table Length
(in double word)
How many DWORDs in the Parameter table
Parameter Table Pointer First address of JEDEC Flash Parameter
0Ch
0Dh
0Eh
0Fh
07:00
15:08
23:16
31:24
30h
00h
00h
FFh
30h
00h
00h
FFh
(PTP)
table
Unused
ID number
it indicates Manufacturer ID
10h
11h
12h
13h
07:00
15:08
23:16
31:24
C2h
00h
01h
04h
C2h
00h
01h
04h
(Manufacturer ID)
Parameter Table Minor Start from 00h
Revision Number
Parameter Table Major Start from 01h
Revision Number
Parameter Table Length
How many DWORDs in the Parameter table
(in double word)
Parameter Table Pointer First address of Flash Parameter table
(PTP)
14h
15h
16h
17h
07:00
15:08
23:16
31:24
60h
00h
00h
FFh
60h
00h
00h
FFh
Unused
© Generalplus Technology Inc.
Proprietary & Confidential
45
Jan 21, 2013
Version: 1.0
GPR25L25605F
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables
Description
Comment
Add (h)
(Byte)
DW Add
(Bit)
Data
Data
(h)
(h/b) note1
Block/Sector Erase sizes
Write Granularity
00: Reserved, 01: 4KB erase, 10:
Reserved, 11: not support 4KB erase
0: 1Byte, 1: 64Byte or larger
01:00
02
01b
1b
Write Enable Instruction 0: not required
Required for Writing to 1: required 00h to be written to the status
03
0b
30h
E5h
Volatile Status Registers
register
Write Enable Opcode Select 0: use 50h opcode, 1: use 06h opcode
for Writing to Volatile Status Note: If target flash status register is
04
0b
Registers
nonvolatile, then bits 3 and 4 must be set
to 00b.
Unused
Contains 111b and can never be changed
07:05
15:08
16
111b
20h
1b
4KB Erase Opcode
(1-1-2) Fast Read (Note2)
31h
32h
20h
F3h
FFh
0=not support 1=support
Address Bytes Number used 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte
in addressing flash array only, 11: Reserved
18:17
19
01b
0b
Double Transfer Rate (DTR) 0=not support 1=support
Clocking
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
20
21
1b
1b
22
1b
23
1b
Unused
33h
31:24
31:00
FFh
Flash Memory Density
37h:34h
0FFF FFFFh
(1-4-4) Fast Read Number of 0 0000b: Wait states (Dummy Clocks) not
Wait states (Note3) support
04:00
0 0100b
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
44h
EBh
08h
6Bh
08h
3Bh
04h
BBh
(1-4-4) Fast Read Number of 000b: Mode Bits not support
Mode Bits (Note4)
07:05
15:08
20:16
010b
EBh
(1-4-4) Fast Read Opcode
(1-1-4) Fast Read Number of 0 0000b: Wait states (Dummy Clocks) not
0 1000b
Wait states
support
(1-1-4) Fast Read Number of 000b: Mode Bits not support
Mode Bits
23:21
31:24
04:00
000b
6Bh
(1-1-4) Fast Read Opcode
(1-1-2) Fast Read Number of 0 0000b: Wait states (Dummy Clocks) not
0 1000b
Wait states
supported
(1-1-2) Fast Read Number of 000b: Mode Bits not supported
Mode Bits
07:05
15:08
20:16
000b
3Bh
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number of 0 0000b: Wait states (Dummy Clocks) not
0 0100b
Wait states
supported
(1-2-2) Fast Read Number of 000b: Mode Bits not supported
23:21
31:24
000b
BBh
Mode Bits
(1-2-2) Fast Read Opcode
© Generalplus Technology Inc.
Proprietary & Confidential
46
Jan 21, 2013
Version: 1.0
GPR25L25605F
Description
Comment
Add (h)
(Byte)
DW Add
(Bit)
Data
Data
(h)
(h/b) note1
(2-2-2) Fast Read
0=not support 1=support
00
0b
Unused
03:01
04
111b
1b
40h
FEh
(4-4-4) Fast Read
Unused
0=not support 1=support
07:05
31:08
15:00
111b
FFh
FFh
Unused
43h:41h
45h:44h
FFh
FFh
Unused
(2-2-2) Fast Read Number of 0 0000b: Wait states (Dummy Clocks) not
Wait states supported
20:16
23:21
0 0000b
000b
46h
00h
(2-2-2) Fast Read Number of 000b: Mode Bits not supported
Mode Bits
(2-2-2) Fast Read Opcode
47h
31:24
15:00
FFh
FFh
FFh
FFh
Unused
49h:48h
(4-4-4) Fast Read Number of 0 0000b: Wait states (Dummy Clocks) not
20:16
0 0100b
Wait states
supported
4Ah
44h
(4-4-4) Fast Read Number of 000b: Mode Bits not supported
23:21
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
010b
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
Mode Bits
(4-4-4) Fast Read Opcode
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
Sector Type 1 Size
Sector/block size = 2^N bytes (Note5) 0x00b:
this sector type doesn't exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes 0x00b: this
sector type doesn't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes 0x00b: this
sector type doesn't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes 0x00b: this
sector type doesn't exist
Sector Type 4 erase Opcode
© Generalplus Technology Inc.
Proprietary & Confidential
47
Jan 21, 2013
Version: 1.0
GPR25L25605F
Table 11. Parameter Table (1): Flash Parameter Tables
Description
Comment
Add (h)
(Byte)
DW Add
(Bit)
Data
Data
(h)
(h/b) note1
Vcc Supply Maximum Voltage
2000h=2.000V
07:00
15:08
00h
36h
00h
36h
2700h=2.700V
61h:60h
63h:62h
3600h=3.600V
Vcc Supply Minimum Voltage
1650h=1.650V
2250h=2.250V
23:16
31:24
00h
27h
00h
27h
2350h=2.350V
2700h=2.700V
H/W Reset# pin
H/W Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
0=not support 1=support
Reset Enable (66h) should be issued
before Reset Opcode.
0=not support 1=support
0=not support 1=support
00
01
02
03
1b
0b
Deep Power Down Mode
S/W Reset
1b
1b
1001 1001b
(99h)
1b
S/W Reset Opcode
65h:64h
F99Dh
11:04
Program Suspend/Resume
Erase Suspend/Resume
Unused
12
13
1b
14
1b
Wrap-Around Read mode
Wrap-Around Read mode Opcode
Wrap-Around Read data length
0=not support 1=support
15
1b
66h
67h
23:16
C0h
C0h
64h
08h:support 8B wrap-around read
16h:8B&16B
31:24
64h
32h:8B&16B&32B
64h:8B&16B&32B&64B
0=not support 1=support
0=Volatile 1=Nonvolatile
Individual block lock
00
01
1b
0b
Individual block lock bit
(Volatile/Nonvolatile)
Individual block lock Opcode
1110 0001b
(E1h)
09:02
10
Individual block lock Volatile protect 0=protect 1=unprotect
bit default protect status
CB85h
0b
6Bh:68h
Secured OTP
Read Lock
Permanent Lock
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
13
0b
15:14
31:16
[31:00]
11b
FFh
FFh
Unused
FFh
FFh
Unused
6Fh:6Ch
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time,
the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg, read performance
enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: All unused and undefined area data is blank FFh.
© Generalplus Technology Inc.
Proprietary & Confidential
48
Jan 21, 2013
Version: 1.0
GPR25L25605F
10. RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at the following states:
- Standby mode
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.
- 3-byte address mode
If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data could be lost. During
the resetting cycle, the SO data becomes high impedance and the current will be reduced to minimum.
Figure 82. RESET Timing
Table 12. Reset Timing
Symbol Alt.
tRLRH
Parameter
Min.
10
Typ.
Max.
Unit
us
Reset Pulse Width
Reset Setup Time
Reset Hold Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tRS
15
ns
tRH
15
ns
tRHSL
Reset Recovery Time (During instruction decoding) (Note 2)
Reset Recovery Time (For Read operation)
Reset Recovery Time (For Program operation)
Reset Recovery Time (For SE/4KB Sector Erase operation)
Reset Recovery Time (For BE64K/32KB Block Erase
operation)
30
us
30
us
300
12
us
ms
ms
25
Reset Recovery Time (For Chip Erase operation)
Reset Recovery Time (for WRSR operation)
100
-
-
-
-
ms
ms
tW (Note 1)
© Generalplus Technology Inc.
Proprietary & Confidential
49
Jan 21, 2013
Version: 1.0
GPR25L25605F
11. POWER-ON STATE
The device is at below states when power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state.
When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any
command.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write,
erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might
occur during the stage while a write, program, erase cycle is in progress.
© Generalplus Technology Inc.
Proprietary & Confidential
50
Jan 21, 2013
Version: 1.0
GPR25L25605F
12. ELECTRICAL SPECIFICATIONS
12.1. Table 13. Absolute Maximum Ratings
Rating
Ambient Operating Temperature
Storage Temperature
Value
Industrial grade
-40°C to 85°C
-65°C to 150°C
-0.5V to Vcc+0.5V
-0.5V to Vcc+0.5V
-0.5V to Vcc+0.5V
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and
functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+2.0V or -2.0V for period up to 20ns.
4. All input and output pins may overshoot to VCC+0.2V
Figure 83. Maximum Negative Overshoot Waveform
Figure 84. Maximum Positive Overshoot Waveform
12.2. Table14 Capacitance TA = 25°C, f = 1.0 MHz
Symbol
CIN
Parameter
Min.
Typ.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
Output Capacitance
-
-
-
-
6
8
COUT
pF
VOUT = 0V
Figure 85. Input test waveforms and measurement level
© Generalplus Technology Inc.
Proprietary & Confidential
51
Jan 21, 2013
Version: 1.0
GPR25L25605F
Figure 86. Output loading
© Generalplus Technology Inc.
Proprietary & Confidential
52
Jan 21, 2013
Version: 1.0
GPR25L25605F
12.3. Table 15. DC CHARACTERISTICS
(Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)
Symbol
Parameter
Notes
Min.
Typ.
Max.
Units Test Conditions
VCC = VCC Max,
uA
ILI
Input Load Current
1
-
-
±2
VIN = VCC or GND
VCC = VCC Max,
uA
ILO
Output Leakage Current
VCC Standby Current
1
1
-
-
-
-
-
±2
100
20
VOUT = VCC or GND
VIN = VCC or GND,
ISB1
ISB2
30
5
uA
CS# = VCC
VIN = VCC or GND,
Deep Power-down Current
uA
CS# = VCC
f=104MHz, (4 x I/O read)
20
15
mA
mA
SCLK=0.1VCC/0.9VCC,
SO=Open
ICC1
VCC Read
1
-
-
f=84MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
Program in Progress,
CS# = VCC
ICC2
ICC3
ICC4
ICC5
VCC Program Current (PP)
1
-
-
-
-
-
20
-
25
20
25
25
mA
mA
mA
mA
VCC
Write
Status
Register
Program status register
in progress, CS#=VCC
(WRSR) Current
VCC Sector/Block (32K, 64K)
Erase Current (SE/BE/BE32K)
Erase
in
Progress,
1
1
20
20
CS#=VCC
Erase
in
Progress,
VCC Chip Erase Current (CE)
CS#=VCC
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-
-
-
-
-0.5
0.7VCC
-
-
-
-
-
0.8
VCC+0.4
0.2
V
V
V
V
VIH
VOL
IOL = 100uA
IOH = -100uA
VOH
VCC-0.2
Notes:
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
© Generalplus Technology Inc.
Proprietary & Confidential
53
Jan 21, 2013
Version: 1.0
GPR25L25605F
12.4. Table 16. AC CHARACTERISTICS
(Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)
Symbol
fSCLK
Alt.
fC
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for all commands (except Read)
Clock Frequency for READ instructions
Clock Frequency for 2READ instructions
Clock Frequency for 4READ instructions
D.C.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
133
MHz
MHz
MHz
MHz
ns
fRSCLK
fTSCLK
fR
-
-
50
fT
84(7)
fQ
-
84(7)
tCH(1)
tCL(1)
tCLH Clock High Time
Others (fSCLK)
3.3
7
-
-
Normal Read (fRSCLK)
Others (fSCLK)
ns
tCLL
Clock Low Time
3.3
7
-
ns
Normal Read (fRSCLK)
-
ns
tCLCH(2)
tCHCL(2)
tSLCH
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
0.1
0.1
5
-
V/ns
V/ns
ns
-
tCSS CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
tDSU Data In Setup Time
-
tCHSL
7
-
ns
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL(3)
2
-
ns
tDH
Data In Hold Time
4
-
ns
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
5
-
ns
5
-
ns
tCSH CS# Deselect Time
Read
7
-
ns
Write/Erase/Program
30
-
-
ns
tSHQZ(2)
tDIS
tV
Output Disable Time
Clock Low to Output Valid
Loading: 30pF/15pF
8
8
6
-
ns
tCLQV
Loading: 30pF
Loading: 15pF
-
ns
-
ns
tCLQX
tWHSL
tSHWL
tDP(2)
tRES1(2)
tRES2(2)
tW
tHO
Output Hold Time
1
ns
Write Protect Setup Time
Write Protect Hold Time
20
100
-
-
ns
-
ns
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature Read
CS# High to Standby Mode with Electronic Signature Read
Write Status/Configuration Register Cycle Time
Write Extended Address Register
10
30
30
40
-
us
-
us
-
us
-
ms
ns
tWREAW
tBP
-
40
12
Byte-Program
-
30
3
3
us
tPP
Page Program Cycle Time
-
0.6
ms
ms
tPP(5)
Page Program Cycle Time (n bytes)
-
0.008+
(nx0.004) (6)
43
tSE
tBE32
tBE
Sector Erase Cycle Time
-
-
-
-
200
1000
2000
300
ms
ms
ms
s
Block Erase (32KB) Cycle Time
Block Erase (64KB) Cycle Time
Chip Erase Cycle Time
190
340
tCE
120
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25°C. Not 100% tested.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Test condition is shown as Figure 85 and Figure 86.
5. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to program the whole 256 bytes or only a few bytes
between 1~256 bytes.
6. “n”=how many bytes to program. In the formula, while n=1, byte program time=12us.
7. By default dummy cycle value. Please refer to the "Table 1. Read performance Comparison".
© Generalplus Technology Inc.
Proprietary & Confidential
54
Jan 21, 2013
Version: 1.0
GPR25L25605F
13. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in Figure 87 and Figure 88 are for the supply voltages and the control signals at device power-up and power-down. If
the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can
be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 87. AC Timing at Device Power-Up
Symbol
Parameter
Notes
Min.
Max.
Unit
tVR
VCC Rise Time
1
20
500000
us/V
Notes:
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "Table 16. AC CHARACTERISTICS".
Figure 88. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
© Generalplus Technology Inc.
Proprietary & Confidential
55
Jan 21, 2013
Version: 1.0
GPR25L25605F
Figure 85. Power-up Timing
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 17. Power-Up Timing and VWI Threshold
Symbol
tVSL(1)
VWI(1)
Parameter
Min.
800
2.3
Max.
-
Unit
us
VCC(min) to CS# low (VCC Rise Time)
Command Inhibit Voltage
2.5
V
Note: 1. These parameters are characterized only.
13.1. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all
Status Register bits are 0).
© Generalplus Technology Inc.
Proprietary & Confidential
56
Jan 21, 2013
Version: 1.0
GPR25L25605F
14. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Min.
Typ. (1)
-
Max. (2)
Unit
ms
ms
s
Write Status Register Cycle Time
Sector Erase Time (4KB)
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
-
-
-
-
-
-
-
-
40
200
1
43
0.19
0.34
120
2
s
300
30
3
s
Byte Program Time (via page program command)
Page Program Time
12
us
0.6
ms
cycles
Erase/Program Cycle
100,000
-
Notes:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and all zero pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
4. The maximum chip programming time is evaluated under the worst conditions of 0°C, VCC=3.3V, and 100K cycle with 90% confidence level.
15. DATA RETENTION
Parameter
Condition
Min.
Max.
Unit
Data retention
55˚C
20
-
years
16. LATCH-UP CHARACTERISTICS
Parameter
Min.
-1.0V
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
2 VCC max
VCC + 1.0V
+100mA
-1.0V
Current
-100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
© Generalplus Technology Inc.
Proprietary & Confidential
57
Jan 21, 2013
Version: 1.0
GPR25L25605F
17. ORDERING INFORMATION
Product Number
Package Type
Package Form - 16-SOP RoHS (Green Package)
GPR25L25605F – HS12x
Note1: Code number is assigned for customer.
Note2: Package form number (x = 1 - 9, serial number).
© Generalplus Technology Inc.
Proprietary & Confidential
58
Jan 21, 2013
Version: 1.0
GPR25L25605F
18. PACKAGE INFORMATION
18.1. Title: Package Outline for SOP 16L 300MIL
18.1.1. Dimensions (Inch dimensions are derived from the original mm dimensions)
Symbol
Θ
A
A1
A2
b
C
D
E
E1
e
L
L1
S
Unit
Min.
Nom.
Max.
Min.
-
0.10
0.20
2.34
2.39
0.36
0.41
0.20
0.25
10.10
10.30
10.50
0.397
0.405
0.413
10.10
10.30
10.50
0.397
0.405
0.413
7.42
7.52
-
0.40
0.84
1.31
1.44
0.51
0.64
0
5
8
0
5
8
mm
-
1.27
2.65
0.30
2.44
0.51
0.30
7.60
-
1.27
1.57
0.77
-
-
0.004
0.008
0.012
0.092
0.094
0.096
0.014
0.016
0.020
0.008
0.010
0.012
0.292
0.296
0.299
-
0.050
-
0.016
0.033
0.050
0.052
0.057
0.062
0.020
0.025
0.030
inch
Nom.
Max.
0.104
REFERENCE
DWG. NO.
REVISION
ISSUE DATE
JEDEC
EIAJ
6110-1402
10
MS-013
-
-
© Generalplus Technology Inc.
Proprietary & Confidential
59
Jan 21, 2013
Version: 1.0
GPR25L25605F
19. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
60
Jan 21, 2013
Version: 1.0
GPR25L25605F
20. REVISION HISTORY
Date
Revision#
Description
Page
Jan 21, 2013
1.0
Original
61
© Generalplus Technology Inc.
Proprietary & Confidential
61
Jan 21, 2013
Version: 1.0
相关型号：
GPR25L25606F-QS12X
3V, 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY
GENERALPLUS
©2020 ICPDF网 联系我们和版权申明