RFD10P03LSM9A [HARRIS]
10A, 30V, 0.200 ohm, Logic Level P-Channel Power MOSFET; 10A ， 30V ， 0.200欧姆，逻辑电平P沟道功率MOSFET
| 型号： | RFD10P03LSM9A |
| 厂家： | 
HARRIS CORPORATION |
| 描述： | 10A, 30V, 0.200 ohm, Logic Level P-Channel Power MOSFET |
| 文件： | 总12页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RFD10P03L, RFD10P03LSM,
RFP10P03L
S E M I C O N D U C T O R
10A, 30V, 0.200Ω, Logic Level
P-Channel Power MOSFET
May 1997
Features
Description
• 10A, 30V
• r = 0.200Ω
These products are P-Channel power MOSFETs manufac-
tured using the MegaFET process. This process, which uses
feature sizes approaching those of LSI circuits, gives opti-
mum utilization of silicon, resulting in outstanding perfor-
mance. They were designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. These transistors can be operated directly
from integrated circuits.
DS(ON)
• Temperature Compensating PSPICE Model
• PSPICE Thermal Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
o
• 175 C Operating Temperature
Symbol
Ordering Information
D
PART NUMBER
RFD10P03L
PACKAGE
TO-251AA
BRAND
10P03L
10P03L
F10P03L
G
RFD10P03LSM
RFP10P03L
TO-252AA
TO-220AB
S
NOTE: When ordering, use the entire part number. Add the suffix, 9A,
to obtain the TO-252AA variant in tape and reel, i.e. RFD10P03LSM9A..
Formerly developmental type TA49205.
Packaging
JEDEC TO-220AB
JEDEC TO-251AA
SOURCE
DRAIN
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
DRAIN (FLANGE)
GATE
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures.
File Number 3515.1
Copyright © Harris Corporation 1997
1
RFD10P03L, RFD10P03LSM, RFP10P03L
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
C
RFD10P03L, RFD10P03LSM,
RFP10P03L
UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
-30
-30
±10
V
V
V
DSS
Drain to Gate Voltage (R
GS
= 20KΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain Current
GS
RMS Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
10
A
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
See Figure 5
DM
Single Pulse Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
AS
Refer to UIS Curve
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
Derate Above 25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
0.43
W
W/ C
D
o
o
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
-55 to 175
300
C
J
STG
o
Maximum Lead Temperature for Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
(0.063in (1.6mm) from case for 10s)
C
L
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
C
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
SYMBOL
TEST CONDITIONS
= 250µA, V = 0V
MIN
TYP
MAX
UNITS
V
BV
I
-30
-
-
-
-
-
-
-
-2
DSS
D
GS
V
V
V
V
V
= V , I = 250µA
-1
-
V
GS(TH)
GS
DS
GS
GS
DS
D
o
Zero Gate Voltage Drain Current
I
= -30V,
T
T
= 25 C
-1
µA
µA
nA
Ω
DSS
C
o
= 0V
= 150 C
-
-50
±100
0.200
0.220
100
-
C
Gate to Source Leakage Current
I
= ±10V
-
GSS
Drain to Source On Resistance
(Note 1)
r
I
I
= 10A, V
= 10A, V
= -5V
= -4.5V
10A
-
DS(ON)
D
GS
GS
Ω
D
Turn-On Time
t
V
= 15V, I
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
50
35
20
-
ns
ON
DD
R = 1.5Ω, R
= 5Ω,
L
GS
Turn-On Delay Time
Rise Time
t
ns
d(ON)
V
= -5V
GS
t
-
ns
r
Turn-Off Delay Time
Fall Time
t
-
ns
d(OFF)
t
-
ns
f
Turn-Off Time
t
80
30
16
1.5
-
ns
OFF
Total Gate Charge
Q
V
V
V
V
= 0 to -10V
= 0 to -5V
= 0 to -1V
V
DD
= -24V,
10A,
25
13
1.2
1035
340
35
-
nC
nC
nC
pF
pF
pF
g(TOT)
GS
GS
GS
DS
I
D
Gate Charge at -5V
Threshold Gate Charge
Input Capacitance
Q
g(-5)
R
= 2.4Ω
L
Q
g(TH)
C
= -25V, V
= 0V
GS
ISS
OSS
RSS
f = 1MHz
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
C
C
-
-
o
R
2.30
100
80
C/W
θJC
θJA
o
R
RFD10P03L, RFD10P03LSM
RFP10P03L
-
C/W
o
C/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Forward Voltage
Reverse Recovery Time
NOTE:
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
-1.5
75
UNITS
V
V
I
I
= -10A
-
-
-
-
SD
SD
t
= -10A, dI /dt = -100A/µs
ns
rr
SD
SD
1. Pulse Test: Pulse width ≤ 300µs, Duty Cycle ≤ 2%.
2
RFD10P03L, RFD10P03LSM, RFP10P03L
Typical Performance Curves Unless Otherwise Specified
1.2
1.0
0.8
0.6
0.4
-12
-10
-8
-6
-4
-2
0
0.2
0.0
150
125
175
25
50
75
100
0
25
50
75
100
125
150
175
o
o
T
, CASE TEMPERATURE ( C)
T , CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2.0
1.0
0.5
0.2
P
0.1
0.1
DM
0.05
0.02
0.01
t
1
t
2
SINGLE PULSE
NOTES: DUTY FACTOR: D = t /t
1
2
PEAK T = P
DM
x Z
x R
+ T
J
θJC
θJC C
0.01
10
-5
-4
10
-3
10
-2
-1
10
0
1
10
t, RECTANGULAR PULSE DURATION (s)
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-100
-100
-10
-1
o
T
= 25 C
o
C
T
T
= MAX RATED
= 25 C
J
C
o
FOR TEMPERATURES ABOVE 25 C
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
100µs
V
= -10V
175 – T
GS
C
I = I
-----------------------
25
150
V
= -5V
GS
1ms
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
-10
-5
100ms
DC
DS(ON)
V
MAX = -30V
DSS
-10
-100
0
1
-5
-4
10
-3
10
-2
-1
-1
10
10
10
10
10
V
, DRAIN TO SOURCE VOLTAGE (V)
t, PULSE WIDTH (s)
DS
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
3
RFD10P03L, RFD10P03LSM, RFP10P03L
Typical Performance Curves Unless Otherwise Specified (Continued)
-50
o
-25
STARTING T = 25 C
J
PULSE DURATION = 250µs,
o
T
= 25 C
C
V
= -5V
GS
-20
-15
-10
-5
-10
V
= -10V
GS
V
= -4V
GS
o
STARTING T = 150 C
J
V
=-3.5V
GS
If R = 0
t
= (L) (I )/(1.3 RATED BV
- V
)
AV
IF R ≠ 0
AS DSS
DD
V
= -3V
GS
t
= (L/R) ln [(I *R)/(1.3 RATED BV
AS
- V ) + 1]
DD
AV
DSS
-1
0.01
0
0.1
AV
1
10
-2.0
, DRAIN TO SOURCE VOLTAGE (V)
0
-1.0
-3.0
-4.0
-5.0
t
, TIME IN AVALANCHE (ms)
V
DS
NOTE: Refer to Application Notes AN9321 and AN9322.
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
400
300
200
-25
o
-55 C
PULSE TEST
PULSE DURATION = 250µs
o
T = 25 C
C
o
I
I
= -20A
= -10A
D
25 C
DUTY CYCLE = 0.5% MAX
-20
D
V
= -15V
o
DD
175 C
I
I
= -5A
D
-15
-10
-5
= -2.5A
D
100
0
0
0
-1.5
-3.0
-4.5
-6.0
-2.0
-4.0
-6.0
-8.0
-10.0
V
, GATE TO SOURCE VOLTAGE (V)
V , GATE TO SOURCE VOLTAGE (V)
GS
GS
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.2
2.0
1.5
V
= -5V, I = -10.0A
D
I
=- 250uA
GS
D
1.1
1.0
1.0
0.5
0.0
0.9
0.8
160
200
40
80
120
-80
-40
0
-80
160
200
-40
0
40
80
120
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
4
RFD10P03L, RFD10P03LSM, RFP10P03L
Typical Performance Curves Unless Otherwise Specified (Continued)
150
125
100
75
1.2
V
= -15V, I = -10A, R = 1.50Ω
D L
V
= V , I = -250µA
DS D
DD
GS
t
1.0
0.8
r
t
d(OFF)
t
f
50
0.6
0.4
t
d(ON)
25
0
-80
-40
0
40
80
120
o
160
200
0
10
R , GATE TO SOURCE RESISTANCE (Ω)
GS
20
30
40
50
T , JUNCTION TEMPERATURE ( C)
J
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 13. SWITCHING TIME vs GATE RESISTANCE
1200
-30
-22.5
-15
-5.00
-3.75
-2.50
V
= 0V, f = 1MHz
GS
V
= BV
DSS
V
=BV
DSS
DD
DD
1000
C
ISS
800
600
400
R
= 3.0Ω
L
I
= -0.25mA
G(REF)
0.75 BV
0.75 BV
0.50 BV
0.25 BV
DSS
DSS
0.50 BV
0.25 BV
DSS
DSS
DSS
-1.25
0.00
-7.5
0
DSS
C
OSS
200
0
V
= -5V
GS
C
RSS
I
I
I
I
G(REF)
G(REF)
G(ACT)
0
-5
-10
-15
-20
-25
t, TIME ( µs)
20
80
V
, DRAIN TO SOURCE VOLTAGE (V)
G(ACT)
DS
NOTE: Refer to Application Notes AN7254 and AN7260.
FIGURE 15. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
5
RFD10P03L, RFD10P03LSM, RFP10P03L
Test Circuits and Waveforms
V
DS
t
AV
L
0
VARY t TO OBTAIN
P
-
R
REQUIRED PEAK I
G
AS
V
DD
+
DUT
0V
V
t
P
V
GS
DD
I
AS
I
AS
V
DS
0.01Ω
t
P
BV
DSS
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
t
d(OFF)
d(ON)
t
t
f
r
0
R
L
10%
10%
DUT
-
V
DS
90%
V
90%
DD
R
G
+
V
V
0
GS
GS
10%
50%
50%
90%
PULSE WIDTH
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
V
DS
V
DS
Q
R
g(TH)
L
0
V
= -1V
-V
GS
V
GS
V
= -5V
-
GS
GS
V
DD
Q
+
g(-5)
V
= -10V
GS
DUT
V
DD
I
G(REF)
Q
g(TOT)
0
I
g(REF)
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
6
RFD10P03L, RFD10P03LSM, RFP10P03L
PSpice Electrical Model
.SUBCKT RFD10P03L 2 1 3
REV 22 Aug 96
CA 12 8 1.29e-9
CB 15 14 9.90e-10
CIN 6 8 1.01e-9
LDRAIN
ESG
5
DRAIN
2
-
+
8
6
10
RLDRAIN
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DPLCAP 10 6 DPLCAPMOD
RSLC1
51
+
+
RSLC2
17
18
5
EBREAK
ESLC
51
EBREAK 5 11 17 18 -36.49
EDS 14 8 5 8 1
-
-
50
EGS 13 8 6 8 1
ESG 5 10 8 6 1
DPLCAP
RDRAIN
DBODY
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
EVTHRES
+
16
21
-
19
8
MWEAK
LGATE
EVTEMP
11
RGATE
GATE
1
IT 8 17 1
6
-
+
18
22
MMED
9
20
LDRAIN 2 5 1e-9
LGATE 1 9 3.40e-9
LSOURCE 3 7 3.22e-9
DBREAK
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
MMED 16 6 8 8 MmedMOD
MSTRO 16 6 8 8 MstroMOD
MWEAK 16 21 8 8 MweakMOD
S1A
S2A
RBREAK
12
15
13
14
13
17
18
8
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 68.25e-3
RGATE 9 20 2.54
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RSourceMOD 25.00e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*33),5.0))}
.MODEL DBODYMOD D (IS=9.15e-13 RS=3.25e-2 IKF=0.05 N=0.97 TRS1=4.11e-5 TRS2=2.03e-6 CJO=1.13e-9 M=0.40 TT=3.72e-8)
.MODEL DBREAKMOD D ( RS=2.62e-1 TRS1=1.74e-3 TRS2=-3.81e-6)
.MODEL DPLCAPMOD D (CJO=1.46e-10 IS=1e-30 N=10 M=0.50)
.MODEL MSTRONGMOD PMOS (VTO=-1.95 KP=11.60 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MMEDMOD PMOS (VTO=-1.65 KP=1.00 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.54)
.MODEL MWEAKMOD PMOS (VTO=-1.43 KP=0.09 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=25.4 RS=0.1)
.MODEL RBREAKMOD RES (TC1=9.17e-4 TC2=-2.74e-7)
.MODEL RDRAINMOD RES (TC1=6.35e-3 TC2=1.98e-5)
.MODEL RSOURCEMOD RES (TC1=0 TC2=0)
.MODEL RSCLMOD RES (TC1=2e-3 TC2=0)
.MODEL RVTHRESMOD RES (TC1=1.23e-3 TC2=1.97e-6)
.MODEL RVTEMPMOD RES (TC1=-1.18e-3 TC2=1.44e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.80 VOFF=1.80)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.80 VOFF=4.80)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.40 VOFF=-3.40)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.40 VOFF=-0.40)
ENDS
For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFet Featuring Global Temperature Options; authored by
William J. Hepp and C. Frank Wheatley.
7
RFD10P03L, RFD10P03LSM, RFP10P03L
PSpice Thermal Model
REV 29 Aug 96
RFP10P03L
JUNCTION
7
CTHERM1 7 6 5.00e-7
CTHERM2 6 5 5.35e-4
CTHERM3 5 4 5.50e-4
CTHERM4 4 3 1.75e-3
CTHERM5 3 2 1.25e-2
CTHERM6 2 1 0.45
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
RTHERM1 7 6 1.00e-2
RTHERM2 6 5 2.05e-2
RTHERM3 5 4 5.39e-2
RTHERM4 4 3 5.45e-1
RTHERM5 3 2 1.01
6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM6 2 1 0.50
5
RFD10P03L, RFD10P03LSM
CTHERM1 7 6 5.00e-7
CTHERM2 6 5 5.35e-4
CTHERM3 5 4 5.50e-4
CTHERM4 4 3 1.75e-3
CTHERM5 3 2 1.25e-2
CTHERM6 2 1 0.11
4
3
2
RTHERM1 7 6 1.00e-2
RTHERM2 6 5 2.05e-2
RTHERM3 5 4 5.39e-2
RTHERM4 4 3 5.45e-1
RTHERM5 3 2 1.01
RTHERM6 2 1 0.50
1
CASE
8
RFD10P03L, RFD10P03LSM, RFP10P03L
TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
A
INCHES
MIN
MILLIMETERS
E
ØP
SYMBOL
MAX
0.180
0.052
0.034
0.055
0.019
0.610
0.160
0.410
0.030
MIN
4.32
1.22
0.77
1.15
0.36
14.99
-
MAX
4.57
NOTES
A
1
A
0.170
0.048
0.030
0.045
0.014
0.590
-
-
Q
H
1
A
1.32
-
1
b
0.86
3, 4
TERM. 4
D
b
1.39
2, 3
1
o
45
E
1
c
0.48
2, 3, 4
D
1
D
15.49
4.06
-
-
L
1
D
1
b1
b
E
0.395
-
10.04
-
10.41
0.76
-
L
E
-
c
1
e
0.100 TYP
0.200 BSC
0.235
2.54 TYP
5.08 BSC
5
5
-
o
60
e
1
2
e
3
1
J
1
H
0.255
0.110
0.550
0.150
0.153
0.112
5.97
6.47
2.79
13.97
3.81
3.88
2.84
1
1
e1
J
0.100
0.530
0.130
0.149
0.102
2.54
13.47
3.31
6
-
L
LEAD NO. 1
LEAD NO. 2
LEAD NO. 3
TERM. 4
- GATE
L
2
-
1
-
-
-
DRAIN
ØP
Q
3.79
SOURCE
DRAIN
2.60
-
NOTES:
1. These dimensions are within allowable dimensions of Rev. J of
JEDEC TO-220AB outline dated 3-24-87.
2. Lead dimension and finish uncontrolled in L .
1
3. Lead dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder coating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bot-
tom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bot-
tom of dimension D.
7. Controlling dimension: Inch.
8. Revision 1 dated 1-93.
9
RFD10P03L, RFD10P03LSM, RFP10P03L
TO-251AA
3 LEAD JEDEC TO-251AA PLASTIC PACKAGE
E
A
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.094
0.022
0.032
0.040
0.215
0.022
0.290
0.265
MIN
2.19
0.46
0.72
0.84
5.21
0.46
6.86
6.35
MAX
2.38
0.55
0.81
1.01
5.46
0.55
7.36
6.73
NOTES
b2
A
H
1
1
A
0.086
0.018
0.028
0.033
0.205
0.018
0.270
0.250
-
TERM. 4
A
1
3, 4
SEATING
PLANE
D
b
3, 4
b
b
3
1
3, 4
2
c
3, 4
b1
D
E
e
-
-
L
1
L
c
b
0.090 TYP
0.180 BSC
2.28 TYP
4.57 BSC
5
5
-
e
1
1
2
3
H
0.035
0.045
0.045
0.375
0.090
0.89
1.14
1.14
9.52
2.28
1
J
e
1
J
0.040
0.355
0.075
1.02
9.02
1.91
6
-
1
e1
L
L
2
1
LEAD NO. 1
LEAD NO. 2
LEAD NO. 3
TERM. 4
-
-
-
-
GATE
NOTES:
DRAIN
SOURCE
DRAIN
1. These dimensions are within allowable dimensions of Rev. C of
JEDEC TO-251AA outline dated 9-88.
2. Solder finish uncontrolled in this area.
3. Dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder plating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bot-
tom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bot-
tom of dimension D.
7. Controlling dimension: Inch.
8. Revision 2 dated 10-95.
10
RFD10P03L, RFD10P03LSM, RFP10P03L
TO-252AA
SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE
INCHES
MIN
MILLIMETERS
A
E
A
SYMBOL
MAX
0.094
0.022
0.032
0.040
0.215
-
MIN
2.19
0.46
0.72
0.84
5.21
4.83
0.46
6.86
6.35
MAX
2.38
0.55
0.81
1.01
5.46
-
NOTES
H
b2
1
1
A
0.086
0.018
0.028
0.033
0.205
0.190
0.018
0.270
0.250
-
SEATING
PLANE
A
4, 5
1
b
4, 5
D
b
b
b
4
1
2
3
L
2
4, 5
2
L
1
3
c
0.022
0.290
0.265
0.55
7.36
6.73
4, 5
b1
b
D
E
e
-
-
L
1
e
c
e1
J
1
0.090 TYP
0.180 BSC
2.28 TYP
4.57 BSC
7
7
-
0.265
(6.7)
e
1
TERM. 4
H
0.035
0.045
0.045
0.115
-
0.89
1.14
1.14
2.92
-
1
1
J
0.040
0.100
0.020
0.025
0.170
1.02
2.54
0.51
0.64
4.32
-
L
-
L
3
0.265 (6.7)
b3
L
L
L
4, 6
3
2
1
2
3
0.040
-
1.01
-
0.070 (1.8)
NOTES:
0.118 (3.0)
1. These dimensions are within allowable dimensions of Rev. B of
JEDEC TO-252AA outline dated 9-88.
BACK VIEW
2. L and b dimensions establish a minimum mounting surface for
3
3
0.063 (1.6)
0.090 (2.3)
0.063 (1.6)
0.090 (2.3)
terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
5. Add typically 0.002 inches (0.05mm) for solder plating.
6. L is the terminal length for soldering.
1
7. Position of lead to be measured 0.090 inches (2.28mm) from bottom
of dimension D.
LEAD NO. 1
LEAD NO. 3
TERM. 4
-
-
-
GATE
SOURCE
DRAIN
8. Controlling dimension: Inch.
9. Revision 6 dated 10-96.
11
RFD10P03L, RFD10P03LSM, RFP10P03L
TO-252AA
16mm TAPE AND REEL
22.4mm
13mm
4.0mm
1.5mm
DIA. HOLE
2.0mm
1.75mm
C
L
16mm
50mm
330mm
8.0mm
16.4mm
USER DIRECTION OF FEED
GENERAL INFORMATION
1. USE "9A" SUFFIX ON PART NUMBER.
2. 2500 PIECES PER REEL.
COVER TAPE
3. ORDER IN MULTIPLES OF FULL REELS ONLY.
4. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
Revision 6 dated 10-96
All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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FAX: (407) 729-5321
S E M I C O N D U C T O R
12
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