ICS556G-03IT [ICSI]
QUAD LVDS OSCILLATOR/BUFFER; 四路LVDS振荡器/缓冲器
| 型号： | ICS556G-03IT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | QUAD LVDS OSCILLATOR/BUFFER |
| 文件： | 总8页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS556-03
QUAD LVDS OSCILLATOR/BUFFER
Description
Features
The ICS556-03 is a clock oscillator with quad LVDS
outputs. Using a standard 25 MHz crystal, no additional
external components are required to generate quad
LVDS outputs at 25 MHz.
• Packaged in 16-pin TSSOP
• Requires no external components
• Low Phase Jitter: <1ps from 10 kHz to 10 MHz
• Quad, Differential LVDS outputs
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
• Operating voltage of 2.5 Volt
• Advanced, low-power, sub-micron CMOS process
Block Diagram
VDD
EN1
EN2
EN3
EN4
CLKA
CLKA
CLKB
CLKB
Crystal
Oscillator
25MHz
LVDS
CLKC
CLKC
CLKD
CLKD
GND
MDS 556-03 B
1
Revision 030204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS556-03
Quad LVDS Oscillator/Buffer
Pin Assignment
1
16
15
14
13
12
11
10
9
EN4
EN1
2
3
4
5
6
7
8
VDD
A
EN3
D
A
D
C
B
B
C
GND
EN2
X2
X1
16-Pin (150 mil) SOIC
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
EN1
Input
Enable pin for Outputs A and A. EN1 high enables A, A outputs.
EN1 low tri states A, A outputs. No Pull-Up resistor.
2
3
4
5
6
7
VDD
A
Power Power supply. Connect to 2.5 V.
Output Differential clock output.
A
Output Inverting differential clock output.
Output Inverting differential clock output.
Output Differential clock output.
B
B
EN2
Input
Enable pin for Outputs B and B. EN2 high enables B, B outputs.
EN2 low tri states B, B outputs. No Pull-Up resistor.
8
X2
X1
GND
C
Input
Input
Crystal connection.
Crystal input.
9
10
11
12
13
Power Connect to ground.
Output Differential clock output.
Output Inverting differential clock output.
Output Inverting differential clock output.
C
D
MDS 556-03 B
2
Revision 030204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS556-03
Quad LVDS Oscillator/Buffer
Pin
Number
Pin
Name
Pin
Type
Pin Description
14
15
D
Output Differential clock output.
EN3
Input
Enable pin for Outputs C and C. EN4 high enables C, C outputs.
EN3 low tri states C, C outputs.No Pull-Up resistor.
16
EN4
Input
Enable pin for Outputs D and D. EN4 high enables D, D outputs.
EN4 low tri states D, D outputs.No Pull-Up resistor.
Quartz Crystal
External Component Selection
The ICS556-03, a quad 25 MHz LVDS Clock utilizes an
external crystal to generate 4 pairs of low phase noise
outputs. The crystal should be a fundamental mode,
parallel resonant. Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these
capacitors is given by the following equation
The ICS556-03 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
A decoupling capacitor of 0.01µF should be connected
between VDD and GND on pins 2 and 10 as close to
the ICS556-03 possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Crystal Caps (pf)= (C -12)x2
L
In the equation, CL is the crystal Load capacitance. So
for the crystal with 16pF load capacitance, two 8
pF[(16-12)x2] capacitors should be used.
LVDS Driver Termination
A general LVDS interface is shown in Figure 2. In a 100
ohm differential transmission line environment, LVDS
drivers require a matched load termination of 100
across near the receiver input. For a multiple LVDS
outputs buffer, if only partial outputs are used, it is
recommended to terminate the un-used outputs.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS556-03. There should be no via’s
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal.
2.5V
2.5V
LVDS_Driver
+
R1
100 ohm
-
100 Ohm Differential Transmission Line
Figure 2. Typical LVDS Driver
Termination
MDS 556-03 B
3
Revision 030204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS556-03
Quad LVDS Oscillator/Buffer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS556-03. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70°C
Ambient Operating Temperature
Storage Temperature
-65 to +150°C
260°C
Soldering Temperature
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Reference crystal parameters
0
+2.375
+2.625
V
Refer to page 3
MDS 556-03 B
4
Revision 030204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS556-03
Quad LVDS Oscillator/Buffer
DC Electrical Characteristics
VDD=2.5 V 5% , Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Output High Voltage
Output Low Voltage
Symbol
Conditions
Min.
2.375
1.375
Typ.
Max.
Units
VDD
2.625
V
V
V
V
V
Note 1
OH
V
Note 1
1.125
0.5
OL
Input High Voltage (EN1,
EN2,EN3 & EN4)
V
2.0
IH
Input High Voltage (EN1,
EN2,EN3 & EN4)
V
V
IL
Operating Supply Current
IDD
OE1:4:1
OE1:4:0
17
4
mA
mA
mA
Short Circuit Current
I
50
OS
Note 1: Outputs terminated with 50Ω to VDD/2
AC Electrical Characteristics
VDD = 2.5 V 5%, Ambient Temperature 0 to +70° C, CL=5 pF, unless stated otherwise
Parameter
Conditions
Min. Typ. Max. Units
Input Frequency
25
25
350
0
MHz
MHz
mV
mV
V
Output Frequency
Differential Output Voltages (V
)
250
-40
450
40
OD
∆ V
V
Magnitude Change
Magnitude Change
OS
OD
OD
Offset Voltage (V
)
1.125 1.25 1.375
OS
∆ V
V
3
25
mV
mA
mA
ns
OS
Differential Output Short Circuit Current (I
)
-3.5
-3.5
0.8
0.8
50
OSD
Output Short Circuit Current (I
Output Rise Time
)
OS
20% to 80%, no load
20% to 80%, no load
Measured at 1.25V,
1.2
1.2
55
Output Fall Time
ns
Output Clock Duty Cycle
Output Short Circuit Current
45
%
50
mA
ps
Channel Output to output Skew
Part to Part Skew
20
100
1.5
ns
Maximum Output Jitter (p-p)
Phase Jitter (RMS)
40
2
ps
Phase Noise integrated
from 10 kHz to 10 MHz
1.0
ps
MDS 556-03 B
5
Revision 030204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS556-03
Quad LVDS Oscillator/Buffer
Parameter Measurement Information
VDD
VDD = 2.5V±5%
SCOPE
nCLK
Z = 50
Qx
Cross Points
VOS
50
VOD
CLK
LVDS
Z = 50
nQx
50
GND
DIFFERENTIAL INPUT LEVEL
2.5V OUTPUT LOAD AC TEST CIRCUIT
nCLK
80%
VOD
80%
CLK
20%
20%
Pulse Width
Clock
Outputs
tOR
tOF
tPERIOD
tPW & tPERIOD
OUTPUT RISE/FALL TIME
nCLK
CLK
VOH
VOL
t( )
tjit( ) = t( ) - t( )mean = Phase Jitter
PHASE JITTER
MDS 556-03 B
6
Revision 030204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS556-03
Quad LVDS Oscillator/Buffer
VDD
VDD
out
out
50
50
DC Input
LVDS
DC Input
LVDS
100
VOD/ VOD
VOS/ VOS
out
out
VOS SETUP
VOD SETUP
MDS 556-03 B
7
Revision 030204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS556-03
Quad LVDS Oscillator/Buffer
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches
Max
16
Symbol
Min
--
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
C
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
D
E
E1
e
L
6.40 BASIC
4.30 4.50
0.65 Basic
1
2
D
0.45
0.75
0.018
0.030
α
0°
8°
0°
8°
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
Ordering Information
Part / Order Number
ICS556G-03I
Marking
ICS556-03I
ICS556-03I
Shipping/Packaging
Tubes
Package
16-pin TSSOP
16-pin TSSOP
Temperature
-40° to +85°C
-40° to +85°C
ICS556G-03IT
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 556-03 B
8
Revision 030204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
相关型号：
©2020 ICPDF网 联系我们和版权申明