ICS83948AYI01 [ICSI]
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER; 低偏移， 1到12差分至LVCMOS扇出缓冲器
| 型号： | ICS83948AYI01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER |
| 文件： | 总11页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83948I-01
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS83948I-01 is a low skew, 1-to-12 Differ-
• 12 LVCMOS outputs
ential-to-LVCMOS Fanout Buffer and a member
of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS83948I-01 has
two selectable clock inputs. The CLK, nCLK pair
• Selectable LVCMOS clock or differential CLK, nCLK inputs
HiPerClockS™
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
can accept most standard differential input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS outputs are designed to drive
50Ω series or parallel terminated transmission lines. The
effective fanout can be increased from 12 to 24 by utilizing
the ability of the outputs to drive two series terminated lines.
• LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 150MHz
• Output skew: 350ps (maximum)
• Part to part skew: 1.5ns (maximum)
• 3.3V core, 3.3V output
The ICS83948I-01 is characterized at 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics make
the ICS83948I-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
• -40°C to 85°C ambient operating temperature
• Pin compatible with the MPC948/948L
BLOCK DIAGRAM
PIN ASSIGNMENT
D
CLK_EN
Q
32 31 30 29 28 27 26 25
LVCMOS_CLK
1
0
GND
Q4
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
CLK_SEL
LVCMOS_CLK
CLK
Q0
CLK
nCLK
VDDO
Q5
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
nCLK
CLK_SEL
ICS83948I-01
GND
Q6
CLK_EN
OE
VDDO
Q7
VDD
GND
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
OE
83948AYI-01
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REV. A SEPTEMBER 23, 2002
1
ICS83948I-01
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
Clock select input. Selects LVCMOS clock input
when HIGH. Selects CLK, nCLK inputs when LOW.
LVCMOS / LVTTL interface levels.
1
CLK_SEL
Input
Pullup
2
3
4
5
6
7
LVCMOS_CLK
CLK
Input
Input
Input
Input
Input
Power
Pullup
Pullup
Clock input. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
nCLK
Pulldown Inverting differential clock input.
CLK_EN
OE
Pullup
Pullup
Clock enable. LVCMOS / LVTTL interface levels.
Output enable. LVCMOS / LVTTL interface levels.
Core supply pin.
VDD
8, 12, 16,
20, 24, 28, 32
GND
Power
Power supply ground.
9, 11, 13, 15,
17, 19, 21, 23
25, 27, 29, 31
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Output
Power
Clock outputs. LVCMOS / LVTTL interface levels.
Output supply pins.
10, 14, 18, 22, 26, 30
VDDO
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
Power Dissipation Capacitance
(per output)
CPD
25
RPULLUP
Input Pullup Resistor
51
51
7
KΩ
KΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
CLK, nCLK
Selected
LVCMOS_CLK
De-selected
Selected
0
1
De-selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK_SEL LVCMOS_CLK
CLK
nCLK
Q0:Q12
LOW
0
0
0
0
0
0
1
1
—
—
—
—
—
—
0
0
1
Differential to Single Ended
Differential to Single Ended
Non Inverting
Non Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
Biased; NOTE 1
HIGH
HIGH
LOW
Biased; NOTE 1
0
1
Single Ended to Single Ended
Single Ended to Single Ended
Inverting
Inverting
Biased; NOTE 1
—
—
—
—
LOW
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
HIGH
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
83948AYI-01
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REV. A SEPTEMBER 23, 2002
2
ICS83948I-01
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, Tstg -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
TABLE 4A. POWER SUPPLY CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Input Supply Voltage
3.0
3.0
3.3
3.3
3.6
3.6
55
V
V
Output Supply Voltage
Quiescent Supply Current
mA
TABLE 4B. DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40° TO 85°
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS/LVTTL
LVCMOS/LVTTL
CLK, nCLK
2
3.6
0.8
1.3
V
V
V
Input Low Voltage
VPP
Peak-to-Peak Input Voltage
0.15
Input Common Mode Voltage;
NOTE 1, 2
VCMR
CLK, nCLK
GND + 0.5
VDD - 0.85
±100
V
IIN
Input Current
µA
V
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -20mA
IOL = 20mA
2.5
0.4
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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REV. A SEPTEMBER 23, 2002
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ICS83948I-01
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40° TO 85°
Symbol Parameter
fMAX Maximum Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
150
MHz
CLK, nCLK;
NOTE 1A
LVCMOS_CLK;
NOTE 1B
2.5
3
6.5
5.5
ns
ns
tPD
Propagation Delay
Measured on
rising edge @VDDO/2
tsk(o)
Output Skew; NOTE 2, 6
350
ps
CLK, nCLK
LVCMOS_CLK
1.5
ns
ns
ns
ns
ps
ns
ns
Part-to-Part Skew;
NOTE 3, 6
Measured on
rising edge @VDDO/2
tsk(pp)
2
tR
Output Rise Time
Output Fall Time
Output Pulse Width
0.8V to 2V
0.8V to 2V
0.2
0.2
1.0
tF
1.0
tPW
tPeriod/2 - 800
tPeriod/2 + 800
tPZL, tPZH Output Disable Time; NOTE 4
11
11
t
PLZ, tPHZ Output Enable Time; NOTE 4
CLK_EN to
1
0
0
1
ns
ns
ns
ns
Clock Enable
CLK
tS
Setup Time;
NOTE 5
CLK_EN to
LVCMOS_CLK
CLK to
CLK_EN
LVCMOS_CLK
to CLK_EN
Clock Enable
Hold Time;
NOTE 5
tH
NOTE 1A: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 1B: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Setup and Hold times are relative to the falling edge of the input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
83948AYI-01
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REV. A SEPTEMBER 23, 2002
4
ICS83948I-01
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
1.65V±0.15V
SCOPE
VDD,
VDDO
Qx
LVCMOS
GND
-1.65V±0.15V
3.3V OUTPUT LOAD TEST CIRCUIT
VDD
nCLK
CLK
VPP
VCMR
Cross Points
GND
DIFFERENTIAL INPUT LEVEL
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REV. A SEPTEMBER 23, 2002
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ICS83948I-01
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
VDDO
2
Qx
Qy
VDDO
2
tsk(o)
OUTPUT SKEW
PART 1
Qx
VDDO
2
VDDO
2
PART 2
Qy
tsk(pp)
PART-TO-PART SKEW
2V
2V
0.8V
0.8V
Clock Outputs
tR
OUTPUT RISE AND FALL TIME
tF
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REV. A SEPTEMBER 23, 2002
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ICS83948I-01
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
VDD
2
LVCMOS_CLK
nCLK
CLK
VDDO
2
Q0:Q11
➤
tPD
➤
PROPAGATION DELAY
VDDO
2
VDDO
2
VDDO
2
Q0:Q11
tPW
tPERIOD
tPW
tPERIOD
odc =
tPW & tPERIOD
83948AYI-01
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REV. A SEPTEMBER 23, 2002
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ICS83948I-01
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 2 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A SEPTEMBER 23, 2002
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ICS83948I-01
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83948I-01 is: 1040
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REV. A SEPTEMBER 23, 2002
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ICS83948I-01
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-026
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REV. A SEPTEMBER 23, 2002
ICS83948I-01
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS83948AYI-01
ICS83948AYI-01T
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS83948AYI01
ICS83948AYI01
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. A SEPTEMBER 23, 2002
11
相关型号：
ICS83948AYLF
Low Skew Clock Driver, 12 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
IDT
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