ICS843-75 [ICSI]
75MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR; 75MHZ ， LVCMOS ， LVPECL双输出振荡器
| 型号： | ICS843-75 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 75MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR |
| 文件： | 总12页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS843-75 is a SAS/SATA Dual Output • One LVCMOS/LVTTL output, 15Ω output impedence
ICS
Oscillator and a member of the HiPerClocksTM
family of high performance devices from ICS.
The ICS843-75 uses a 25MHz crystal to
synthesize 75MHz. The ICS843-75 has
One LVPECL output pair
HiPerClockS™
• Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
excellent jitter performance. The ICS843-75 is packaged
in a small 8-pin TSSOP, making it ideal for use in systems
with limited board space.
• Output frequency: 75MHz
• Random jitter: 3.07ps (maximum)
• Deterministic jitter: 0.13ps (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
LVCMOS
75MHz
Q0
VCC
XTAL_IN
XTAL_OUT
VEE
Q1
1
2
3
4
8
7
6
5
nQ1
VCCO
Q0
25MHz
XTAL_IN
Clock
Synthesizer
LVPECL
75MHz
Q1
ICS843-75
XTAL_OUT
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
nQ1
G Package
TopView
ICS843-75
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
843AG-75
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REV.A JANUARY 9, 2006
1
ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VCC
Power
Input
Positive supply pin.
XTAL_IN,
XTAL_OUT
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
2, 3
4
VEE
Power
Output
Negative supply pin.
Single-ended clock output. LVCMOS/LVTTL interface levels.
15Ω output impedence.
5
Q0
6
VCCO
Power
Output
Output supply pin.
7, 8
nQ1, Q1
Differential LVPECL output pair.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
CIN
Input Capacitance
4
pF
ROUT
Output Impedance Q0
15
Ω
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REV.A JANUARY 9, 2006
2
ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Func-
tional operation of product at these conditions or any condi-
tions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect prod-
uct reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
-0.5V to VCCO + 0.5V
I
Outputs, VO (LVCMOS)
Outputs, IO (LVPECL)
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance, θJA
8 Lead TSSOP
101.7°C/W (0 mps)
112.7°C/W (0 lfpm)
8 Lead SOIC
Storage Temperature, T
-65°C to 150°C
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V 0.3V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.0
Typical
3.3
Maximum Units
VCC
VCCO
IEE
Positive Supply Voltage
3.6
3.6
110
100
12
V
Output Supply Voltage
Power Supply Current
Power Supply Current
Output Supply Current
3.0
3.3
V
mA
mA
mA
ICC
ICCO
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V 0.3V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.6
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VCCO/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V 0.3V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
843AG-75
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REV.A JANUARY 9, 2006
3
ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
Integrated
Circuit
Systems, Inc.
TABLE 4. CRYSTAL CHARACTERISTICS (NOTE 1)
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
25
Mode of Oscillation
Frequency
MHz
ppm
Frequency Tolerance
30
30
Frequency Stability Over Operating
Temperature Range
ppm
Load Capacitance (CL); NOTE 2
Aging for 10 Years
18
15
pF
ppm
mW
Drive Level
1
NOTE 1: Using an HC49/US SMD package, the parameters shown above target 100ppm accuracy.
NOTE 2: See Crystal Input Interface in the Application Information Section.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V 0.3V, TA = 0°C TO 70°C
Symbol Parameter
fOUT Output Frequency
tDJ
Test Conditions
Minimum Typical Maximum Units
75
MHz
ps
Deterministic Jitter; NOTE 1
Random Jitter; NOTE 1
0.13
3.07
tRJ
ps
RMS of Total Distribution (σ);
NOTE 2
tRMS
3.08
ps
tp-p
Peak-to-Peak Jitter; NOTE 1
Oscillation Start Up Time
25
10
ps
ms
ps
tOSC
Q0
100
500
Output
tR / tF
20% to 80%
Rise/Fall Time
Q1/nQ1
Q0
250
48
800
52
ps
%
%
Output
odc
Duty Cycle
Q1, nQ1
49
51
NOTE 1: Measured using Wavecrest SIA-3000.
NOTE 2: Measured using Wavecrest SIA-3000, Tj @ 10e-12BER result divided by 14.
843AG-75
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REV.A JANUARY 9, 2006
4
ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V
2V
SCOPE
SCOPE
VCC,
VCCO
VCC,
VCCO
Qx
Qx
LVCMOS
GND
LVPECL
VEE
nQx
-1.65V 0.15V
-1.3V 0.3V
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
VCC
nQ1
2
Q0
Q1
tPW
tPW
tPERIOD
tPERIOD
tPW
tPW
odc =
x 100%
x 100%
odc =
tPERIOD
tPERIOD
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
tF
80%
tF
80%
tR
80%
tR
VSWING
20%
20%
Clock
Outputs
20%
20%
Clock
Outputs
LVCMOS OUTPUT RISE/FALL TIME
LVPECL OUTPUT RISE/FALL TIME
843AG-75
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REV.A JANUARY 9, 2006
5
ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
LVCMOS OUTPUT:
An unused LVCMOS output should be terminated with 100Ω
to ground as close as possible to the device.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
CRYSTAL INPUT INTERFACE
The ICS843-75 has been characterized with 18pF parallel resonant crystal and were chosen to minimize the ppm error.
resonant crystals. The capacitor values, C1 and C2, shown in The optimum C1 and C2 values can be slightly adjusted for
Figure 1 below were determined using a 25MHz, 18pF parallel different board layouts.
XTAL_OUT
C1
12p
X1
18pF Parallel Crystal
XTAL_IN
C2
12p
Figure 1. CRYSTAL INPUt INTERFACE
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REV.A JANUARY 9, 2006
6
ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
Integrated
Circuit
Systems, Inc.
FREQUENCY STABILITY
The table shown below provides a basic guideline in se-
lecting the proper quartz crystal that meets a timing budget
of 100ppm. For more information on selecting the proper
crystal, see the application note, Crystal Timing Budget
and Accuracy for FemtoClock™ .
Parameter
Typical
Units
ppm
ppm
ppm
ppm
ppm
ppm
30
30
15
10
3
Frequency Tolerance
Frequency Stability
Aging for 10 Years
Accuracy of ICS Oscillator
Load Capacitance Accuracy
Total Overall Timing Error
88
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines.Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
Z
o = 50Ω
3.3V
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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REV.A JANUARY 9, 2006
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ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843-75.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843-75 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 110mA = 396mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 396mW + 30mW = 426mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6A
below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.426W * 90.5°C/W = 108.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6A.THERMAL RESISTANCE θJA FOR 8-PINTSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TABLE 6B. THERMAL RESISTANCE θJA FOR 8 LEAD SOIC FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV.A JANUARY 9, 2006
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ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 3.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT ANDT ERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination
voltage of V - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
L
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843AG-75
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REV.A JANUARY 9, 2006
9
ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOWTABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TABLE 7B. θJAVS. AIR FLOWT ABLE 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843-75 is: 2376
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REV.A JANUARY 9, 2006
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ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 8A. PACKAGE DIMENSIONS
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Millimeters
SYMBOL
Minimum
Maximum
MINIMUM
MAXIMUM
N
A
8
N
A
A1
B
C
D
E
e
8
--
1.20
0.15
1.05
0.30
0.20
3.10
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
1.27 BASIC
E1
e
4.30
4.50
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
0.45
0°
0.75
8°
L
α
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-153
843AG-75
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REV.A JANUARY 9, 2006
11
ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS843AG-75
Marking
43A75
43A75
TBD
Package
8 lead TSSOP
Shipping Packaging Temperature
tube
2500 tape & reel
tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS843AG-75T
ICS843AG-75LF
ICS843AG-75LFT
ICS843AM-75
8 lead TSSOP
8 lead "Lead-Free" TSSOP
8 lead "Lead-Free" TSSOP
8 lead SOIC
TBD
2500 tape & reel
tube
TBD
ICS843AM-75T
ICS843AM-75LF
ICS843AM-75LFT
TBD
8 lead SOIC
2500 tape & reel
tube
TBD
8 lead "Lead-Free" SOIC
8 lead "Lead-Free" SOIC
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
843AG-75
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REV.A JANUARY 9, 2006
12
相关型号：
ICS8430-71B
700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICSI
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