ICS8535AG-01T [ICSI]
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER; 低偏移， 1到4 LVCMOS - TO- 3.3V的LVPECL扇出缓冲器
| 型号： | ICS8535AG-01T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER |
| 文件： | 总12页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8535-01 is a low skew, high performance • 4 differential 3.3V LVPECL outputs
1-to-4 LVCMOS-to-3.3V LVPECL fanout buffer
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8535-01 has two single ended clock inputs.
• Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
HiPerClockS™
• CLK0 or CLK1 can accept the following differential input
the single ended clock input accepts LVCMOS or LVTTL in-
put levels and translate them to 3.3V LVPECL levels. The
clock enable is internally synchronized to eliminate runt clock
pulses on the output during asynchronous assertion/
deassertion of the clock enable pin.
levels: LVCMOS or LVTTL
• Maximum output frequency up to 266MHz
• Translates LVCMOS and LVTTL levels to 3.3V
LVPECL levels
Guaranteed output and part-to-part skew characteristics
make the ICS8535-01 ideal for those applications demand-
ing well defined performance and repeatability.
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.9ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VEE
CLK_EN
CLK_SEL
CLK0
nc
Q0
D
CLK_EN
nQ0
VCC
Q1
nQ1
Q2
nQ2
VCC
Q3
Q
LE
CLK0
CLK1
0
1
Q0
nQ0
CLK1
nc
Q1
nQ1
nc
nc
VCC
CLK_SEL
nQ3
Q2
nQ2
ICS8535-01
20-Lead TSSOP
4.4mm x 6.5mm x 0.92mm body package
Q3
nQ3
G Package
Top View
ICS8535AG-01
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REV. B JULY 5, 2001
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ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VEE
Power
Input
Negative supply pin. Connect to ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock
input. When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Pulldown
3
CLK_SEL
Input
4
CLK0
CLK1
Input
Input
Pulldown LVCMOS / LVTTL clock input.
Pulldown LVCMOS / LVTTL clock input.
No connect.
6
5, 7, 8, 9
10, 13, 18
11, 12
14, 15
16, 17
19, 20
nc
Unused
Power
Output
Output
Output
Output
VCC
Positive supply pins. Conncect to 3.3V.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CLK0, CLK1
4
4
pF
pF
CIN
Input Capacitance
CLK_EN,
CLK_SEL
RPULLUP
Input Pullup Resistor
51
51
KΩ
KΩ
RPULLDOWN
Input Pulldown Resistor
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ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK0
Q0 thru Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0 thru nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
0
0
1
1
0
1
0
1
CLK1
CLK0
CLK1
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as show in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B.
Disabled
Enabled
CLK0, CLK1
CLK_EN
nQ0 - nQ3
Q0 - Q3
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
CLK0 or CLK1
Q0 thru Q3
LOW
nQ0 thru nQ3
HIGH
0
1
HIGH
LOW
ICS8535AG-01
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REV. B JULY 5, 2001
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ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
73.2°C/W (no airflow)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These rat-
ings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those
listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
IEE
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK0, CLK1
2
3.765
3.765
1.3
V
V
V
V
VIH
VIL
IIH
Input High Voltage
CLK_EN,
CLK_SEL
2
CLK0, CLK1
-0.3
-0.3
Input Low Voltage
Input High Current
Input Low Current
CLK_EN,
0.8
CLK_SEL
CLK0, CLK1,
CLK_SEL
V
IN = VCC = 3.465V
VIN = VCC = 3.465V
IN = 0V, VCC = 3.465V
150
5
µA
µA
µA
µA
CLK_EN
CLK0, CLK1,
CLK_SEL
V
-5
IIL
CLK_EN
VIN = 0V, VCC = 3.465V
-150
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 1.4
VCC - 2.0
0.6
VCC - 1.0
VCC - 1.7
0.85
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
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ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
fMAX Maximum Output Frequency
tPD
Minimum Typical
Maximum
266
Units
MHz
ns
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
IJ 266MHz
1.0
1.9
tsk(o)
tsk(pp)
tR
11
30
ps
150
ps
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
700
ps
tF
Output Fall Time
700
ps
odc
Output Duty Cycle
48
50
52
%
All parameters measured at 266MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the 50% point of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Uusing the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VCC
SCOPE
Qx
LVPECL
VCC = 2V
nQx
VEE =-1.3V ± 0.135V
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
Qx
nQx
Qy
nQy
tsk(o)
FIGURE 3 - OUTPUT SKEW
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ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
Qx
PART 1
nQx
Qy
PART 2
nQy
tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME
CLK0, CLK1
Q0 - Q3
nQ0 - nQ3
tPD
FIGURE 6 - PROPAGATION DELAY
CLK0, CLK 1, Qx
nQx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
FIGURE 7 - odc & tPERIOD
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REV. B JULY 5, 2001
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ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8535-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.25mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 x 30.2mW = 120.8mW
Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120.8mW = 294.05mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C
This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply
voltage, air flow, and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 20-pin TSSOP, Forced Convection
JA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 8 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of V - 2V.
CC
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
Pd_L = [(V
– (V
- 2V))/R ]*(V
- V
)
OH_MAX
OH_MAX
CC_MAX
L
CC_MAX
– (V
- 2V))/R ]*(V
- V
)
OL_MAX
CC_MAX
L
CC_MAX
OL_MAX
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CC_MAX
Using V
= 3.465, this results in V
= 2.465V
OH_MAX
CC_MAX
For logic low, V = V
= V – 1.7V
CC_MAX
OUT
OL_MAX
Using V
= 3.465, this results in V
= 1.765V
CC_MAX
OL_MAX
Pd_H = [(2.465V - (3.465V - 2V))/50 Ω]*(3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50 Ω]*(3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
JA by Velocity (Linear Feet per Minute)
200
0
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8535-01 is: 412
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ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - G SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
ICS8535AG-01
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<
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
72 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
ICS8535AG-01
ICS8535AG-01T
ICS8535AG-01
ICS8535AG-01
20 lead TSSOP
20 lead TSSOP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
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