ICS8602BYT [ICSI]

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL; 零延迟，差分至LVCMOS / LVTTL


型号：	ICS8602BYT
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL 零延迟，差分至LVCMOS / LVTTL
文件：	总10页 (文件大小：149K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

GENERAL DESCRIPTION

FEATURES

The ICS8602 is a high performance, low skew,

• Fully integrated PLL

,&6

1-to-9 Differential-to-LVCMOS/LVTTL Zero De-

• 9 LVCMOS/LVTTL outputs, 7Ω typical output impedance

HiPerClockS™

lay Buffer and a member of the HiPerClockS™

family of High Performance Clocks Solutions

from ICS. The CLK, nCLK pair can accept most

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

standard differential input levels. The VCO operates at a fre-

quency range of 250MHz to 500MHz. The external feedback

allows the device to achieve “zero delay” between the input

clock and the output clocks. The device is designed only for

1:1 input/output frequency ratios. The output divider allows a

wide input/output frequency range with the 250MHz to

500MHz VCO. The PLL_SEL pin can be used to bypass the

PLL for system test and debug purposes. In bypass mode,

the reference clock is routed around the PLL and into the in-

ternal output dividers.The low impedance LVCMOS/LVTTL out-

puts are designed to drive 50Ω series or parallel terminated

transmission lines. The effective fanout can be doubled by

utilizing the ability of the outputs to drive two series termi-

nated lines. The differential reference clock input will accept

any differential signal levels.

• Output frequency range: 15.625MHz to 250MHz

• Input frequency range: 15.625MHz to 250MHz

• VCO range: 250MHz to 500MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Cycle-to-cycle jitter: 36ps (typical)

• Output skew: 125ps (maximum)

• Static Phase Offset: TBD±100ps (typical)

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

BLOCK DIAGRAM

PIN ASSIGNMENT

SEL0

SEL1

32 31 30 29 28 27 26 25

V^DDA

VDD

V^DDO

CLK

GND

÷2

÷4

÷8

÷16

nCLK

CLK

ICS8602

GND

V^DDO

nCLK

PLL

DIV_SEL0

DIV_SEL1

GND

MR/nOE

GND

FB_IN

10 11 12 13 14 15 16

PLL_SEL

MR/nOE

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

8602BY

www.icst.com/products/hiperclocks.html

REV. F APRIL 16, 2003

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

V_DDA

V_DD

Power

Analog supply pin.

Core supply pin.

CLK

nCLK

Input Pulldown Non-inverting differential clock input.

Input

Pullup Inverting differential clock input.

5, 8, 12 16,

18, 22, 25, 29

GND

Power

Power supply ground.

Determines output divider valued in Table 3.

LVCMOS / LVTTL interface levels.

Feedback input to phase detector for regenerating clocks

with "zero delay". LVCMOS / LVTTL interface levels.

6, 7

DIV_SEL0, DIV_SEL1 Input Pulldown

FB_IN

V_DDO

Input Pulldown

Power

10, 14, 20,

24, 27, 31

Output supply pins.

11, 13, 15, 19, 21, Q0, Q1, Q2, Q3, Q4,

Clock outputs. 7Ω typical output impedance.

LVCMOS / LVTTL interface levels.

Output

23, 26, 28, 30

Q5, Q6, Q7, Q8

Active HIGH Master Reset. Active LOW output enable.

When logic HIGH, the internal dividers are reset and

MR/nOE

Input Pulldown the outputs are tri-stated (HiZ). When logic LOW, the

internal dividers and the outputs are enabled.

LVCMOS / LVTTL interface levels.

Selects between the PLL and the reference clock as

the input to the dividers. When HIGH, selects PLL.

When LOW, selects reference clock.

LVCMOS / LVTTL interface levels.

PLL_SEL

Input

Pullup

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

C_IN

Input Capacitance

Input Pullup Resistor

KΩ

R_PULLUP

R_PULLDOWNInput Pulldown Resistor

Power Dissipation Capacitance

(per output)

C_PD

V_DD, V_DDA, V_DDO= 3.47V

TBD

R_OUT

Output Impedance

Ω

TABLE 3A. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 1

fOUT = fIN

TABLE 3B. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 0

PLL BYPASS MODE

Frequency Divider

Frequency Range (MHz)

DIV_SEL1 DIV_SEL0

fIN

fOUT

fIN/2

fIN/4

fIN/8

fIN/16

Minimum

125

Maximum

250

62.5

125

31.25

15.625

62.5

31.25

8602BY

www.icst.com/products/hiperclocks.html

REV. F APRIL 16, 2003

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

4.6V

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

Inputs, V

-0.5V to V_DD+ 0.5 V

Outputs, V_O

-0.5V to V_DDO+ 0.5V

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

Package Thermal Impedance, θ_JA42.1°C/W (0 lfpm)

Storage Temperature, T -65°C to 150°C

STG

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

3.135

Typical

3.3

Maximum

3.465

Units

V_DD

V_DDA

V_DDO

I_DD

Core Supply Voltage

Analog Supply Voltage

Output Supply Voltage

Power Supply Current

Analog Supply Current

Output Supply Current

3.135

3.3

3.465

3.135

3.3

3.465

I_DDA

I_DDO

160

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

V_IH

V_IL

Input High Voltage

V_DD+ 0.3

0.8

Input Low Voltage

-0.3

DIV_SEL0, DIV_SEL1,

FB_IN, MR/nOE

V_DD= V_IN= 3.465V

150

µA

I_IH

Input High Current

PLL_SEL

_DD= V_IN= 3.465V

V_DD= 3.465V, V_IN= 0V

_DD= 3.465V, V_IN= 0V

DIV_SEL0, DIV_SEL1,

FB_IN, MR/nOE

-5

I_IL

Input Low Current

PLL_SEL

-150

2.6

µA

V_OH

V_OL

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

0.5

NOTE 1: Outputs terminated with 50Ω to V_DDO/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V±5%, TA = 0°C TO 70°C

Symbol Parameter

I_IHInput High Current

Test Conditions

Minimum

Typical

Maximum Units

CLK

_DD= V_IN= 3.465V

150

µA

nCLK

CLK

V_DD= V_IN= 3.465V

_DD= 3.465, V_IN= 0V

-5

-150

I_IL

Input Low Current

nCLK

V_PP

Peak-to-Peak Input Voltage

0.15

1.3

V_CMR

Common Mode Input Voltage; NOTE 1, 2

GND + 0.5

V_DD- 0.85

NOTE 1: Common mode voltage is defined as V_IH.

NOTE 2: For single ended applications, the maximum voltage for CLK, nCLK is V_DD+ 0.3V.

8602BY

www.icst.com/products/hiperclocks.html

REV. F APRIL 16, 2003

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

TABLE 5. AC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

f_MAX

tp_LH

Output Frequency

15.625

250

MHz

Propagation Delay,

Low-to-High; NOTE 1

PLL_SEL=0V, 0MHz ≤ f ≤ 250MHz

TBD

PLL_SEL = 3.3V, fREF = 133MHz,

fVCO = 266MHz

PLL_SEL = 3.3V, fREF = 50MHz,

fVCO = 100MHz

TBD±100

t(Ø)

Static Phase Offset; NOTE 2

tsk(o)

tjit(cc)

t_L

Output Skew; NOTE 3, 4

Measured on rising edge at V_DDO/2

125

Cycle-to-Cycle Jitter; NOTE 4 Measured on rising edge at V_DDO/2

PLL Lock Time

t_R

Output Rise Time

Output Fall Time

Output Duty Cycle

20% to 80% @ 50MHz

f = 250MHz

400

950

t_F

odc

All parameters measured at f_MAXunless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the output at V_DDO/2.

NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal

when the PLL is locked and the input reference frequency is stable.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at V_DDO/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

8602BY

www.icst.com/products/hiperclocks.html

REV. F APRIL 16, 2003

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

PARAMETER MEASUREMENT INFORMATION

V_DD, V_DDA, V_DDO= 1.65V±5%

V_DD

SCOPE

nCLK

CLK

V_PP

V_CMR

Cross Points

LVCMOS

GND

GND = -1.65V±5%

3.3V OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVEL

V_DDO

Q0:Q8

➤

tcycle n

tcycle n+1

➤

V_DDO

tjit(cc) = tcycle n –tcycle n+1

1000 Cycles

tsk(o)

CYCLE-TO-CYCLE JITTER

OUTPUT SKEW

V_DDO

80%

Q0:Q8

Pulse Width

t_PERIOD

20%

Clock Outputs

t_PW

odc =

t_PERIOD

odc & t_PERIOD

OUTPUT RISE/FALL TIME

nCLK

CLK

nCLK

CLK

V_DD

V_DDO

Q0:Q8

FB_IN

➤

t(Ø)

➤

t(Ø) mean = Static Phase Offset

(where t(Ø) is any random sample, and t(Ø) mean is the average

of the sampled cycles measured on controlled edges)

STATIC PHASE OFFSET

PROPAGATION DELAY

8602BY

www.icst.com/products/hiperclocks.html

REV. F APRIL 16, 2003

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V_DD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V_DD= 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

VDD

Single Ended Clock Input

V_REF

CLK

nCLK

0.1u

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS8602 provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V_DD, V_DDA, and V_DDO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 2 illustrates how

a 10Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each V_DDApin.

3.3V

V_DD

.01µF

10Ω

V_DDA

.01µF

10 µF

FIGURE 2. POWER SUPPLY FILTERING

8602BY

www.icst.com/products/hiperclocks.html

REV. F APRIL 16, 2003

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the

and other differential signals. Both V_SWINGand V_OHmust meet the driver component to confirm the driver termination requirements.

V_PPand V_CMRinput requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS

face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTLdrivers. If you are using an LVHSTLdriver

the most common driver types. The input interfaces suggested from another vendor, use their termination recommendation.

3.3V

1.8V

Zo = 50 Ohm

CLK

Zo = 50 Ohm

CLK

Zo = 50 Ohm

nCLK

Zo = 50 Ohm

HiPerClockS

Input

LVPECL

nCLK

HiPerClockS

Input

LVHSTL

ICS

HiPerClockS

LVHSTL Driver

FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

ICS HIPERCLOCKS LVHSTL DRIVER

FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

3.3V

Zo = 50 Ohm

3.3V

125

LVDS_Driver

Zo = 50 Ohm

CLK

100

nCLK

Receiv er

nCLK

HiPerClockS

Input

Zo = 50 Ohm

LVPECL

FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

8602BY

www.icst.com/products/hiperclocks.html

REV. F APRIL 16, 2003

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

RELIABILITY INFORMATION

TABLE 6. θ_JAVS. AIR FLOW TABLE

q_JAby Velocity (Linear Feet per Minute)

200

500

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

67.8°C/W

47.9°C/W

55.9°C/W

42.1°C/W

50.1°C/W

39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TRANSISTOR COUNT

The transistor count for ICS8602 is: 1828

8602BY

www.icst.com/products/hiperclocks.html

REV. F APRIL 16, 2003

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

PACKAGE OUTLINE - Y SUFFIX

TABLE 7. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

BBA

SYMBOL

MINIMUM

NOMINAL

MAXIMUM

1.60

0.15

1.45

0.45

0.20

0.05

1.35

0.30

0.09

1.40

0.37

9.00 BASIC

7.00 BASIC

5.60 Ref.

9.00 BASIC

7.00 BASIC

5.60 Ref.

0.80 BASIC

0.60

0.45

0.75

7°

ccc

0.10

Reference Document: JEDEC Publication 95, MS-026

8602BY

www.icst.com/products/hiperclocks.html

REV. F APRIL 16, 2003

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

TABLE 8. ORDERING INFORMATION

Part/Order Number

ICS8602BY

Marking

Package

32 Lead LQFP

Count

250 per tray

1000

Temperature

0°C to 70°C

ICS8602BY

ICS8602BYT

32 Lead LQFP on Tape and Reel

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or

for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for

use in life support devices or critical medical instruments.

8602BY

www.icst.com/products/hiperclocks.html

REV. F APRIL 16, 2003

ICS8602BYT [ICSI]

相关型号：

ICS8602Y

ICS8602YLF

ICS8602YLFT

ICS8624

ICS8624AYLF

ICS8624AYLFT

ICS8624AYT

ICS8624BY

ICS8624BYI

ICS8624BYILF

ICS8624BYILFT

ICS8624BYIT