ICS874004AGT [ICSI]
PCI EXPRESS JITTER ATTENUATOR; PCI EXPRESS抖动衰减器型号: | ICS874004AGT |
厂家: | INTEGRATED CIRCUIT SOLUTION INC |
描述: | PCI EXPRESS JITTER ATTENUATOR |
文件: | 总10页 (文件大小:182K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
ICS874004
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
Features
The ICS874004 is a high performance Differential- • (4) Differential LVDS output pairs
ICS
to HCSL Jitter Attenuator designed for use in PCI
• (1) Differential clock input
HiPerClockS™
Express™ systems. In some PCI Express™
systems, such as those found in desktop PCs, the
PCI Express™ clocks are generated from a low
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
bandwidth, highphase noise PLL frequency synthesizer.In these
systems, a jitter attenuator may be required to attenuate high
frequency random and deterministic jitter components from the
PLL synthesizer and from the system board. The ICS874004
has 3 PLL bandwidth modes: 200KHz, 400KHz, and 800KHz.
200KHz mode will provide maximum jitter attenuation, but with
higher PLL tracking skew and spread spectrum modulation from
the motherboard synthesizer may be attenuated. 400KHz
provides an intermediate bandwidth that can easily track
triangular spread profiles, while providing good jitter attenuation.
800KHz bandwidth provides the best tracking skew and will pass
most spread profiles, but the jitter attenuation will not be as good
as the lower bandwidth modes. Because some 2.5 Gb serdes
have x20 multipliers while others have than x25 multipliers, the
874004 can be set for 1:1 mode or 5/4 multiplication mode (i.e.
100MHz input/125MHz output) using the F_SEL pin.
• Cycle-to-cycle jitter: 50ps (maximum) design target
• 3.3V operating supply
• 3 bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
• 0°C to 70°C ambient operating temperature
The ICS874004 uses ICS 3rd Generation FemtoClockTM
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express™ add-in cards.
PLL BANDWIDTH
BW_SEL
0 = PLL Bandwidth: ~200KHz
Float = PLL Bandwidth: ~400KHz (Default)
1 = PLL Bandwidth: ~800KHz
BLOCK DIAGRAM
PIN ASSIGNMENT
PU
OEA
nQA0
nQB0
QB0
1
24
23
22
21
20
19
18
17
16
15
14
13
QA0
PD
2
3
4
5
6
7
8
9
VDDO
QA1
F_SEL
QA0
VDDO
nQA1
QB1
nQB1
nFB_IN
FB_IN
Float
BW_SEL
0 = ~200KHz
0 ÷5
(default)
FB_OUT
nFB_OUT
MR
BW_SEL
VDDA
nQA0
QA1
Float = ~400KHz
1 = ~800KHz
1
÷4
nQA1
PD
CLK
OEB
GND
nCLK
CLK
Phase
Detector
VCO
10
11
12
F_SEL
VDD
PU
PD
nCLK
FB_IN
490-640MHz
QB0
OEA
nQB0
PU
nFB_IN
ICS874004
QB1
24-LeadTSSOP
nQB1
FB_OUT
4.40mm x 7.8mm x 0.92mm
package body
÷5
G Package
Top View
nFB_OUT
PD
PU
MR
OEB
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
874004AG
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REV. A JANUARY 21, 2005
1
PRELIMINARY
ICS874004
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 24
2, 3
4, 23
5
Name
nQA0, QA0
nQB0, QB0
VDDO
Type
Description
Output
Output
Power
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output supply pins.
FB_OUT
nFB_OUT
Non-inverting differential feedback output.
Inverting differential feedback output.
6
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (nQx) to go low and the inverted outputs
(Qx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
7
8
MR
Input
Pulldown
Pullup/
Pulldown
BW_SEL
Input
Selects PLL Band Width input. LVCMOS/LVTTL interface levels.
Analog supply pin.
9
VDDA
F_SEL
VDD
Power
Input
10
11
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Power
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
12
OEA
Input
Pullup
active. When LOW, the QAx/nQAx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
13
14
15
CLK
nCLK
GND
Input
Input
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
Power supply ground.
Power
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
active. When LOW, the QBx/nQBx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
16
OEB
Input
Pullup
17
18
FB_IN
Input
Input
Pulldown Non-inverting differential feedback input.
nFB_IN
Pullup
Inverting differential feedback input.
19, 20
21, 22
nQB1, QB1
nQA1, QA1
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL
Inputs
PLL
Inputs
Outputs
Bandwidth
~200KHz
~800KHz
~400KHz
BW_SEL
OEA
OEB QAx/nQAx QBx/nQBx FB_OUT/nFB_OUT
0
1
0
1
0
1
HiZ
HiZ
Enabled
Enabled
Enabled
Enabled
Float
874004AG
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REV. A JANUARY 21, 2005
2
PRELIMINARY
ICS874004
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
J
ITTER
ATTENUATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
60
8
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
82
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_SEL, MR,
OEA, OEB
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
VIH
VIL
Input High Voltage
BW_SEL
V
DD - 0.3
-0.3
F_SEL, MR,
OEA, OEB
Input Low Voltage
BW_SEL
-0.3
0.3
5
V
BW_SEL, OEA, OEB
F_SEL, MR
VDD = VIN = 3.465V
µA
µA
µA
IIH
Input High Current
Input Low Current
VDD = VIN = 3.465V
150
BW_SEL, OEA, OEB
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-150
-5
IIL
F_SEL, MR
V
µA
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = VIN = 3.465V
Minimum Typical Maximum Units
CLK, FB_IN
150
µA
µA
µA
µA
V
nCLK, nFB_IN
CLK, FB_IN
5
150
IIL
Input Low Current
nCLK, nFB_IN
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK and FB_IN, nFB_IN is VDD + 0.3V.
874004AG
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REV. A JANUARY 21, 2005
3
PRELIMINARY
ICS874004
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
350
50
mV
mV
V
∆ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.35
50
∆ VOS
VOS Magnitude Change
mV
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
98
160
MHz
ps
tjit(cc)
tR / tF
odc
Cycle-to-Cycle Jitter, NOTE 1
Output Rise/Fall Time
Output Duty Cycle
13
330
50
20ꢀ to 80ꢀ
ps
ꢀ
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
874004AG
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REV. A JANUARY 21, 2005
4
PRELIMINARY
ICS874004
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
3.3V
VDD
SCOPE
Qx
nCLK,
nFB_IN
POWER SUPPLY
Float GND
VPP
VCMR
LVDS
Cross Points
+
-
CLK,
nQx
FB_IN
GND
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQAx,
nQBx
nQAx,
nQBx
QAx,
QBx
QAx,
QBx
Pulse Width
➤
➤
tPERIOD
tcycle n
tcycle n+1
➤
➤
tPW
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
odc =
tPERIOD
CYCLE-TO-CYCLE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
80ꢀ
tF
out
80ꢀ
VSWING
20ꢀ
➤
DC Input
LVDS
Clock
20ꢀ
Outputs
tR
out
VOS/∆ VOS
➤
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
VDD
➤
out
out
LVDS
DC Input
100
V
OD/∆ VOD
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
874004AG
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REV. A JANUARY 21, 2005
5
PRELIMINARY
ICS874004
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS874004 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VDDA pin.
3.3V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V,V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
874004AG
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REV. A JANUARY 21, 2005
6
PRELIMINARY
ICS874004
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
J
ITTER
ATTENUATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
3.3V
3.3V
LVDS_Driv er
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
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874004AG
REV. A JANUARY 21, 2005
7
PRELIMINARY
ICS874004
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS874004 is: 1216
874004AG
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REV. A JANUARY 21, 2005
8
PRELIMINARY
ICS874004
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
874004AG
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REV. A JANUARY 21, 2005
9
PRELIMINARY
ICS874004
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS874004AG
Marking
Package
Shipping Packaging
Temperature
0°C to 70°C
0°C to 70°C
ICS874004AG
ICS874004AG
24 Lead TSSOP
24 Lead TSSOP
tube
ICS874004AGT
2500 tape & reel
The aforementioned trademarks, HiPerClockS™ and PCI ExpresS™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
874004AG
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REV. A JANUARY 21, 2005
10
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