ICS8761CYT [ICSI]
LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR; 低电压，低偏移， PCI / PCI -X时钟发生器
| 型号： | ICS8761CYT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR |
| 文件： | 总15页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
GENERAL DESCRIPTION
FEATURES
• Fully integrated PLL
The ICS8761 is a low voltage, low skew PCI /
ICS
PCI-X Clock Generator and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS.The ICS8761 has a selectable
REF_CLK or crystal input. The REF_CLK input
• 17 LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_CLK
HiPerClockS™
• Maximum output frequency: 166.67MHz
• Maximum crystal input frequency: 38MHz
• Maximum REF_CLK input frequency: 83.33MHz
• Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz simultaneously
accepts LVCMOS or LVTTL input levels. The ICS8761 has a
fully integrated PLL along with frequency configurable clock
and feedback outputs for multiplying and regenerating clocks
with “zero delay”. Using a 20MHz or 25MHz crystal or a
33.333MHz or 66.666MHz reference frequency, the ICS8761
will generate output frequencies of 33.333MHz, 66.666MHz,
100MHz and 133.333MHz simultaneously.
• Separate feedback control for generating PCI / PCI-X
frequencies from a 20MHz or 25MHz crystal or 33.333MHz
or 66.666MHz reference frequency
The low impedance LVCMOS/LVTTL outputs of the ICS8761
are designed to drive 50Ω series or parallel terminated
transmission lines.
• Cycle-to-cycle jitter: 70ps (maximum)
• Period jitter, RMS: 17ps (maximum)
• Output skew: 230ps (maximum)
• Bank skew: 40ps (maximum)
• Static phase offset: 0 150ps (maximum)
• Full 3.3V or 3.3V core, 2.5V multiple output supply modes
• 0°C to 85°C ambient operating temperature
• Lead-Free package available
BLOCK DIAGRAM
OEA
MR
D_SELA0
D_SELA1
QA0
QA1
PIN ASSIGNMENT
REF_CLK
XTAL1
0 0
0 1
1 0
1 1
0
1
÷3
÷4
QA2
QA3
0
1
÷6
OSC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
÷12
XTAL2
PLL
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
G
ND
REF_CLK
GND
QB0
QB1
QB2
QB3
XTAL_SEL
FB_IN
FB_OUT
0 0
0 1
1 0
1 1
V
DDOFB
XTAL1
XTAL2
PLL_SEL
OEB
FB_IN
V
DD
V
DD
FBDIV_SEL0
FBDIV_SEL1
MR
D_SELB1
D_SELB0
XTAL_SEL
PLL_SEL
QC0
QC1
QC2
QC3
0 0
0 1
1 0
1 1
V
DDA
DD
ICS8761
OEC
V
DD
V
9
40
39
38
37
36
35
34
33
D_SELC0
D_SELD0
10
11
12
13
14
15
16
D_SELC1
OEC
D_SELD1
OED
D_SELC1
D_SELC0
OEA
OEB
QD0
QD1
OED
0 0
0 1
1 0
1 1
D_SELA0
D_SELA1
GND
D_SELB0
D_SELB1
GND
QD2
QD3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D_SELD1
D_SELD0
÷6
÷12
÷16
÷20
0 0
0 1
1 0
1 1
64-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
FB_OUT
TopView
FBDIV_SEL1
FBDIV_SEL0
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
1
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
REF_CLK
Input Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
2, 16, 17,
21, 25, 29,
33, 48, 52,
56, 60, 64
GND
Power
Power supply ground.
XTAL1,
XTAL2
3, 4
Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Core supply pins.
5, 9, 40, 44
VDD
Power
Selects between crystal oscillator or reference clock as the PLL
reference source. Selects XTAL inputs when HIGH. Selects REF_CLK
when LOW. LVCMOS / LVTTL interface levels.
Selects between PLL and bypass mode. When HIGH, selects PLL.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
6
XTAL_SEL
Input
Pullup
Pullup
7
8
PLL_SEL
VDDA
Input
Power
Analog supply pin. See Applications Note for filtering.
D_SELC0,
D_SELC1
Selects divide value for Bank C outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
10, 11
Input Pulldown
Determines state of Bank C outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Determines state of Bank A outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Selects divider value for Bank A outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
12
13
OEC
OEA
Input
Input
Pullup
Pullup
D_SELA0,
D_SELA1
QA0, QA1,
QA2, QA3
14, 15
Input Pulldown
18, 20,
22, 24
Bank A clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
19, 23
VDDOA
Power
Output supply pins for Bank A outputs.
26, 28,
30, 32
QB0, QB1,
QB2, QB3
Bank B clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
27, 31
VDDOB
Power
Output supply pins for Bank B outputs.
D_SELB1,
D_SELB0
Selects divider value for Bank B outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
34, 35
Input Pulldown
Determines state of Bank B outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Determines state of Bank D outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Selects divider value for Bank D outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Active HIGH Master reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled.
36
37
OEB
OED
Input
Input
Pullup
Pullup
D_SELD1,
D_SELD0
38, 39
Input Pulldown
Input Pulldown
41
MR
LVCMOS / LVTTL interface levels.
Selects divider value for bank feedback output as described in Table 3.
LVCMOS / LVTTL interface levels.
Selects divider value for bank feedback output as described in Table 3.
LVCMOS / LVTTL interface levels.
Feedback input to phase detector for generating clocks with "zero
delay". LVCMOS / LVTTL interface levels.
42
43
45
FBDIV_SEL1 Input Pulldown
FBDIV_SEL0
FB_IN
Input
Pullup
Input Pulldown
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
2
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
Number
Name
Type
Description
Output supply pin for FB_Out output.
46
VDDOFB
Power
Feedback output. Connect to FB_IN. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
47
FB_OUT
Output
49, 51,
53, 55
50, 54
57, 59,
61, 63
QD3, QD2,
QD1, QD0
VDDOD
QC3, QC2,
QC1, QC0
Bank D clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank D outputs.
Bank C clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
Power
Output
Power
58, 62
VDDOC
Output supply pins for Bank C outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
pF
pF
Ω
RPULLUP
51
51
9
RPULLDOWN Input Pulldown Resistor
VDD, VDDA = 3.465V; VDDOx = 3.465V
VDD, VDDA = 3.465V; VDDOx = 2.625V
Power Dissipation Capacitance
(per output); NOTE 1
CPD
11
ROUT
Output Impedance
15
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, VDDOFB
.
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs
Outputs
MR
1
OEA
OEB
OEC
OED
QA0:QA3
LOW
QB0:QB3
LOW
QC0:QC3
LOW
QD0:QD3
1
1
0
1
1
0
1
1
0
1
1
0
LOW
Active
HiZ
0
Active
HiZ
Active
HiZ
Active
HiZ
X
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs
Operating Mode
PLL_SEL
XTAL_SEL
PLL Input
REF_CLK
0
1
Bypass
PLL
0
1
XTAL Oscillator
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
3
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
TABLE 3D. CONTROL FUNCTION TABLE
Outputs
Inputs
PLL_SEL =1
QX0:QX3
Frequency
Reference
QX0:QX3
(MHz)
FB_OUT
(MHz)
D_SELx1 D_SELx0 FBDIV_SEL1 FBDIV_SEL0 Frequency Range
(MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
x 2
x 4
83.33 - 166.67 41.6 - 83.33
83.33 - 166.67 20.83 - 41.67
83.33 - 166.67 15.62 - 31.25
x 5.33
x 6.67
x 1.5
x 3
83.33 - 166.67
62.4 - 125
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
62.4 - 125
x 4
62.4 - 125
x 5
62.4 - 125
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
x 1
41.6 - 83.33
41.6 - 83.33
41.6 - 83.33
41.6 - 83.33
20.8 - 41.67
20.8 - 41.67
20.8 - 41.67
20.8 - 41.67
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
x 2
x 2.67
x 3.33
÷ 2
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
÷ 1
x 1.33
x 1.67
NOTE: D_SELX1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELX0 denotes D_SELA0, D_SELB0,
D_SELC0, and D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
TABLE 3E. CONTROL FUNCTION TABLE (PCI CONFIGURATION)
Outputs
Frequency
Inputs
PLL_SEL = 1
QX0:QX3
Reference Frequency
(MHz)
QX0:QX3
FB_OUT
(MHz)
D_SELx1 D_SELx0 FBDIV_SEL1 FBDIV_SEL0
(MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
33.33
25
x 2
x 4
133
66.67
33.33
25
133
133
x 5.33
x 6.67
x 1.5
x 3
20
133
20
66.67
33.33
25
100
66.67
33.33
25
100
x 4
100
20
x 5
100
20
66.67
33.33
25
x 1
66.67
66.67
66.67
66.67
33.33
33.33
33.33
33.33
66.67
33.33
25
x 2
x 2.67
x 3.33
÷ 2
20
20
66.67
33.33
25
66.67
33.33
25
÷ 1
x 1.33
x 1.67
20
20
NOTE: D_SELx1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELx0 denotes D_SELA0, D_SELB0,
D_SELC0, and D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
4
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VDD
Inputs, VI
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
-0.5V to VDD + 0.5 V
-0.5V to VDDOx + 0.5V
Outputs, VO
PackageThermal Impedance, θJA 41.1°C/W (0 lfpm)
StorageTemperature, TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V 5ꢀ, TA = 0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDOx
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
175
V
V
Analog Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
V
mA
mA
mA
IDDA
Analog Supply Current
55
IDDOx
Output Supply Current; NOTE 2
25
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, and VDDOFB
NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOD, and IDDOFB
.
.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V 5ꢀ, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
OEA:OED, XTAL_SEL, MR,
D_SELA0:D_SELD0, FB_IN,
D_SELA1:D_SELD1, PLL_SEL,
FBDIV_SEL0, FBDIV_SEL1
2
VDD + 0.3
V
Input
VIH
High Voltage
REF_CLK
2
VDD + 0.3
0.8
V
V
OEA:OED, XTAL_SEL, MR,
D_SELA0:D_SELD0, FB_IN,
D_SELA1, D_SELD1, PLL_SEL
-0.3
-0.3
Input
VIL
Low Voltage
REF_CLK
1.3
V
D_SELA0:D_SELD0, FB_IN, MR,
D_SELA1:D_SELD1, REF_CLK,
FBDIV_SEL1
VDD = VIN = 3.465V
150
µA
Input
IIH
High Current
XTAL_SEL, PLL_SEL,
V
DD = VIN = 3.465V
5
µA
µA
FBDIV_SEL0, OEA:OED
D_SELA0:D_SELD0, FB_IN, MR,
D_SELA1:D_SELD1, REF_CLK,
FBDIV_SEL1
VDD = 3.465V,
VIN = 0V
-5
Input
IIL
Low Current
VDD = 3.465V,
XTAL_SEL, PLL_SEL,
FBDIV_SEL0, OEA:OED
-150
2.6
µA
VIN = 0V
VOH
VOL
IOZL
IOZH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
5
Output Tristate Current Low
Output Tristate Current High
-5
µA
µA
NOTE 1: Outputs terminated with 50Ω to VDDOx/2. See Parameter Measurement Information section,
"3.3V Output Load Test Circuit".
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
5
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V 5ꢀ, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
fMAX
Output Frequency
166.67
150
40
MHz
ps
t(Ø)
Static Phase Offset; NOTE 1, 7
Bank Skew; NOTE 2, 6
f = 50MHz
-150
tsk(b)
tsk(o)
ps
Output Skew; NOTE 3, 6
230
70
ps
f = 50MHz; NOTE 4, 7
ps
tjit(cc)
Cycle-to-Cycle Jitter; 6
f = 25MHz XTAL,
133.3MHz out
190
ps
tjit(per)
Period Jitter, RMS; NOTE 4, 6, 7, 8
PLL Lock Time
17
1
ps
ms
ps
ps
ꢀ
tL
tR
Output Rise Time
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
300
300
45
800
800
55
tF
Output Fall Time
odc
Output Duty Cycle; NOTE 5, 7
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable. Measured from VDD/2 of the input to
VDDOx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOx/2.
NOTE 4: Jitter performance using LVCMOS inputs.
NOTE 5: Measured using REF_CLK. For XTAL input, refer to Application Note.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 7: Tested with D_SELXX =10 (divide by 6); FBDIV_SEL = 00 (divide by 6).
NOTE 8: This parameter is defined as an RMS value.
8761CY
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REV. C SEPTEMBER 7, 2004
6
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDOX = 2.5V 5ꢀ, TA = 0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDOx
IDD
Core Supply Voltage
3.135
3.135
2.375
3.3
3.3
2.5
3.465
3.465
2.625
160
V
V
Analog Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
V
mA
mA
mA
IDDA
Analog Supply Current
50
IDDOx
Output Supply Current; NOTE 2
210
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, and VDDOFB
NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOD, and IDDOFB
.
.
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDOX = 2.5V 5ꢀ, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
OEA:OED, XTAL_SEL, MR,
D_SELA0:D_SELD0, FB_IN,
D_SELA1:D_SELD1, PLL_SEL,
FBDIV_SEL0, FBDIV_SEL1
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
Input
VIH
High Voltage
REF_CLK
2
OEA:OED, XTAL_SEL, MR,
D_SELA0:D_SELD0, FB_IN,
D_SELA1:D_SELD1, PLL_SEL,
FBDIV_SEL0, FBDIV_SEL1
-0.3
-0.3
Input
VIL
Low Voltage
REF_CLK
1.3
V
D_SELA0:D_SELD0, FB_IN, MR,
D_SELA1:D_SELD1, REF_CLK,
FBDIV_SEL1
VDD = VIN = 3.465V
150
µA
Input
IIH
High Current
XTAL_SEL, PLL_SEL,
V
DD = VIN = 3.465V
VDD = 3.465V,
5
µA
µA
FBDIV_SEL0, OEA:OED
D_SELA0:D_SELD0, FB_IN, MR,
D_SELA1:D_SELD1, REF_CLK,
FBDIV_SEL1
-5
V
IN = 0V
Input
IIL
Low Current
VDD = 3.465V,
VIN = 0V
XTAL_SEL, PLL_SEL,
FBDIV_SEL0, OEA:OED
-150
1.8
µA
VOH
VOL
IOZL
IOZH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
5
Output Tristate Current Low
Output Tristate Current High
-5
µA
µA
NOTE 1: Outputs terminated with 50Ω to VDDOx/2. See Parameter Measurement Information section,
"3.3V/2.5V Output Load Test Circuit".
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
7
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDOX = 2.5V 5ꢀ, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
fMAX
Output Frequency
166.67
20
MHz
ps
t(Ø)
Static Phase Offset; NOTE 1, 7
Bank Skew; NOTE 2, 6
f = 50MHz
-350
tsk(b)
tsk(o)
40
ps
Output Skew; NOTE 3, 6
230
70
ps
f = 50MHz; NOTE 4, 7
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 6
f = 25MHz XTAL,
133.3MHz out
190
ps
tjit(per)
Period Jitter, RMS; NOTE 4, 6, 7, 8
PLL Lock Time
17
1
ps
ms
ps
ps
ꢀ
tL
tR
Output Rise Time
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
300
300
45
800
800
55
tF
Output Fall Time
odc
Output Duty Cycle; NOTE 5, 7
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable. Measured from VDD/2 of the input to
VDDOX/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOx/2.
NOTE 4: Jitter performance using LVCMOS inputs.
NOTE 5: Measured using REF_CLK. For XTAL input, refer to Application Note.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 7: Tested with D_SELXX =10 (divide by 6); FBDIV_SEL = 00 (divide by 6).
NOTE 8: This parameter is defined as an RMS value
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
10
38
70
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
7
pF
TABLE 7. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V 5ꢀ, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
10 83.33 MHz
fREF
Reference Frequency
8761CY
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REV. C SEPTEMBER 7, 2004
8
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
2.05V 5ꢀ
SCOPE
SCOPE
VDD,
VDDA, VDDOx
VDD
VDDA
,
VDDOx
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.165V 5ꢀ
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDDO
2
VDDOX
Qx
Qx
Qy
2
VDDO
2
VDDOX
Qy
2
tsk(o)
tsk(o)
OUTPUT SKEW
BANK SKEW (Where X denotes outputs in the same Bank)
VDD
2
VDDOX
VDDOX
2
VDDOX
REF_CL:K
2
2
QAx,
QBx,
QCx,
QDx
➤
➤
tcycle n
tcycle n+1
➤
➤
VDD
2
FB_IN
➤
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
➤
t(Ø)
STATIC PHASE OFFSET
CYCLE-TO-CYCLE JITTER
VDDOX
2
VDDOX
VDDOX
2
80ꢀ
80ꢀ
2
QAx, QBx,
QCx, QDx,
FB_OUT
tPW
20ꢀ
20ꢀ
Clock Outputs
tPERIOD
t
t
F
R
tPW
tPERIOD
odc =
tPW & tPERIOD
OUTPUT RISE/FALL TIME
8761CY
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REV. C SEPTEMBER 7, 2004
9
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS8761 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDOx
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10 µF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS8761 crystal interface is shown in Figure 2.While layout
the PC Board, it is recommended to provide C1 and C2 spare
footprints for frequency fine tuning. For an 18pF parallel reso-
nant crystal, the C1 and C2 are expected to be ~10pF and ~5pF
respectively.
XTAL2
XTAL1
C1
SPARE
X1
18pF Parallel Crystal
C2
SPARE
FIGURE 2. CRYSTAL INPUT INTERFACE
8761CY
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REV. C SEPTEMBER 7, 2004
10
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS8761. In this near the power pin. For ICS8761, the unused clock outputs can
example, the input is driven by an ICS HiPerClockS LVHSTL be left floating. The optional C1 and C2 are spare footprints for
driver. The decoupling capacitors should be physically located frequency fine tuning.
Zo = 50
R1
36
VDDO
Receiver
VDD
Zo = 50
R2
36
U1
R5
1K
R6
1K
C1
SP
Receiver
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
X1
REF_CLK
GND
XTAL1
XTAL2
VDD
XTAL_SEL
PLL_SEL
VDDA
GND
FB_OUT
VDDOFB
FB_IN
25MHz,18pF
VDDO
VDD
R7
VDD
10
C2
SP
FBDIV_SEL0
FBDIV_SEL1
MR
VDD
VDD
VDD
C17
0.1u
C16
10u
D_SELC0
D_SELC1
OEC
D_SELD0
D_SELD1
OED
OEA
OEB
D_SELA0
D_SELA1
GND
D_SELB0
D_SELB1
GND
Zo = 50
R3
36
SP = Spare, Not Install
Receiver
ICS8761
VDDO
Zo = 50
R4
36
Logic Input Pin Examples
(U1,5)
(U1,9)
(U1,40)
(U1,44)
VDD
Set Logic
Input to '1'
Set Logic
VDD
Receiver
VDD
VDD=3.3V
Input to '0'
C6
C5
C4
0.1u
C3
VDDO=3.3V
0.1u
0.1u
0.1u
RU1
1K
RU2
SP
(U1,19)
(U1,23)
VDDO
(U1,27)
(U1,31)
(U1,50)
(U1,54)
(U1,58)
(U1,62)
(U1,46)
To Logic
Input pins
To Logic
Input pins
C7
0.1u
C8
C9
0.1u
C10
0.1u
C11
0.1u
C12
0.1u
C13
0.1u
C14
0.1u
C15
0.1u
RD1
SP
RD2
1K
0.1u
FIGURE 3. ICS8761 CLOCK GENERATOR SCHEMATIC EXAMPLE
8761CY
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REV. C SEPTEMBER 7, 2004
11
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 64 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
48.5°C/W
35.8°C/W
500
43.2°C/W
33.6°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
58.8°C/W
41.1°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8761 is: 6040
8761CY
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REV. C SEPTEMBER 7, 2004
12
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
PACKAGE OUTLINE - Y SUFFIX FOR 64 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCD
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
64
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
--
1.40
--
--
c
D
12.00 BASIC
10.00 BASIC
7.50 Ref.
12.00 BASIC
10.00 BASIC
7.50 Ref.
0.50 BASIC
--
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
8761CY
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REV. C SEPTEMBER 7, 2004
13
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
0°C to 85°C
0°C to 85°C
0°C to 85°C
ICS8761CY
ICS8761CYT
ICS8761CYLN
ICS8761CY
ICS8761CY
64 Lead LQFP
160 per tray
64 Lead LQFP on Tape and Reel
500
ICS8761CYLN
64 Lead "Lead-Free/Annealed" LQFP 160 per tray
64 Lead "Lead-Free/Annealed" LQFP
ICS8761CYLNT
ICS8761CYLF
ICS8761CYLFT
ICS8761CYLN
ICS8761CYLF
ICS8761CYLF
500
0°C to 85°C
0°C to 85°C
0°C to 85°C
on Tape and Reel
64 Lead "Lead-Free" LQFP
160 per tray
500
64 Lead "Lead-Free" LQFP
on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
8761CY
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REV. C SEPTEMBER 7, 2004
14
ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
Pin Description Table, revised Master Reset description.
A
T1
T1
2
2
8/15/02
Pin Description Table, pin 43 should be labeled at a PULL-UP instead of a
PULL-DOWN.
A
B
11/05/02
11/06/02
T4B, T4D
6, 8
1
LVCMOS DC Characteristics table -in the IIH and IIL rows, FBDIV_SEL0 was
deleted from the "pulldown" row and was added to the "pullup" row.
Features section, changed max. output frequency from 200MHz to 183.3MHz,
and max. REF_CLK input frequency from 100MHz to 91.6MHz.
T3D
4
Control Function Table - revised Reference Frequency Range column and
Frequency columns to reflect the output frequency change.
AC Characteristics tables - changed Output Frequency from 200MHz max. to
183.3MHz max.
T5A, T5B
7, 9
T1
2
Pin Description Table, revised crystal description.
T5A, T5B
7, 9
AC Characteristics tables - changed Period Jitter measurement to
Period Jitter, RMS and added NOTE 8.
B
B
1/20/03
3/25/03
10
Added Crystal information.
11
2
Added Schematic Example in the Application Information Section.
Pin Description Table - revised MR description.
T1
T4A, T4C
5, 7
Power Supply Tables - changed VDD parameter to read "Core Supply Voltage"
from "Positive Supply Voltage".
10
10
1
Deleted Crystal Input Interface section.
Updated Schematic Example diagram.
Updated Features to reflect T5A 3.3V AC Characteristics (see below).
T3D
T4A
4
5
Adjusted Ref. Frequency Range and Frequency columns.
Changed IDD max. from 150mA to 175mA, IDDA max. from 50mA to 55mA, and
C
4/10/03
IDDO max. from 330mA to 25mA.
T5A & T5B
6 & 8
Changed fMAX from 183.3MHz max. to 166.67MHz max.
Changed RMS tjit(per) from 20ps max. to 17ps max.
1
10
14
Features Section - added Lead-Free bullet.
Added Crystal Section.
Ordering Information Table - added Lead-Free/Annealed Part Number.
C
C
8/2/04
8/7/04
14
Ordering Information Table - added Lead-Free Part Number.
8761CY
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REV. C SEPTEMBER 7, 2004
15
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