ICS87931AYIT [IDT]
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32;![ICS87931AYIT](http://pdffile.icpdf.com/pdf2/p00235/img/icpdf/ICS87931AYIL_1381108_icpdf.jpg)
型号: | ICS87931AYIT |
厂家: | ![]() |
描述: | PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32 驱动 逻辑集成电路 |
文件: | 总14页 (文件大小:156K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS87931I is a low voltage, low skew
• Fully integrated PLL
,&6
LVCMOS/LVTTL Clock Multiplier/Zero Delay
• 6 LVCMOS/LVTTL outputs, 7Ω typical output impedance
HiPerClockS™
Buffer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from ICS.
With output frequencies up to 150MHz, the
• Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock
for redundant clock applications
ICS87931I is targeted for high performance clock applications.
Along with a fully integrated PLL, the ICS87931I contains fre-
quency configurable outputs and an external feedback input for
regenerating clocks with “zero delay”.
• Maximum output frequency: 150MHz
• VCO range: 220MHz to 480MHz
• External feedback for “zero delay” clock regeneration
• Output skew, Same Frequency: 300ps (maximum)
• Output skew, Different Frequency: 400ps (maximum)
• Cycle-to-cycle jitter: ±100ps (typical)
• 3.3V supply voltage
Selectable clock inputs, CLK1 and differential CLK0, nCLK0
support redundant clock applications. The CLK_SEL input de-
termines which reference clock is used. The output divider val-
ues of Bank A, B and C are controlled by the DIV_SELA,
DIV_SELB and DIV_SELC, respectively.
For test and system debug purposes, the PLL_SEL input al-
lows the PLL to be bypassed. When LOW, the nMR input re-
sets the internal dividers and forces the outputs to the high im-
pedance state.
• -40°C to 85°C ambient operating temperature
• Pin compatible with MPC931
The effective fanout of the ICS87931I can be increased to 12
by utilizing the ability of each output to drive two series termi-
nated transmission lines.
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
nc
VDDA
GND
QB0
POWER_DN
CLK1
QB1
VDDO
ICS87931I
nMR
EXTFB_SEL
CLK_SEL
PLL_SEL
nc
CLK0
nCLK0
GND
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87931AYI
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REV. A MARCH 14, 2003
1
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
BLOCK DIAGRAM
Pullup
Pullup
POWER_DN
PLL_SEL
Pulldown
Pullup
CLK_SEL
CLK1
0
Pullup
None
1
0
CLK0
0
1
QA0
QA1
÷2/÷4
÷2/÷4
PHASE
DETECTOR
1
VCO
÷2
nCLK0
Pulldown
Pullup
LPF
EXTFB_SEL
EXT_FB
1
0
QB0
QB1
÷8
Pulldown
Pulldown
DIV_SELA
DIV_SELB
Pullup
÷4/÷6
QC0
QC1
CLK_EN0
CLK_EN1
DIV_SELC
DISABLE
LOGIC
Pullup
Pulldown
POWER-ON RESET
Pullup
nMR
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REV. A MARCH 14, 2003
2
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 9, 17, 32
2
Name
nc
Type
Description
Unused
Power
No connect.
VDDA
Analog supply pin.
Controls the frequency being fed to the output dividers.
LVCMOS / LVTTL interface levels.
3
4
POWER_DN
CLK1
Input
Input
Pullup
Pullup
Clock input. LVCMOS / LVTTL interface levels.
Active LOW Master reset. When logic LOW, the internal dividers are
reset causing the outputs to go low. When logic HIGH, the internal
dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.
5
nMR
Input
Pullup
6
CLK0
nCLK0
GND
Input
Input
Pullup
none
Non-inverting differential clock input.
Inverting differential clock input.
Power supply ground.
7
8, 16, 24,25
Power
CLK_EN0,
CLK_EN1
Controls the enabling and disabling of the clock outputs. See Table 3B.
LVCMOS / LVTTL interface levels.
External feedback. When LOW, selects internal feedback.
When HIGH, selects EXT_FB. LVCMOS / LVTTL interface levels.
10, 11
Input
Pullup
Pullup
12
EXT_FB
VDDO
Input
Power
Output
13, 21, 28
14, 15
Output supply pins.
Bank C clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
QC0, QC1
Selects between the PLL and reference clocks as the input to the
output dividers. When HIGH, selects PLL. When LOW, bypasses
the PLL. LVCMOS / LVTTL interface levels.
18
19
PLL_SEL
CLK_SEL
Input
Input
Pullup
Clock select input. Selects the Phase Detector Reference.
Pulldown When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
20
EXTFB_SEL
QB1, QB0
Input
Pulldown External feedback select. LVCMOS / LVTTL interface levels.
Bank B clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
22, 23
Output
Bank A clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank A as described in Table 4A.
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank B as described in Table 4A.
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank C as described in Table 4A.
LVCMOS / LVTTL interface levels.
26, 27
29
QA1, QA0
DIV_SELA
DIV_SELB
DIV_SELC
Output
Input
Input
Input
Pulldown
30
Pulldown
31
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
Power Dissipation Capacitance
(per output)
CPD
VDDA, VDDO = 3.465V
TBD
7
pF
ROUT
Output Impedance
Ω
87931AYI
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REV. A MARCH 14, 2003
3
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Function
Control Pin
CLK_SEL
Logic 0
Logic 1
CLK1
CLK0, nCLK0
Bypass PLL
PLL_SEL
PLL Enabled
EXT_FB
EXTFB_SEL
POWER_DN
nMR
Internal Feedback
VCO/1
VCO/2
Master Reset/Output Hi Z
QA(÷2); QB(÷2); QC(÷4)
Enable Outputs
QA(÷4); QB(÷4); QC(÷6)
DIV_SELA:DIV_SELC
TABLE 3B. CLK_ENX FUNCTION TABLE
Inputs
CLK_EN1
CLK_EN0
DIV_SELA:DIVSELC
QB:QC LOW; QA Toggle
QA:QB LOW; QC Toggle
0
0
1
1
0
1
0
1
QB LOW; QA & QC Toggle
All Toggle
TABLE 4A. VCO FREQUENCY FUNCTION TABLE
Inputs
Outputs
QBx
QAx
QCx
DIV_
DIV_
DIV_
SELA SELB SELC
POWER_DN = 0 POWER_DN = 1 POWER_DN = 0 POWER_DN = 1 POWER_DN = 0 POWER_DN = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/2
VCO/2
VCO/2
VCO/2
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/2
VCO/2
VCO/4
VCO/4
VCO/2
VCO/2
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/6
VCO/4
VCO/6
VCO/4
VCO/6
VCO/4
VCO/6
VCO/8
VCO/12
VCO/8
VCO/12
VCO/8
VCO/12
VCO/8
VCO/12
TABLE 4B. INPUT REFERENCE FREQUENCY TO OUTPUT FREQUENCY FUNCTION TABLE (INTERNAL FEEDBACK ONLY)
Inputs
Outputs
QBx
QAx
QCx
DIV_
DIV_
DIV_
SELA SELB SELC
POWER_DN = 0 POWER_DN = 1 POWER_DN = 0 POWER_DN = 1 POWER_DN = 0 POWER_DN = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4x
4x
4x
4x
2x
2x
2x
2x
2x
2x
2x
2x
x
4x
4x
2x
2x
4x
4x
2x
2x
2x
2x
x
2x
4/3x
2x
x
2/3x
x
x
4/3x
2x
2/3x
x
2x
2x
x
x
4/3x
2x
2/3x
x
x
x
x
4/3x
2/3x
87931AYI
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REV. A MARCH 14, 2003
4
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
VCO
VCO/2
POWER_DN
QA(÷2)
QB(÷4)
QC(÷6)
FIGURE 1A. POWER_DN TIMING DIAGRAM
QA
QB
QC
CLK_EN0
CLK_EN1
QA(÷2)
QB(÷4)
QC(÷6)
CLK_EN0
CLK_EN1
FIGURE 1B. CLK_ENX TIMING DIAGRAM
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REV. A MARCH 14, 2003
5
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
DD
Inputs, V
-0.5V to VDDA + 0.5 V
-0.5V to VDDO + 0.5V
I
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, VO
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDDA
VDDO
IDDA
Analog Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
V
Output Supply Voltage
Analog Supply Current
Output Supply Current
V
TBD
TBD
mA
mA
IDDO
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
DIV_SELA:DIV_SELC,
CLK_EN0, CLK_EN1,
POWER_DN, nMR, CLK_SEL,
PLL_SEL, EXTFB_SEL
2
V
DD + 0.3
DD + 0.3
0.8
V
V
V
Input
VIH
High Voltage
CLK1, EXT_FB
2
V
DIV_SELA:DIV_SELC,
CLK_EN0, CLK_EN1,
POWER_DN, nMR, CLK_SEL,
PLL_SEL, EXTFB_SEL
-0.3
-0.3
2.4
Input
VIL
Low Voltage
CLK1, EXT_FB
1.3
V
µA
V
IIN
Input Current
±120
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
IOH = -20mA
IOL = 20mA
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, 3.3V Output Load Test Circuit.
TABLE 5C. DIFFERENTIAL DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
IIN
Input Current
±120
1.3
µA
V
VPP
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDDA + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
87931AYI
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REV. A MARCH 14, 2003
6
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
Input Reference Frequency
fREF
NOTE: Input reference frequency is limited by
the divider selection and the VCO lock range.
TBD
MHz
TABLE 7. AC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
QAx, QBx
÷2
÷4
÷6
150
120
80
MHz
MHz
MHz
ps
fMAX
Output Frequency QAx, QBx, QCx
QCx
CLK0, nCLK0 to EXT_FB
CLK1 to EXT_FB
-350
-100
-200
50
-50
200
Propagation Delay;
NOTE 1
tPD
ps
Same Frequency,
300
400
400
600
ps
ps
ps
ps
f
MAX ≤ 100MHz
Different Frequency,
MAX ≤ 100MHz
f
tsk(o)
Output Skew; NOTE 2, 4
Same Frequency,
fMAX > 100MHz
Different Frequency,
fMAX > 100MHz
tjitter(cc) Cycle-to-Cycle Jitter; NOTE 4
±100
50
ps
MHz
ns
fVCO
tR/tF
odc
tLOCK
tEN
PLL VCO Lock Range
Output Rise Time; NOTE 3
Output Duty Cycle
220
0.1
480
1
0.8V to 2.0V
%
PLL Lock Time
10
10
8
ms
ns
Output Enable Time; NOTE 3
Output Disable Time; NOTE 3
2
2
tDIS
ns
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
87931AYI
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REV. A MARCH 14, 2003
7
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
VDDA, VDDO = 1.65V±5%
VDDA
SCOPE
nCLK0
CLK0
Qx
LVCMOS
VPP
VCMR
Cross Points
GND
GND = -1.165V±5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
VDDO
VDDO
VDDO
VDDO
2
Qx
Qy
2
2
2
QAx,
QBx,
QCx
➤
➤
tcycle n+1
tcycle n
➤
➤
VDDO
2
tsk(o)
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
2V
2V
VDDO
0.8V
0.8V
2
Clock Outputs
CLK1
t
t
F
R
nCLK0
CLK0
OUTPUT RISE/FALL TIME
VDDO
2
VDDO
2
QAx,
QBx,
QCx
QAx, QBx, QCx
➤
Pulse Width
tPD
➤
tPERIOD
tPW
odc =
tPERIOD
PROPAGATION DELAY
odc & tPERIOD
87931AYI
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REV. A MARCH 14, 2003
8
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A MARCH 14, 2003
9
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTLdrivers. If you are using an LVHSTLdriver
from another vendor, use their termination recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3D show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
nCLK
HiPerClockS
Input
nCLK
HiPerClockS
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
87931AYI
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REV. A MARCH 14, 2003
10
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
SCHEMATIC EXAMPLE
Figure 4A shows a schematic example of using an ICS87931I. In
this example, the input is a 25MHz parallel resonant crystal with
load capacitor CL=18pF. The frequency fine tuning capacitors
C1 and C2 is 22pF and 18pF respectively. This example also
shows logic control input handling. The configuration is set at
F_SEL[2:0]=101, therefore, the output frequency is 156.25MHz.
It is recommended to have one decouple capacitor per power
pin. Each decoupling capacitor should be located as close as
possible to the power pin. The low pass filter R7, C11 and C16 for
clean analog supply should also be located as close to the VDDA
pin as possible. For LVDS driver, the unused output pairs should
be terminated with a 100Ω resistor across.
R1
43
Zo = 50
VDD
VDD
R7
10 - 15
Receiv er
VDD
U1
C16
10u
C11
0.01u
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
nc
GND
QB0
QB1
VDDO
3.3V
R3
1K
R4
1K
VDDA
POWER_DN
CLK1
nMR
CLK0
nCLK0
GND
POWER_DN
Zo = 50 Ohm
EXTFB_SEL
CLK_SEL
PLL_SEL
nc
Zo = 50 Ohm
R5
1K
3.3V PECL Driver
R8
50
R9
50
ICS87931I
Logic Input Pin Examples
Set Logic
R10
50
Set Logic
Input to
’0’
VDD
VDD
Zo = 50
Input to
’1’
R2
43
RU1
1K
RU2
Not Install
Receiv er
To Logic
Input
pins
To Logic
Input
pins
(U1-13)
C1
(U1-21)
(U1-28)
VDD
RD1
RD2
1K
C2
0.1uF
C3
0.1uF
VDD=3.3V
Not Install
0.1uF
SP = Space (i.e. not intstalled)
FIGURE 4A. ICS87931I SCHEMATIC EXAMPLE
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REV. A MARCH 14, 2003
11
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87931I is: 2942
87931AYI
www.icst.com/products/hiperclocks.html
REV. A MARCH 14, 2003
12
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
87931AYI
www.icst.com/products/hiperclocks.html
REV. A MARCH 14, 2003
13
PRELIMINARY
ICS87931I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS87931AYI
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS87931AI
ICS87931AI
ICS87931AYIT
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
87931AYI
www.icst.com/products/hiperclocks.html
REV. A MARCH 14, 2003
14
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