ICS87931BYI [ICSI]
LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER; 低偏移， 1到6 LVCMOS / LVTTL时钟乘法器/零延迟缓冲器
| 型号： | ICS87931BYI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER |
| 文件： | 总14页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS87931I is a low voltage, low skew
• Fully integrated PLL
LVCMOS/LVTTL Clock Multiplier/Zero Delay
• 6 LVCMOS/LVTTLoutputs, 7Ω typical output impedance
HiPerClockS™
Buffer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from ICS.
With output frequencies up to 150MHz, the
• Selectable differential CLK0, nCLK0 or LVCMOS/LVTTLclock
for redundant clock applications
ICS87931I is targeted for high performance clock applications.
Along with a fully integrated PLL, the ICS87931I contains fre-
quency configurable outputs and an external feedback input for
regenerating clocks with “zero delay”.
• Maximum output frequency: 150MHz
• VCO range: 220MHz to 480MHz
• External feedback for “zero delay” clock regeneration
• Output skew, Same Frequency: 300ps (maximum)
• Output skew, Different Frequency: 400ps (maximum)
• Cycle-to-cycle jitter: 100ps (maximum)
• 3.3V supply voltage
Selectable clock inputs, CLK1 and differential CLK0, nCLK0
support redundant clock applications. The CLK_SEL input de-
termines which reference clock is used. The output divider val-
ues of Bank A, B and C are controlled by the DIV_SELA,
DIV_SELB and DIV_SELC, respectively.
• -40°C to 85°C ambient operating temperature
• Pin compatible with MPC931
For test and system debug purposes, the PLL_SEL input al-
lows the PLL to be bypassed. When LOW, the nMR input re-
sets the internal dividers and forces the outputs to the high im-
pedance state.
PIN ASSIGNMENT
The effective fanout of the ICS87931I can be increased to 12
by utilizing the ability of each output to drive two series termi-
nated transmission lines.
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
nc
VDDA
GND
QB0
ICS87931I
POWER_DN
CLK1
QB1
32-Lead LQFP
VDDO
7mm x 7mm x 1.4mm
package body
nMR
EXTFB_SEL
CLK_SEL
PLL_SEL
nc
CLK0
Y package
Top View
nCLK0
GND
9
10 11 12 13 14 15 16
BLOCK DIAGRAM
POWER_DN
Pullup
Pullup
PLL_SEL
Pulldown
Pullup
CLK1
CLK_SEL
0
1
Pullup
None
1
0
CLK0
0
QA0
QA1
÷2/÷4
÷2/÷4
PHASE
DETECTOR
VCO
÷2
nCLK0
1
Pulldown
Pullup
LPF
EXTFB_SEL
EXT_FB
1
0
QB0
QB1
÷8
Pulldown
Pulldown
DIV_SELA
DIV_SELB
Pullup
÷4/÷6
QC0
QC1
CLK_EN0
CLK_EN1
DIV_SELC
DISABLE
LOGIC
Pullup
Pulldown
POWER-ON RESET
Pullup
nMR
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REV. A JUNE 23, 2003
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ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
1, 9, 17, 32
2
Name
nc
Type
Description
Unused
Power
No connect.
VDDA
Analog supply pin.
Controls the frequency being fed to the output dividers.
LVCMOS / LVTTL interface levels.
3
4
POWER_DN
CLK1
Input
Input
Pullup
Pullup
Clock input. LVCMOS / LVTTL interface levels.
Active LOW Master reset. When logic LOW, the internal dividers are
reset causing the outputs to go low. When logic HIGH, the internal
dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.
5
nMR
Input
Pullup
Pullup
6
7
CLK0
nCLK0
GND
Input
Input
Power
Input
Non-inverting differential clock input.
Pullup/
Pulldown
Inverting differential clock input. VCC/2 default when left floating.
8, 16, 24,25
10, 11
Power supply ground.
CLK_EN0,
CLK_EN1
Controls the enabling and disabling of the clock outputs. See Table 3B.
LVCMOS / LVTTL interface levels.
External feedback. When LOW, selects internal feedback.
When HIGH, selects EXT_FB. LVCMOS / LVTTL interface levels.
Pullup
Pullup
12
EXT_FB
VDDO
Input
Power
Output
13, 21, 28
14, 15
Output supply pins.
Bank C clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
QC0, QC1
Selects between the PLL and reference clocks as the input to the
output dividers. When HIGH, selects PLL. When LOW, bypasses
the PLL. LVCMOS / LVTTL interface levels.
18
19
PLL_SEL
CLK_SEL
Input
Input
Pullup
Clock select input. Selects the Phase Detector Reference.
Pulldown When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
20
EXTFB_SEL
QB1, QB0
Input
Pulldown External feedback select. LVCMOS / LVTTL interface levels.
Bank B clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
22, 23
Output
Bank A clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank A as described in Table 4A.
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank B as described in Table 4A.
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank C as described in Table 4A.
LVCMOS / LVTTL interface levels.
26, 27
29
QA1, QA0
DIV_SELA
DIV_SELB
DIV_SELC
Output
Input
Input
Input
Pulldown
30
Pulldown
31
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
Power Dissipation Capacitance
(per output)
CPD
VDDA, VDDO = 3.465V
12
7
pF
ROUT
Output Impedance
Ω
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ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Function
Control Pin
CLK_SEL
Logic 0
Logic 1
CLK1
CLK0, nCLK0
Bypass PLL
PLL_SEL
PLL Enabled
EXT_FB
EXTFB_SEL
POWER_DN
nMR
Internal Feedback
VCO/1
VCO/2
Master Reset/Output Hi Z
QA(÷2); QB(÷2); QC(÷4)
Enable Outputs
QA(÷4); QB(÷4); QC(÷6)
DIV_SELA:DIV_SELC
TABLE 3B. CLK_ENX FUNCTION TABLE
Inputs
DIV_SELA:DIVSELC
CLK_EN1
CLK_EN0
QAx
Toggle
LOW
QBx
LOW
LOW
LOW
Toggle
QCx
LOW
0
0
1
1
0
1
0
1
Toggle
Toggle
Toggle
Toggle
Toggle
TABLE 4A. VCO FREQUENCY FUNCTION TABLE
Inputs
Outputs
QBx
QAx
QCx
DIV_
DIV_
DIV_
SELA SELB SELC
POWER_DN = 0 POWER_DN = 1 POWER_DN = 0 POWER_DN = 1 POWER_DN = 0 POWER_DN = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/2
VCO/2
VCO/2
VCO/2
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/2
VCO/2
VCO/4
VCO/4
VCO/2
VCO/2
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/6
VCO/4
VCO/6
VCO/4
VCO/6
VCO/4
VCO/6
VCO/8
VCO/12
VCO/8
VCO/12
VCO/8
VCO/12
VCO/8
VCO/12
TABLE 4B. INPUT REFERENCE FREQUENCY TO OUTPUT FREQUENCY FUNCTION TABLE (INTERNAL FEEDBACK ONLY)
Inputs
Outputs
QBx
QAx
QCx
DIV_
DIV_
DIV_
SELA SELB SELC
POWER_DN = 0 POWER_DN = 1 POWER_DN = 0 POWER_DN = 1 POWER_DN = 0 POWER_DN = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4x
4x
4x
4x
2x
2x
2x
2x
2x
2x
2x
2x
x
4x
4x
2x
2x
4x
4x
2x
2x
2x
2x
x
2x
4/3x
2x
x
2/3x
x
x
4/3x
2x
2/3x
x
2x
2x
x
x
4/3x
2x
2/3x
x
x
x
x
4/3x
2/3x
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ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
VCO
VCO/2
POWER_DN
QA(÷2)
QB(÷4)
QC(÷6)
FIGURE 1A. POWER_DN TIMING DIAGRAM
QA
QB
QC
CLK_EN0
CLK_EN1
QA(÷2)
QB(÷4)
QC(÷6)
CLK_EN0
CLK_EN1
FIGURE 1B. CLK_ENX TIMING DIAGRAMS
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ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
DD
Inputs, V
-0.5V to VDDA + 0.5 V
-0.5V to VDDO + 0.5V
I
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, VO
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDDA
VDDO
IDDA
Analog Supply Voltage
3.135
3.135
3.3
3.3
20
3.465
3.465
V
Output Supply Voltage
Analog Supply Current
Output Supply Current
V
mA
mA
IDDO
100
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
DIV_SELA:DIV_SELC,
CLK_EN0, CLK_EN1,
POWER_DN, nMR, CLK_SEL,
PLL_SEL, EXTFB_SEL
2
VDD + 0.3
V
V
V
Input
VIH
High Voltage
CLK1, EXT_FB
2
VDD + 0.3
DIV_SELA:DIV_SELC,
CLK_EN0, CLK_EN1,
POWER_DN, nMR, CLK_SEL,
PLL_SEL, EXTFB_SEL
-0.3
-0.3
2.4
0.8
Input
VIL
Low Voltage
CLK1, EXT_FB
1.3
V
µA
V
IIN
Input Current
±120
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
IOH = -20mA
IOL = 20mA
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, 3.3V Output Load Test Circuit.
TABLE 5C. DIFFERENTIAL DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
IIN
Input Current
±120
1.3
µA
V
VPP
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDDA + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
Input Reference Frequency
fREF
NOTE: Input reference frequency is limited by
the divider selection and the VCO lock range.
150
MHz
TABLE 7. AC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
QAx, QBx
÷2
÷4
÷6
150
120
80
MHz
MHz
MHz
ps
fMAX
Output Frequency QAx, QBx, QCx
QCx
CLK1 to EXT_FB
-375
-100
-200
50
-50
200
300
400
100
480
1
Propagation Delay;
NOTE 1
fref = 50MHz,
FB = ÷ 8
tPD
CLK0, nCLK0 to EXT_FB
ps
Same Frequency
ps
tsk(o)
Output Skew; NOTE 2, 4
Different Frequency
ps
tjitter(cc) Cycle-to-Cycle Jitter; NOTE 4
ps
fVCO
PLL VCO Lock Range
Output Rise Time; NOTE 3
Output Duty Cycle
220
0.1
45
MHz
ns
tR/tF
0.8V to 2.0V
odc
55
%
tLOCK
PLL Lock Time
10
ms
ns
tPZL, tPZH
tPLZ, tPHZ
Output Enable Time; NOTE 3
Output Disable Time; NOTE 3
2
2
10
8
ns
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A JUNE 23, 2003
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ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VDDA, VDDO = 1.65V±5%
VDDA
SCOPE
nCLK0
CLK0
Qx
LVCMOS
VPP
VCMR
Cross Points
GND
GND = -1.165V±5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
VDDO
VDDO
VDDO
VDDO
2
Qx
Qy
2
2
2
QAx,
QBx,
QCx
➤
➤
tcycle n+1
tcycle n
➤
➤
VDDO
2
tsk(o)
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
2V
2V
VDD
0.8V
0.8V
Clock Outputs
2
CLK1
t
t
F
R
nCLK0
CLK0
VDDO
OUTPUT RISE/FALL TIME
2
EXT_FB
VDDO
2
QAx, QBx, QCx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
PROPAGATION DELAY
odc & tPERIOD
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ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1. This bias circuit clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin. The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL CLOCK INPUT INTERFACE
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTLdrivers. If you are using an LVHSTLdriver
from another vendor, use their termination recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3D show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiver
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
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ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
SCHEMATIC EXAMPLE
Figure 4A shows a schematic example of using an ICS87931I. It
is recommended to have one decouple capacitor per power pin.
Each decoupling capacitor should be located as close as pos-
sible to the power pin. The low pass filter R7, C11 and C16 for
clean analog supply should also be located as close to the VDDA
pin as possible.
R1
43
Zo = 50
VDD
VDD
R7
10 - 15
Receiver
VDD
U1
C16
10u
C11
0.01u
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
nc
GND
QB0
QB1
3.3V
R3
1K
R4
1K
VDDA
POWER_DN
CLK1
nMR
CLK0
nCLK0
GND
POWER_DN
VDDO
Zo = 50 Ohm
EXTFB_SEL
CLK_SEL
PLL_SEL
nc
Zo = 50 Ohm
R5
1K
3.3V PECL Driver
R8
50
R9
50
ICS87931I
Logic Input Pin Examples
Set Logic
R10
50
Set Logic
Input to
’0’
VDD
VDD
Zo = 50
Input to
’1’
R2
43
RU1
1K
RU2
Not Install
Receiver
To Logic
Input
pins
To Logic
Input
pins
(U1-13)
C1
(U1-21)
(U1-28)
VDD
RD1
RD2
1K
C2
0.1uF
C3
0.1uF
VDD=3.3V
Not Install
0.1uF
SP = Space (i.e. not intstalled)
FIGURE 4A. ICS87931I SCHEMATIC EXAMPLE
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LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
The following component footprints are used in this layout
example:
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
• The differential 50Ω output traces should have same
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
length.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
• Make sure no other signal traces are routed between the
clock trace pair.
• The series termination resistors should be located as
close to the driver pins as possible.
50 Ohm
Trace
GND
VCC
C3
R1
VCCA
U1
VIA
Pin 1
Other
signals
C2
R2
C1
50 Ohm
Trace
FIGURE 4B. PCB BOARD LAYOUT FOR ICS87931I
87931BYI
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REV. A JUNE 23, 2003
11
ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87931I is: 2942
87931BYI
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REV. A JUNE 23, 2003
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ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - Y SUFFIX
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
87931BYI
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REV. A JUNE 23, 2003
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ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS87931BYI
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS87931BI
ICS87931BI
ICS87931BYIT
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
87931BYI
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REV. A JUNE 23, 2003
14
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