ICS9148F-26 [ICSI]
Frequency Generator & Integrated Buffers for PENTIUM/ProTM; 频率发生器和缓冲器集成奔腾/ ProTM
| 型号： | ICS9148F-26 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| 文件： | 总17页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9148-26
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
Features
3.3Voutputs:SDRAM, PCI, REF, 48/24MHz
The ICS9148-26 generates all clocks required for high speed
RISCorCISCmicroprocessorsystemssuchasIntel PentiumPro
orCyrix. Eightdifferentreferencefrequencymultiplyingfactors
are externally selectable with smooth frequency transitions.
2.5V outputs: CPU, IOAPIC
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1 to 4 ns, center 2.2 ns.
No external load cap for CL=18pF crystals
±250 ps CPU, PCI clock skew
FeaturesincludetwoCPU, sixPCIandfourteenSDRAMclocks.
Two reference outputs are available equal to the crystal
frequency. Plus the IOAPIC output powered by VDDL1. One
48 MHz for USB, and one 24 MHz clock for Super IO. Spread
Spectrum built in at ±0.5% or ±1.5% modulation to reduce the
EMI. Serial programming I2C interface allows changing
functions, stop clock programing and Frequency selection.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be stable
within 2ms after power-up. It is not recommended to use I/O
dual function pin for the slots (ISA, PIC, CPU, DIMM). The
add on card might have a pull up or pull down.
250ps (cycle to cycle) CPU jitter @ 66.66MHz
Smooth frequency switch, with selections from 50 to
133MHz CPU.
I2C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%.
48pin300milSSOPpackage
3.3V operation, 5V tolerant inputs (with series R)
<6ns propagation delay SDRAM form Buffer Input
Pin Configuration
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50±5% duty cycle. The REF and 24 and 48
MHz clock outputs typically provide better than 0.5V/ns slew
rates into 20pF.
Block Diagram
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Power Groups
VDD1=REF(0:1),X1,X2
VDD2=PCICLK_F,PCICLK(0:4)
VDD3=SDRAM(0:13), supplyforPLLcore
VDD4= 24MHz,48MHz
VDDL1=IOAPIC
VDDL2=CPUCLK(0:1)
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9148-26Rev D07/23/98
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148-26
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDD1
PWR Ref (0:2), XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the
STRONGER buffer for ISA BUS loads
2
REF0
OUT
3,9,16,22,
33,39,45
GND
X1
PWR Ground
Crystal input, has internal load cap (36pF) and feedback
4
IN
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
5
X2
OUT
6,14
VDD2
PCICLK_F
PWR Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
OUT Free running PCI clock
7
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
MODE1, 2
IN
8
10, 11, 12, 13
15
PCICLK0
OUT PCI clock output.
OUT PCI clock outputs.
PCICLK(1:4)
BUFFER IN
IN
Input to Fanout Buffers for SDRAM outputs.
Halts PCICLK(0:4) clocks at logic 0 level, when input low (In
mobile mode, MODE=0)
18
PCI_STOP#1
IN
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38,40,41
(Pins 17, 18 SDRAM output only if MODE=High)
SDRAM (0:13)
OUT SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
19,30,36
23
VDD3
SDATA
SCLK
PWR Supply for SDRAM (0:13) and CPU PLL Core, nominal 3.3V.
IN
IN
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
24
24MHz
FS11, 2
48MHz
FS01, 2
OUT 24MHz output clock
25
26
IN
OUT
IN
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
27
43, 44
42
VDD4
PWR Power for 24 & 48MHz output buffers and fixed PLL core.
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
CPUCLK(0:1)
VDDL2
REF1
OUT
PWR Supply for CPU (0:1), either 2.5V or 3.3V nominal
OUT 14.318 MHz reference clock.
46
17
FS21, 2
Frequency select pin. Latched Input
IN
Halts CPUCLK (0:1) clocks at logic 0 level, when input low (in
Mobile Mode, MODE=0)
CPU_STOP#1
IN
47
48
IOAPIC
VDDL1
OUT IOAPIC clock output. 14.318 MHz Powered by VDDL1.
PWR Supply for IOAPIC, either 2.5 or 3.3V nominal
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2
ICS9148-26
Mode Pin - Power Management Input Control
MODE, Pin 7
(Latched Input)
Pin 17
Pin 18
CPU_STOP#
(INPUT)
PCI_STOP#
(INPUT)
0
SDRAM11
(OUTPUT)
SDRAM10
(OUTPUT)
1
Power Management Functionality
PCICLK_F,
REF,
24/48MHz
and SDRAM
CPUCLK
Outputs
PCICLK
(0:4)
Crystal
OSC
CPU_STOP# PCI_STOP#
VCO
0
1
1
0
1
1
0
0
Stopped Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped Low
Stopped Low
Stopped Low
Functionality
VDD1,2,3=3.3V±5%,VDDL1,2=2.5V±5%or3.3±5%,TA=0to70°C
Crystal(X1,X2)=14.31818MHz
C PU
(M Hz)
P C IC LK
(M Hz)
REF, IO AP IC
(M Hz)
FS2
FS1
FS0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
100.2
133.31
112.01
103
66.8
83.3
75
33.3 (CPU/3)
33.3 (CPU/4)1
37.3 (CPU/3)1
34.3 (CPU/3)
33.4 (CPU/2)
41.65 (CPU/2)
37.5 (CPU/2)
25 (CPU/2)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
50
Note1. Performance not guaranteed
3
ICS9148-26
General I2C serial interface information
A.
For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with
an acknoledge bit between each byte.
Clock Generator
Address (7 bits)
Then Byte 0, 1, 2, etc in
sequence until STOP.
+ 8 bits dummy
command code
+ 8 bits dummy
Byte count
ACK
ACK
ACK
A(6:0) & R/W#
D2(H)
B.
The clock generator is a slave/receiver I2C component. It can read back the data stored in the latches for verification. (set
R/W# to 1 above) Read-Back will support Intel PIIX4 "Block-Read" protocol, with a "Byte count" following the
address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.
Clock Generator
Address (7 bits)
Then Byte 0, 1, 2, etc. in
sequence until STOP.
Byte Count
Readback
ACK
ACK
A(6:0) & R/W#
D3(H)
C.
D.
E.
F.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
G..
At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1 (Enabled
output state).
Serial Configuration Command Bitmap
Byte0:FunctionalityandFrequencySelectRegister(default=0)
Bit
Description
PWD
0 - ±1.5% Spread Spectrum Modulation
1 - ±0.5% Spread Spectrum Modulation
Bit 7
0
Bit6 Bit5 Bit4
CPU clock
PCI
Note1. Default at Power-up will be for
latched logic inputs to define
frequency. Bits 4, 5, 6 are default
to 000, and if bit 3 is written to a 1
to use Bits 6:4, then these should
be defined to desired frequency at
same write cycle.
111
110
101
100
011
010
001
000
100.2
33.3 (CPU/3)
33.32
133.32
112.02
103
66.8
83.3
75
50
37.32
Note1
34.3 (CPU/3)
33.4 (CPU/2)
41.65(CPU/2)
37.5 (CPU/2)
25 (CPU/2)
Bit 6:4
Note2. Performance not guaranteed
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
Note: PWD=Power-UpDefault
0 - Running
1- Tristate all outputs
I2C is a trademark of Philips Corporation
4
ICS9148-26
Byte1:CPU,Active/InactiveRegister(1=enable, 0=disable)
Bit
Pin #
-
-
-
-
40
41
43
44
PWD
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM12 (Act/Inact)
SDRAM13 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
Byte 2: PCIActive/Inactive Register(1 = enable, 0 = disable)
Bit
Pin #
-
7
PWD
Description
(Reserved)
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
-
14
12
11
10
8
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
Byte3:SDRAMActive/InactiveRegister(1=enable, 0=disable)
Bit
Pin #
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
-
-
26
25
-
1
1
1
1
1
(Reserved)
(Reserved)
48MHz (Act/Inact)
24 MHz (Act/Inact)
(Reserved)
SDRAM (8:11) (Active/Inactive)
(SDRAM 10, 11 only in Desktop Mode, MODE=1)
Bit 2
21,20,18,17
1
Bit 1
Bit 0
32,31,29,28
38,37,35,34
1
1
SDRAM (4:7) (Active/Inactive)
SDRAM (0:3) (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
5
ICS9148-26
Byte 4: Reserved Active/Inactive Register(1 = enable, 0 = disable)
Bit
Pin #
PWD
Description
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
Byte 5: Peripheral Active/Inactive Register(1 = enable, 0 = disable)
Bit
Pin #
-
-
-
47
-
-
46
2
PWD
Description
(Reserved)
(Reserved)
(Reserved)
IOAPIC0 (Act/Inact)
(Reserved)
(Reserved)
REF1 (Act/Inact)
REF0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
6
ICS9148-26
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-26. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-26.
3. All other clocks continue to run undisturbed.
4. SDRAM outputs are controlled by Buffer in signal, not affected by the ICS9148-26
CPU_STOP# signal.
7
ICS9148-26
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-26. It is used to turn off the PCICLK (0:4) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-26 internally.The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
8
ICS9148-26
Shared Pin Operation -
Input/Output Pins
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
Pins 7,25,26,46 on the ICS9148-26 serve as dual signal
functions to the device. During initial power-up, they act as
input pins. The logic level (voltage) that is present on these
pins at this time is read and stored into a 4-bit internal data
latch. At the end of Power-On reset, (see AC characteristics
for timing values), the device changes the mode of operations
for these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
9
ICS9148-26
Fig. 2a
Fig. 2b
10
ICS9148-26
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Supply Current
SYMBOL
CONDITIONS
MIN
2
TYP
MAX UNITS
V
IH
VDD+0.3
0.8
V
V
V
IL
VSS-0.3
IDD
IDDL
Fi
CL = 0 pF; Select @ 66M
77
6.0
180
mA
mA
MHz
30
Input frequency
Input Capacitance1
VDD = 3.3 V;
14.318
CIN
Logic Inputs
X1 & X2 pins
5
pF
pS
CINX
27
36
45
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
Ttrans
Ts
To 1st crossing of target Freq.
1.5
3
mS
mS
mS
nS
From1st crossing to 1% target Freq.
From VDD = 3.3 Vto 1% target Freq.
TSTAB
3
TCPU-BUS VT = 1.5 V;
1.0
2.2
4.0
1Guarenteed by design, not 100% tested in production.
11
ICS9148-26
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
10
TYP
MAX UNITS
1
Output Impedance
RDSP2A
VO = VDD*(0.5)
20
20
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN2A
VO = VDD*(0.5)
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
10
2
Ω
V
VOH2B
VOL2B
IOH2B
IOL2B
2.3
0.2
-41
37
0.4
-19
V
mA
mA
VOL = 0.7 V
19
1
Rise Time
Fall Time
tr2A
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.3
1.0
2.1
2.0
nS
nS
%
1
tf2 A
1
Duty Cycle
Skew (Window)
dt2A
45.0
51.0
55.0
1
tsk2A
VT = 1.25 V
120
10
250
pS
nS
nS
period(norm) VT = 1.25 V; 100MHz
9.75
9.75
10.25
10.35
period(spr) VT = 1.25 V; 100MHz
10
1
Jitter
tj1s2A
VT = 1.25 V
120
350
pS
1
tjabs2A
VT = 1.25 V
VT = 1.25 V
-250
100
150
+250
250
Dev run avg
pS
1Guarenteed by design, not 100% tested in production.
12
ICS9148-26
Electrical Characteristics - 24M, 48M, REF 1
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
20
MAX UNITS
1
Output Impedance
RDSP5
VO = VDD*(0.5)
60
W
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN5
VO = VDD*(0.5)
IOH = -14 mA
IOL = 6.0 mA
VOH = 2.0 V
VOL = 0.8 V
55
2.9
0.25
-42
18
100
W
V
VOH5
VOL5
IOH5
IOL5
2.4
10
0.4
-20
V
mA
mA
1
Rise Time
Fall Time
Duty Cycle
Jitter
tr5
VOL = 0.8 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.8 V
VT = 1.5 V
1.1
1.0
2.0
2.5
nS
nS
%
1
tf5
1
dt5
40.0
52.0
100
250
60.0
250
800
1
tj1s5
VT = 1.5 V
pS
pS
1
tjabs5
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
13
ICS9148-26
Electrical Characteristics - BUS
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
23
MAX UNITS
1
Output Impedance
RDSP1
VO = VDD*(0.5)
55
55
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VO = VDD*(0.5)
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
20
2.9
0.2
-58
52
Ω
V
VOH1
VOL1
IOH1
IOL1
2.4
0.4
-22
V
mA
mA
25
1
Rise Time
Fall Time
Duty Cycle
Skew
tr1
VOL = 0.8 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.8 V
VT = 1.5 V
1.5
1.4
50.0
80
2.0
2.5
nS
nS
%
1
tf1
1
dt1
45.0
55.0
250
150
500
1
tsk1
VT = 1.5 V
pS
pS
pS
1
Jitter
tj1s1
VT = 1.5 V
50
1
tjabs1
VT = 1.5 V
200
1Guarenteed by design, not 100% tested in production.
14
ICS9148-26
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD =VDDL 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
10
TYP MAX UNITS
1
Output Impedance
RDSP2A
VO = VDD*(0.5)
20
20
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN2A
VO = VDD*(0.5)
IOH = -28 mA
IOL = 19 mA
VOH = 2.0 V
VOL = 0.8 V
10
Ω
V
VOH2A
VOL2A
IOH2A
IOL2A
2.4
2.8
0.3
-72
50
0.4
-42
V
mA
mA
33
55
1
Rise Time
Fall Time
tr2A
VOL = 0.8 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.8 V
VT = 1.5 V
1.1
1.5
65
2.0
2.5
75
nS
nS
%
1
tf2 A
1
Duty Cycle
dt2A
1
Skew ( output to output )
Skew ( Bufferin to output )
tsk2A
VT = 1.5 V
200
5.5
600
7.0
pS
nS
1
tsk2A
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
15
ICS9148-26
GeneralLayoutPrecautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
3 Optional crystal load capacitors are
recommended.
CapacitorValues:
C1, C2 : Crystal load values determined by user
C3:100pFceramic
All unmarked capacitors are 0.01µF ceramic
16
ICS9148-26
SSOP Package
SYM BOL
COM MON DIM ENSIONS
VARIATIONS
D
N
M IN.
.095
.008
.088
.008
.005
NOM .
.101
.012
.090
.010
-
M AX.
.110
.016
.092
.0135
.010
M IN.
.620
NOM .
.625
M AX.
.630
A
A1
A2
B
AC
48
C
D
E
e
H
h
L
See Variations
.292
.296
0.025 BSC
.406
.013
.032
.299
.400
.010
.024
.410
.016
.040
N
See Variations
5°
0°
8°
X
.085
.093
.100
Ordering Information
ICS9148F-26
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
17
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