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ICS9148F-13 [ICSI]

Frequency Generator & Integrated Buffers for PENTIUMTM; 频率发生器和集成缓冲器对PENTIUMTM
ICS9148F-13
型号： ICS9148F-13
厂家： INTEGRATED CIRCUIT SOLUTION INC    INTEGRATED CIRCUIT SOLUTION INC
描述：

Frequency Generator & Integrated Buffers for PENTIUMTM
频率发生器和集成缓冲器对PENTIUMTM

晶体 外围集成电路 光电二极管 时钟
文件： 总7页 (文件大小：192K)
中文：  中文翻译
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Integrated  
Circuit  
Systems, Inc.  
ICS9148-13  
Frequency Generator & Integrated Buffers for PENTIUMTM  
General Description  
Features  
The ICS9148-13 generates all clocks required for high speed  
RISC or CISC microprocessor systems such as Intel Pentium  
and PentiumPro. An output enable is provided for testability.  
•
Generates twelve processor, six bus, two  
14.31818MHz, 24MHz and one 48MHz clock for  
USB support.  
•
Synchronous clocks skew matched to 250ps window  
on CPUs and 500ps window on BUSs  
Spread Spectrum is available to modulate the CPU and BUS  
PLL (leaving the REF, 24, 48 MHz operating normally). The  
SS_EN# pin enables the spreading when low. The SS_TYPE  
pin choses ±0.5% (nominally) center spread or +0, -2%  
(nominally) downspread modulation.  
•
•
•
CPU to BUS skew, 3.0 to 5.0ns (CPU Early)  
3.0V - 3.7V supply range  
48-pin SSOP package  
Pin Configuration  
High drive BUS outputs typically provide greater than 1V/ns  
slew rate into 30pF loads. CPU outputs typically provide  
better than 1V/ns slew rate into 20pF loads while maintaining  
50 ±  
5% duty cycle. The REF clock outputs typically provide  
better than 0.8/ns slew rates.  
Block Diagram  
48-Pin SSOP  
Functionality  
Output Enable  
CPU (1:12) in  
MHz  
BUS (1:6) in  
MHz  
FS2  
FS1  
FS0  
24  
48  
OE  
REF  
CPU BUS VCO OSC  
(MHz) (MHz)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
75  
100  
75  
37.5  
33.3  
30.0  
41.65  
25  
1
Runs Runs Runs Runs Runs Runs Runs  
83.3  
50  
Tri-  
Tri-  
Tri-  
Tri-  
Tri-  
0
Runs Runs  
60  
30  
state state state state state  
66.67  
55  
33.33  
27.5  
30K pullup resistor to VDD on OE, FS(0:2), SS_EN#, SS_TYPE  
Pentium is a trademark of Intel Corporation  
9148-13 Rev A 020398  
ICS reserves the right to make changes in the device data identified in this  
publication without further notice. ICS advises its customers to obtain the latest  
version of all device data to verify that any information being relied upon by the  
customer is current and accurate.  
ICS9148-13  
Pin Descriptions  
PIN NUMBER  
PIN NAME  
TYPE  
OUT  
DESCRIPTION  
14.318 MHz reference clock outputs.  
1, 2  
REF1, REF2  
GND  
3, 10, 18, 24,  
30, 35, 43, 44  
PWR  
Device Ground  
4
X1  
IN  
OUT  
PWR  
IN  
Crystal or external clock input.  
5
6
X2  
Crystal output. (for external reference clock leave unconnected)  
3.3V volt I/O power supply.  
VDD  
FS (0:2)  
7, 26, 27  
Frequency select inputs. See function list table. Has pull up resistors  
BUS clock outputs.  
11,12,13,14,16, 17 BUS (1:6)  
OUT  
IN  
19  
SS_EN#  
Spread Spectrum Enable. Low=enable.  
High=Spread Spectrum down spread.  
Low=Spread Spectrum center spread.  
20  
SS_TYPE  
IN  
15, 21, 28, 31, 32,  
40, 46, 48  
VDD  
PWR  
Core power supply. 3.3V  
22  
23  
24MHz  
48MHz  
OUT  
OUT  
24MHz clock output  
48MHz clock output.  
25  
N/C  
OE  
No connect  
Output Enable when this signal is Low all Bus Clocks, Fixed Clocks, CPU  
Clocks outputs placed in tristate mode (internally pulled up)  
29  
IN  
33, 34, 36, 37, 38,  
39, 41, 42, 45, 47, 8, CPU (1:12)  
9
CPU clocks outputs see functionality table for  
specifications  
frequency  
OUT  
Spread Spectrum Functionality  
Input Pin 19  
SS_EN#  
Input Pin 20  
SS_TYPE  
CPU, SDRAM  
and PCICLOCKS  
REF, IOAPIC  
24MHz  
48MHz  
Frequency modulated in  
spread spectrum mode  
+0.5%, -0.5% (nominally)  
0
14.318MHz  
24MHz  
48MHz  
0
1
Frequency modulated in  
spread spectrum mode  
+0%, -2.0% (nominally)  
1
14.318MHz  
14.318MHz  
24MHz  
24MHz  
48MHz  
48MHz  
Normal, Steady frequency  
mode  
X
VDD Pins: 48, REFs, XTALOSC  
VDD Pins: 6, CPU 1- 2  
VDD Pins: 28, CPU PLL CORE  
VDD Pins: 32, CPU 3-6  
VDD Pins: 15, BUS 1-6  
VDD Pins: 24, 48, Fix PLL  
VDD Pins: 40, CPU 7-10  
VDD Pins: 46, CPU 11-12  
2
ICS9148-13  
Absolute Maximum Ratings  
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V  
Logic Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V  
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C  
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are  
stress specifications only and functional operation of the device at these or any other conditions above those listed in the  
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods  
may affect product reliability.  
Electrical Characteristics - Input/Supply/Common Output Parameters  
TA = 0 - 70C; Supply Voltage VDD = 3.3 V+/-5% (unless otherwise stated)  
PARAMETER  
Input High Voltage  
Input Low Voltage  
Input High Current  
SYMBOL  
CONDITIONS  
MIN  
2
TYP  
MAX UNITS  
V
IH  
VDD+0.3  
V
V
V
IL  
VSS-0.3  
0.8  
200  
5
A
µ
IIH1  
IIH2  
IIL1  
IIL2  
IDD  
Fi  
V = VDD; SS_Type only  
68.0  
0.2  
IN  
A
µ
V = VDD; All outputs Except SS_Type  
-5  
-5  
IN  
VIN = 0 V;with pull-down resistors SS_Type only  
VIN = 0 V;with pull-up resistors except SS_Type  
CL = 0 pF; Select @ 66M  
A
µ
Input Low Current  
0.2  
5
A
µ
-200  
-100  
67  
Supply Current  
Input frequency  
Input Capacitance1  
180  
mA  
VDD = 3.3 V;  
14.318  
MHz  
CIN  
Logic Inputs  
X1 & X2 pins  
5
pF  
pF  
CINX  
27  
36  
45  
Transition Time1  
Clk Stabilization1  
Skew1  
Ttrans  
To 1st crossing of target Freq.  
1.5  
3
3
ms  
ms  
ns  
TSTAB  
From VDD = 3.3 Vto 1% target Freq.  
TCPU-BUS VT = 1.5 V;  
3.0  
4.0  
5.0  
1Guarenteed by design, not 100% tested in production.  
3
ICS9148-13  
Electrical Characteristics - CPU  
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
10  
TYP  
MAX UNITS  
1
Output Impedance  
RDSP2A  
VO = VDD*(0.5)  
20  
20  
Ω
1
Output Impedance  
Output High Voltage  
Output Low Voltage  
Output High Current  
Output Low Current  
RDSN2A  
VO = VDD*(0.5)  
IOH = -28 mA  
IOL = 27 mA  
VOH = 2.0 V  
VOL = 0.8 V  
10  
Ω
V
VOH2A  
VOL2A  
IOH2A  
IOL2A  
2.4  
2.5  
0.35  
-52  
59  
0.4  
-48  
V
mA  
mA  
49.3  
45  
1
Rise Time  
Fall Time  
Duty Cycle  
Skew  
tr2A  
VOL = 0.8 V, VOH = 2.4 V  
VOH = 2.4 V, VOL = 0.8 V  
VT = 1.5 V  
1.5  
1.3  
51  
2.5  
2
ns  
ns  
%
ps  
ps  
ps  
ps  
1
tf2 A  
1
dt2A  
55  
1
tsk2A  
VT = 1.5 V  
120  
60  
250  
150  
+250  
-300  
1
Jitter  
tj1s2A  
VT = 1.5 V  
1
tjabs2A  
VT = 1.5 V; For 66.66 MHz and lower  
VT = 1.5 V; For 75 MHz and Higher  
-250  
-300  
100  
150  
1
tjabs2A  
1Guarenteed by design, not 100% tested in production.  
Electrical Characteristics - 24M, 48M, REF(1:2)  
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
20  
TYP MAX UNITS  
1
Output Impedance  
RDSP5  
VO = VDD*(0.5)  
60  
60  
Ω
1
Output Impedance  
Output High Voltage  
Output Low Voltage  
Output High Current  
Output Low Current  
RDSN5  
VO = VDD*(0.5)  
IOH = -8 mA  
IOL = 9 mA  
20  
Ω
V
VOH5  
VOL5  
IOH5  
IOL5  
2.6  
2.9  
0.3  
-32  
25  
0.4  
-22  
V
VOH = 2.0 V  
VOL = 0.8 V  
mA  
mA  
16  
1
Rise Time  
Fall Time  
Duty Cycle  
Jitter  
tr5  
VOL = 0.8 V, VOH = 2.4 V  
VOH = 2.4 V, VOL = 0.8 V  
VT = 1.5 V  
2.0  
1.8  
53  
2.5  
2.3  
60  
ns  
ns  
%
ps  
ps  
1
tf5  
1
dt5  
40  
1
tj1s5  
VT = 1.5 V  
200  
500  
300  
700  
1
tjabs5  
VT = 1.5 V  
-700  
1Guarenteed by design, not 100% tested in production.  
4
ICS9148-13  
Electrical Characteristics - BUS  
TA = 0 - 70C; VDD = 3.3 V+/-5%; CL = 30 pF (unless otherwise stated)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
12  
TYP MAX UNITS  
1
Output Impedance  
RDSP1  
VO = VDD*(0.5)  
55  
55  
Ω
1
Output Impedance  
Output High Voltage  
Output Low Voltage  
Output High Current  
Output Low Current  
RDSN1  
VO = VDD*(0.5)  
IOH = -11 mA  
IOL = 9.4 mA  
VOH = 2.0 V  
VOL = 0.8 V  
12  
Ω
V
VOH1  
VOL1  
IOH1  
IOL1  
2.4  
3
0.2  
-60  
46  
0.4  
-22  
V
mA  
mA  
16  
45  
1
Rise Time  
Fall Time  
Duty Cycle  
Skew  
tr1  
VOL = 0.8 V, VOH = 2.4 V  
VOH = 2.4 V, VOL = 0.8 V  
VT = 1.5 V  
1.7  
1.5  
51  
2
ns  
ns  
%
ps  
ps  
ps  
1
tf1  
2
1
dt1  
55  
1
tsk1  
VT = 1.5 V  
200  
30  
500  
150  
250  
1
Jitter  
tj1s1  
VT = 1.5 V  
1
tjabs1  
VT = 1.5 V  
-250  
110  
1Guarenteed by design, not 100% tested in production.  
5
ICS9148-13  
GeneralLayoutPrecautions:  
1) Use a ground plane on the top layer  
of the PCB in all areas not used by  
traces.  
2) Make all power traces and vias as  
wide as possible to lower inductance.  
Notes:  
1 All clock outputs should have series  
terminating resistor. Not shown in all  
places to improve readibility of  
diagram  
2 Optional EMI capacitor should be  
used on all CPU, SDRAM, and PCI  
outputs.  
3. Optional crystal load capacitors are  
recommended  
CapacitorValues:  
C1, C2: Crystal load values determined by user.  
All unmarked capacitors are 0.01µF ceramic  
6
ICS9148-13  
SSOP Package  
SYMBOL  
COMMON DIMENSIONS  
VARIATIONS  
D
N
MIN.  
.095  
.008  
.088  
.008  
.005  
NOM.  
.101  
.012  
.090  
.010  
MAX.  
.110  
.016  
.092  
.0135  
.010  
MIN.  
.620  
NOM. MAX.  
.625 .630  
A
A1  
A2  
B
AC  
48  
C
-
D
E
See Variations  
.296  
.292  
.299  
e
H
h
0.025 BSC  
.406  
.013  
.400  
.010  
.024  
.410  
.016  
.040  
L
.032  
N
See Variations  
0°  
5°  
8°  
X
.085  
.093  
.100  
This table in inches  
Ordering Information  
ICS9148F-13  
Example:  
ICS XXXX F - PPP  
Pattern Number (2 or 3 digit number for parts with ROM code patterns)  
Package Type  
F=SSOP  
Device Type (consists of 3 or 4 digit numbers)  
Prefix  
ICS, AV = Standard Device  
ICS reserves the right to make changes in the device data identified in this  
publication without further notice. ICS advises its customers to obtain the latest  
version of all device data to verify that any information being relied upon by the  
customer is current and accurate.  
7

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