ICS9148F-37 [ICSI]
Frequency Generator & Integrated Buffers for PENTIUM/ProTM; 频率发生器和缓冲器集成奔腾/ ProTM
| 型号： | ICS9148F-37 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| 文件： | 总14页 (文件大小：650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9148-93
Integrated
Circuit
Systems, Inc.
Advance Information
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-93 is the single chip clock solution for Desktop/
Notebook designs using the VIA MVP3 style chipset. It
provides all necessary clock signals for such a system.
Features
Generates the following system clocks:
-4CPU(2.5V/3.3V)upto100MHz.
-6PCI(3.3V)@ 33.3MHz
-2AGP(3.3V)@2x PCI
-12SDRAMs(3.3V)@eitherCPUorAGP
-2REF(3.3V)@14.318MHz
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-93
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Skew characteristics:
-CPUCPU<250ps
- SDRAM SDRAM < 250ps
- CPU SDRAM < 250ps
- CPU(early) PCI : 1-4ns
Supports Spread Spectrum modulation +0.25, ±0.6%
Serial I2C interface for Power Management, Frequency
Select, Spread Spectrum.
Serial programming I2C interface allows changing functions,
stopclockprogrammingandfrequencyselection. TheSD_SEL
latched input allows the SDRAM frequency to follow the
CPUCLK frequency(SD_SEL=1) or the AGP clock
frequency(SD_SEL=0).
Efficient Power management scheme through PCI and CPU
STOPCLOCKS.
Uses external 14.318MHz crystal
48pin300milSSOP.
Block Diagram
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
VDD4=AGP(0:1)
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
VDDL=CPUCLK(0:3)
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
9148-93 Rev - 1/22/99
ICS9148-93
Advance Information
Pin Descriptions
PIN NUMBER
PIN NAME
VDD1
REF0
TYPE
PWR
OUT
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V
1
2
CPU3.3#_2.51,2
IN
PWR
IN
CPU1. Latched input2
3,9,16,22,27,
33,39,45
GND
X1
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
4
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew
(CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determines the
CPU, SDRAM, PCI & AGP frequencies.
PCI clock output. Synchronous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input Along with other FS pins determines the
CPU, SDRAM, PCI & AGP frequencies.
5
X2
OUT
PWR
OUT
6,14
VDD2
PCICLK_F
7
FS11, 2
IN
OUT
IN
PCICLK0
FS21, 2
8
10, 11, 12, 13
15, 47
PCICLK(1:4)
AGP (0:1)
OUT
OUT
PCI clock outputs. Synchronous CPUCLKs with 1-4ns skew (CPU early)
Advanced Graphic Port outputs, powered by VDD4.
This asynchronous input halts CPUCLK (0:3) and AGP (0:1) clocks at logic 0
level, when input low (in Mobile Mode, MODE=0)
CPU_STOP#1
SDRAM 11
PCI_STOP#1
SDRAM 10
IN
OUT
IN
17
18
SDRAM clock output. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frequency
SD_SEL = 0 at power on causes SDRAM frequency = AGP frequency
This asynchronous input halts PCICLK(0:5) clocks at logic 0 level, when
input low (In mobile mode, MODE=0)
SDRAM clock output. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquency
SD_SEL = 0 at power on causes SDRAM frequency = AGP frequency
SDRAM clock outputs. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frequency
SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequency
Supply for SDRAM (0:11), CPU Core and 24, 48MHz clocks,
nominal 3.3V.
OUT
20, 21,28, 29, 31,
32, 34, 35,37,38
SDRAM (0:9)
VDD3
OUT
PWR
19,30,36
23
24
SDATA
SCLK
IN
IN
Data input for I2C serial input.
Clock input of I2C input
24MHz
OUT
24MHz output clock, for Super I/O timing.
25
26
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock, for USB timing.
Frequency select pin. Latched Input Along with other FS pins determines the
CPU, SDRAM, PCI & AGP frequencies.
MODE1, 2
48MHz
FS01, 2
IN
OUT
IN
40, 41, 43, 44
42
CPUCLK(0:3)
VDDL
REF1
OUT
PWR
OUT
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Supply for CPU (0:3), either 2.5V or 3.3V nominal
14.318MHz reference clock.
46
48
Latched input at Power On selects either CPU (SDSEL=1) or AGP
(SD_SEL=0) frequencies for the SDRAM clock outputs.
Supply for AGP (0:1)
SD_SEL
VDD4
IN
PWR
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2
ICS9148-93
Advance Information
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
Pin 17
Pin 18
CPU_STOP#
(INPUT)
PCI_STOP#
(INPUT)
0
SDRAM 11
(OUTPUT)
SDRAM 10
(OUTPUT)
1
Power Management Functionality
PCICLK_F,
REF,
24/48MHz
and SDRAM
AGP,
CPUCLK
Outputs
PCICLK
(0:5)
Crystal
OSC
CPU_STOP# PCI_STOP#
VCO
0
1
1
1
1
0
Stopped Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Buffer Selected for
Input level
operation at:
(Latched Data)
1
0
2.5V VDD
3.3V VDD
Functionality
VDD1, 2, 3, 4=3.3V±5%,VDDL = 2.5V±5% or 3.3 ±5%, TA= 0 to 70°C
Crystal (X1, X2) = 14.31818MHz
CPU (MHz)
SDRAM (MHz)
FS2
FS1
FS0
PCI (MHz)
AGP (MHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
90.00
66.82
68.49
75.00
75.00
83.31
95.25
100.00
30.00
33.41
34.25
37.5
30.00
33.32
31.75
33.33
60.00
66.82
68.49
75.00
60.00
66.64
63.50
66.66
3
ICS9148-93
Advance Information
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C
programming application note.
How to Write:
Send the address D2(H) .
Send two additional dummy bytes, a command code
and byte count.
Send the desired number of data bytes.
See the diagram below:
Clock Generator
Address (7 bits)
+ 8 bits
dummy
command code
+ 8 bits
dummy Byte
count
Data Byte
1
Data Byte
N
ACK
ACK
ACK
ACK
ACK
A(6:0) & R/W#
D2(H)
Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must
be sent.
How to Read:
Send the address D3(H).
Send the byte count in binary coded decimal
Read back the desired number of data bytes
See the diagram below:
Clock Generator
Address (7 bits)
Byte
Count
Data Byte
1
Data Byte
N
ACK
ACK
ACK
A(6:0) & R/W#
D3(H)
The following specifications should be observed:
1. Operating voltage for I2C pins is 3.3V
2. Maximum data transfer rate (SCLK) is 100K bits/sec.
Serial Configuration Command Bitmap
Byte0:FunctionalityandFrequencySelectRegister
(default=0)
Bit
Description
0 - ±0.25% Spread Spectrum Modulation
1 - ±0.6% Spread Spectrum Modulation
PWD
0
Bit 7
Bit (6:4)
CPU
SDRAM
(MHz)
PCI
(MHz)
AGP
(MHz)
Note 1. Default at Power-up will be for latched logic inputs,
000
001
010
011
100
101
110
111
90.00
66.82
68.49
75.00
75.00
83.31
95.25
100.00
30.00
33.41
34.25
37.50
30.00
33.32
31.75
33.33
60.00
66.82
68.49
75.00
60.00
66.64
63.50
66.66
as defined by Bit 3.
Bit
6:4
XXX
Note 1
0 - Frequency is selected by hardware select,
Bit 3
FS(0:2) pins only
0
I2C is a trademark of Philips Corporation
1 - Select frequencies by I2C
0 - Center Spread
1 - Down Spread
0
0
0
0 - Normal operation
Bit 1
Bit 0
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
4
ICS9148-93
Advance Information
Byte 1: CPU,Active/Inactive Register
(1 = enable, 0 = disable)
Byte2:PCIActive/InactiveRegister
(1 = enable, 0 = disable)
Bit
Pin # PWD
Description
(Reserved)
PCICLK_F (Act/Inact)
AGP0 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Bit
Pin #
-
-
-
-
40
41
43
44
PWD
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
7
15
13
12
11
10
8
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: SDRAMActive/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
28
29
31
32
34
35
37
38
PWD
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Bit
Pin #
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
-
-
-
-
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 3
Bit 2
17
18
1
1
Bit 1
Bit 0
20
21
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte5:Peripheral Active/InactiveRegister
(1 = enable, 0 = disable)
Bit
Pin #
-
-
-
47
-
-
46
2
PWD
Description
(Reserved)
(Reserved)
(Reserved)
AGP1(Act/Inact)
(Reserved)
(Reserved)
REF1 (Act/Inact)
REF0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
5
ICS9148-93
Advance Information
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-93. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-93.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
6
ICS9148-93
Advance Information
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-93. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by theICS9148-93 internally.The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
7
ICS9148-93
Advance Information
Shared Pin Operation -
Input/Output Pins
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
Pins 2, 7, 8, 25, 26 and 46 on the ICS9148-93 serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 4-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
8
ICS9148-93
Advance Information
Fig. 2a
Fig. 2b
9
ICS9148-93
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
VIL
VSS-0.3
V
IIH
VIN = VDD
0.1
2.0
5
mA
mA
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
-100
100
IDD3.3OP CL = 0 pF; 66.8 MHz
160
Supply Current
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
14.318
36
MHz
pF
pF
ms
ms
ms
ps
CIN
Logic Inputs
5
45
2
CINX
Ttrans
Ts
X1 & X2 pins
27
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
TSTAB
2
500
4
TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads
TCPU-PCI1 VT = 1.5 V; CPU Leads
-500
1
200
2.8
ns
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
CL = 0 pF; 66.8 MHz
MIN
TYP
10
MAX
20
UNITS
mA
Operating
IDD2.5OP
Supply Current
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
-500
1
200
2.7
500
4
ps
ns
Skew1
1Guaranteed by design, not 100% tested in production.
10
ICS9148-93
Advance Information
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage VOH2B IOH = -8 mA
Output Low Voltage VOL2B OL = 12 mA
SYMBOL
CONDITIONS
MIN
2
TYP
2.2
0.3
-20
26
MAX
UNITS
V
I
0.4
-16
V
Output High Current IOH2B VOH = 1.7 V
Output Low Current IOL2B VOL = 0.7 V
mA
mA
ns
19
40
tr2B1
Rise Time
Fall Time
VOL = 0.4 V, VOH = 2.0 V
1.5
1.6
47
1.8
1.8
55
tf2B1
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
ns
dt2B1
tsk2B1
Duty Cycle
%
Skew
VT = 1.25 V
60
250
ps
Jitter, Single Edge
Displacement2
Jitter, One Sigma
Jitter, Absolute
tjsed2B1
VT = 1.25 V
200
250
ps
tj1s2B1
tjabs2B1
VT = 1.25 V
VT = 1.25 V
65
150
300
ps
ps
-300
160
1 Guaranteed by design, not 100% tested in production.
2 Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
2.5
TYP
2.6
0.35
-29
37
MAX
UNITS
V
VOH2A IOH = -28 mA
VOL2A IOL = 27 mA
IOH2A VOH = 2.0 V
0.4
-23
V
mA
mA
ns
IOL2A VOL = 0.8 V
33
45
1
tr2A
VOL = 0.4 V, VOH = 2.4 V
1.75
1.1
50
2
1
Fall Time
tf2A
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
ns
1
Duty Cycle
dt2A
55
%
1
Skew
tsk2A
VT = 1.5 V
50
250
150
250
ps
1
Jitter, One Sigma
tj1s2A
VT = 1.5 V
65
ps
1
tjabs2A VT = 1.5 V
Jitter, Absolute
-250
165
ps
1Guaranteed by design, not 100% tested in production.
11
ICS9148-93
Advance Information
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
3
MAX
UNITS
V
IOL = 23 mA
0.2
-60
50
0.4
-40
V
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
41
45
Tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.75
1.5
50
2
2
Fall Time1
Duty Cycle1
Tf1
ns
Dt1
55
%
Skew1
Tsk1
VT = 1.5 V
200
50
500
150
+250
400
ps
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Absolute1
Tj1s1
Tjabs1
Tjabs1
VT = 1.5 V
ps
VT = 1.5 V (with synchronous PCI)
VT = 1.5 V (with asynchronous PCI)
-250
-400
ps
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
3
MAX
UNITS
V
V
VOL1
IOL = 23 mA
0.2
-60
50
0.4
-40
IOH1
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
41
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.8
1.6
51
2
2
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
55
250
%
1
Skew
tsk1
VT = 1.5 V
130
ps
Jitter, One Sigma1
Jitter, Absolute1
tj1s1a
tj1s1b
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
40
150
250
ps
ps
200
tabs1a VT = 1.5 V, synchronous
tjabs1b VT = 1.5 V, asynchronous
1Guaranteed by design, not 100% tested in production.
-250
-650
135
500
250
650
ps
ps
12
ICS9148-93
Advance Information
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
3
MAX
UNITS
V
VOL1
IOL = 23 mA
0.2
-60
50
1.1
1
0.4
-40
V
IOH1
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
41
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.4 V
2
2
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
49
130
2
55
250
3
%
1
Skew
tsk1
VT = 1.5 V
ps
Jitter, One Sigma1
Jitter, Absolute1
tj1s1
tabs1a
tjabs1b
VT = 1.5 V
%
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
-5
-6
2.5
4.5
5
%
6
%
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz, REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH5
CONDITIONS
IOH = -16 mA
MIN
2.4
TYP
MAX
UNITS
2.6
0.3
-32
25
2
V
V
VOL5
IOL = 9 mA
0.4
-22
IOH5
VOH = 2.0 V
mA
mA
ns
IOL5
VOL = 0.8 V
16
1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4
4
1
Fall Time
tf5
1.9
54
1
ns
1
Duty Cycle
dt5
45
-5
57
3
%
1
Jitter, One Sigma
tj1s5
VT = 1.5 V
%
1
tjabs5
VT = 1.5 V
Jitter, Absolute
-
5
%
1Guaranteed by design, not 100% tested in production.
13
ICS9148-93
Advance Information
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
MIN. NOM. MAX.
A
A1
A2
B
AC
.620
.625
.630
48
C
D
E
See Variations
.296
.292
.299
e
H
h
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
L
.032
N
See Variations
0°
5°
8°
X
.085
.093
.100
Ordering Information
ICS9148F-37
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
14
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