ICS9148F-32 [ICSI]
Pentium/ProTM System Clock Chip; 奔腾/ ProTM系统时钟芯片
| 型号： | ICS9148F-32 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Pentium/ProTM System Clock Chip |
| 文件： | 总14页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9148-32
TM
Pentium/Pro System Clock Chip
General Description
Features
Generates system clocks for CPU, IOAPIC, PCI,
The ICS9148-32 is a Clock Synthesizer chip for Pentium and
PentiumPro CPU based Desktop/Notebook systems that will
provide all necessary clock timing.
14.314MHzREF, USB, andSuperI/O
Supports single or dual processor systems
I2C interface
Features include four CPU and eight PCI clocks. Three
reference outputs are available equal to the crystal frequency.
Additionally, the device meets the Pentium power-up
stabilization requirement, assuring that CPU and PCI clocks
are stable within 2ms after power-up.
Supports Spread Spectrum modulation for CPU & PCI
clocks, ±0.255% Center Spread or 0 to -0.6% Down
Spread.
Skew from CPU (earlier) to PCI clock 1 to 4ns
CPU cycle to cycle jitter ±200ps
2.5Vor3.3Voutput:CPU, IOAPIC
3.3Voutputs:PCI, REF, 48MHz
No power supply sequence requirements
PD# pin enables low power mode by stopping crystal OSC
and PLL stages. Other power management features include
CPU_STOP#, whichstopsCPU(0:3)clocks, andPCI_STOP#,
which stops PCICLK (0:6) clocks.
Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal
48pin300milSSOP
Serial I2C interface allows power management by output clock
disabling.
High drive CPUCLK outputs typically provide greater than 1
V/ns slew rate into 20pF loads. PCICLK outputs typically
provide better than 1V/ns slew rate into 30pF loads while
maintaining50±5%dutycycle. TheREFclockoutputstypically
provide better than 0.5V/ns slew rates.
Pin Configuration
The ICS9148-32 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Block Diagram
48-Pin SSOP
Power Groups
VDD = Supply for PLL core
VDD1=REF(0:2),X1,X2
VDD2=PCICLK_F,PCICLK(0:6)
VDD3=48MHz,24/48MHz#
VDDL1=IOAPIC(0:1)
VDDL2=CPUCLK(0:3)
Ground Groups
GND = Ground for PLL core
GND1=REF(0:2),X1,X2
GND2=PCICLK_F,PCICLK(0:6)
GND3=48MHz,24/48MHz#
GNDL1=IOAPIC(0:1)
GNDL2=CPUCLK(0:3)
PentiumisatrademarkonIntelCorporation.
9148-32RevB09/09/98
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9148-32
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
14.318MHz clock output / Latched input at power up. When
low, pin 23 is 48MHz.
1
REF0/SEL48#
OUT/IN
2, 47
3
REF (1:2)
GND1
OUT
PWR
14.318MHz clock output
Ground for REF outputs
XTAL_IN 14.318MHz Crystal input, has internal 33pF load
cap and feed back resistor from X2
4
X1
IN
5
X2
GND2
PCICLK_F
PCICLK (0:6)
VDD2
OUT
PWR
OUT
OUT
PWR
PWR
PWR
PWR
OUT
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Isolated power for core, nominally 3.3V
Isolated ground for core
Power for 48MHz outputs, nominally 3.3V
48MHz output
6, 12, 18
7
8, 10, 11, 13, 14, 16, 17
9, 15
19, 33
20, 32
21
VDD
GND
VDD3
48MHz
22
Fixed clock output. 24MHz if pin1=1 at power up
48MHz if pin 1=0 at power up
Ground for 48MHz outputs
23
24
25
24/48MHz#
GND3
OUT
PWR
IN
Select pin for enabling 100MHz or 66.6MHz
SEL100/66.6#
H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz)
26
SCLK
SDATA
SPREAD#
PD#
CPU_STOP#
PCI_STOP#
VDDL2
GNDL2
CPUCLK (3:0)
N/C
IN
IN
IN
IN
IN
Clock input for I2C input
27
281
Data input for I2C input
Enables Spread Spectrum feature when LOW
Powers down chip, active low
Halts CPU clocks at logic "0" level when low
Halts PCI Bus at logic "0" level when low
Power for CPU outputs, nominally 2.5V
Ground for CPU outputs.
291
301
311
IN
37, 41
34, 38
35, 36, 39, 40
42
PWR
PWR
OUT
-
CPU and Host clock outputs, nominally 2.5V
Not internally connected
43
44, 45
46
GNDL1
IOAPIC (0:1)
VDDL1
PWR
OUT
PWR
Ground for IOAPIC outputs
IOAPIC outputs (14.318MHz) nominally 2.5V
Power for IOAPIC outputs, nominally 2.5V
Select Functions
PCI,
PCI_F
48 MHz
IOAPIC
Functionality
CPU
REF
Selection
Tristate
Testmode
HI - Z
TCLK/21
HI - Z
TCLK/61
HI - Z
TCLK1
HI - Z
TCLK1
HI - Z
TCLK/21
Spread Spectrum
Modulated2 Modulated2 14.318MHz 14.318MHz
48.0MHz
2
ICS9148-32
Technical Pin Function Descriptions
VDD, VDD(1,2,3)
48MHz
This is the power supply to the internal core logic of the
device as well as the clock output buffers for REF(0:2),
PCICLK_F, PCICLK(0:6),48MHz0,48MHz1.
This is a fixed frequency Clock output that is typically used
to drive USB devices.
24/48MHz
This pin operates at 3.3V volts. Clocks from the listed buffers
that it supplies will have a voltage swing from Ground to this
level. For the actual guaranteed high and low voltage levels
for the Clocks, please consult the DC parameter table in this
data sheet.
Fixed frequency clock output. 24MHz output if Pin1=1 at
power up. 48MHz if pin1=0 at power up.
IOAPIC(0:1)
This Output is a fixed frequency Output Clock that runs at
the Reference Input (typically 14.31818MHz) . Its voltage
level swing is controlled by VDDL1 and may operate at 2.5 or
3.3volts.
VDDL(1,2)
This is the power supply for the CPUCLK (0:3) and IOAPIC
output buffers. The voltage level for these outputs may be
2.5 or 3.3volts. Clocks from the buffers that each supplies will
have a voltage swing from Ground to this level. For the actual
Guaranteed high and low voltage levels of these Clocks,
please consult the DC parameter table in this Data Sheet.
REF0/SEL48#
This is an input pin during power up only. During power up if
high, then pin 23 is a 24MHz fixed clock during normal
operation. If Low during power up, pin 23 is a 48MHz fixed
clockduringnormaloperation. Duringnormaloperation, REF0
is an output which is a fixed frequency running at 14.318MHz.
GND,GND(1,2,3)
This is the ground to the internal core logic of the device as
well as the clock output buffers for REF(0:2), PCICLK_F,
PCICLK(0:6),48MHz0,48MHz1.
REF(1:2)
The REF Outputs are fixed frequency Clocks that run at the
same frequency as the Input Reference Clock X1 or the
Crystal (typically 14.31818MHz) attached across X1 and X2.
GNDL(1,2)
This is the ground for the CPUCLK (0:3) and IOAPIC output
buffers.
PCICLK_F
ThisOutputisequaltoPCICLK(0:6)andisFREERUNNING,
and will not be stopped by PCI_STOP#.
X1
This input pin serves one of two functions. When the device
is used with a Crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal. When
the device is driven by an external clock signal, X1 is the
device input pin for that reference clock. This pin also
implements an internal Crystal loading capacitor that is
connected to ground. With a nominal value of 33pF no
external load cap is needed for a CL=17 to 18pF crystal.
PCICLK(0:6)
These Output Clocks generate all the PCI timing requirements
for a Pentium/Pro based system. They conform to the current
PCI specification. They run at 33.3 MHz.
SEL 100/66.6#
This Input pin controls the frequency of the Clocks at the
CPUCLK, PCICLK and SDRAM output pins. If a logic 1
valueispresentonthispin, the100MHzClockwillbeselected.
If a logic 0 is used, the 66.6MHz frequency will be selected.
The PCI clock is multiplexed to be 33.3MHz for both select
cases. PCI is synchronous at the rising edge of PCI to the
CPU rising edge (with the skew making CPU early).
X2
This Output pin is used only when the device uses a Crystal
as the reference frequency source. In this mode of operation,
X2 is an output signal that drives (or excites) the discrete
Crystal. The X2 pin will also implement an internal Crystal
loading capacitor nominally 33pF.
CPUCLK(0:3)
These Output pins are the Clock Outputs that drive processor
and other CPU related circuitry that requires clocks which are
in tight skew tolerance with the CPU clock. The voltage
swing of these Clocks is controlled by the Voltage level
applied to the VDDL2 pin of the device. See the Functionality
Table for a list of the specific frequencies that are available
for these Clocks and the selection codes to produce them.
3
ICS9148-32
Technical Pin Function Descriptions
PWR_DWN#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all
the Outputs in a low state at the end of their current cycle.
The latency of Power Down will not be greater than 3ms.
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks
including SDRAM clocks will continue to run while this
function is enabled. The CPUCLKs will have a turn ON
latency of at least 3 CPU clocks. This input pin is valid only
when MODE=0 (Power Management Mode)
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK clocks in an active low state. It will not affect
PCICLK_F nor any other outputs. This input pin is valid only
when MODE=0 (Power Management Mode)
4
ICS9148-32
Power Management
ClockEnableConfiguration
Other Clocks,
REF,
CPU_STOP# PCI_STOP# PWR_DWN#
CPUCLK
PCICLK
IOAPICs,
48 MHz 0
48 MHz 1
Crystal
VCOs
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
Low
Stopped
Running
Running
Running
Running
Off
Off
Running
Running
Running
Running
Running
Running
Running
Running
Low
33.3 MHz
Low
100/66.6MHz
100/66.6MHz
33.3 MHz
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up
and power down operations using the PD# select pin will not cause clocks of a shorter or longer pulse than that of the running
clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging
circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9148-32PowerManagementRequirements
Latency
No. of rising edges of free
running PCICLK
SIGNAL
SIGNAL STATE
CPU_ STOP#
0 (Disabled)2
1 (Enabled)1
1
1
1
PCI_STOP#
PD#
0 (Disabled)2
1 (Enabled)1
1
1 (Normal Operation)3
0 (Power Down)4
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF and IOAPIC will be stopped independent of these.
5
ICS9148-32
Serial Bitmap
Byte3:Functionality&FrequencySelect
& Sperad Select Register
Bit
Description
PWD
0: Center Spread ±0.255%
1: Down Spread 0 to -0.6%
7
0
SEL 100/66.6#
CPU
MHz
68.5
75
83.3
66.6
103
112
133.3
100
PCI
MHz
34.25
37.5
41.6
33.3
34.3
37.3
44.43
33.3
Bits 5 4
or Bit 6
0
0
0
0
1
1
1
1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
6:4
000
0 - Frequency is selected by hardware select
SEL100166.6#
1 - Frequency is selected by 6:4 above
(Reserved)
3
2
0
00 - Normal operation
01 - Test mode
10 - Spread sprectrum ON
11 - Tristate all outputs
10
00
Byte4:
Description
Bit Value = 0 Bit Value = 1
Bit Pin# Pin Name PWD
7
6
5
4
-
-
-
-
-
-
-
-
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Disabled
(low)
Disabled
(low)
Disabled
(low)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
3
2
1
0
35
36
39
40
CPUCLK3
CPUCLK2
CPUCLK1
CPUCLK0
1
1
1
1
Enabled
Enabled
Enabled
Enabled
(Disabled)
(low)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
6
ICS9148-32
Byte5:
Description
Bit Value = 0 Bit Value = 1
Bit Pin# Pin Name PWD
Disabled
Enabled
(low)
Disabled
Enabled
(low)
Disabled
Enabled
(low)
Disabled
Enabled
(low)
Disabled
Enabled
(low)
Disabled
Enabled
(low)
Disabled
Enabled
(low)
Disabled
Enabled
(low)
7
6
5
4
3
2
1
0
7
PCICLK_F
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
1
1
1
1
1
1
1
1
14
16
14
13
11
6
5
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte6:
Description
Bit Value = 0 Bit Value = 1
Bit Pin# Pin Name PWD
7
6
-
-
-
-
0
0
(Reserved)
(Reserved)
Disabled
(low)
(Reserved)
(Reserved)
5
44
IOAPIC1
1
Enabled
Disabled
(low)
(Reserved)
Disabled
(low)
4
3
2
45
-
IOAPIC1
0
0
0
Enabled
(Reserved)
Enabled
-
47
REF2
(Disabled)
(low)
(Disabled)
(low)
1
0
2
1
REF1
REF0
1
1
Enabled
Enabled
Notes: 1 = Enabled; 0 = Disabled, outputs held low
7
ICS9148-32
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9148-32. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs.All other clocks will continue to run while the CPUCLKs are disabled.The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9148-32.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-32. It is used to turn off the PCICLK (0:6) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-32 internally.The minimum that the PCICLK (0:6) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:6) clocks. PCICLK (0:6) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:6) clock on latency cycles are only one rising PCICLK. Clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148-32.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
8
ICS9148-32
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9148-32 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on
latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are dont care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
9
ICS9148-32
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
IIH
VIN = VDD
0.1
2.0
-100
60
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
A
µ
IIL2
-200
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
170
170
650
mA
Supply Current
Power Down
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
66
A
µ
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
3
Supply Current
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
14.318
36
MHz
pF
CIN
Logic Inputs
5
45
3
CINX
Ttrans
Ts
X1 & X2 pins
27
1
pF
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
ns
5
TSTAB
3
4
TAGP-PCI1 VT = 1.5 V;
3.5
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V+/-5% (unless otherwise stated)
PARAMETER
SYMBOL
IDD2.5OP66
CONDITIONS
MIN
TYP
16
MAX UNITS
Operating
Supply Current
Power Down Supply
Current
CL = 0 pF; Select @ 66.8 MHz
72
mA
mA
IDD2.5OP100 CL = 0 pF; Select @ 100 MHz
23
100
CL = 0 pF; With input address to
IDD2.5PD
10
100
A
µ
Vdd or GND
tCPU-AGP
0
1
0.5
2.6
1
4
ns
ns
Skew1
tCPU-PCI2
VT = 1.5 V; VTL = 1.25 V
1Guaranteed by design, not 100% tested in production.
10
ICS9148-32
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP MAX UNITS
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
2.3
0.2
-41
37
V
V
0.4
-19
mA
mA
ns
IOL2B
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.25
1
1.6
1.6
1
Fall Time
tf2B
ns
%
1
Duty Cycle
dt2B
48
55
1
Skew
tsk2B
VT = 1.25 V
30
175
250
150
+250
ps
ps
ps
ps
1
Jitter, Cycle-to-cycle tjcyc-cyc2B VT = 1.25 V
150
40
1
Jitter, One Sigma
tj1s2B
VT = 1.25 V
VT = 1.25 V
1
tjabs2B
Jitter, Absolute
-250
140
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF
PARAMETER
SYMBOL
VOH4B
VOL4B
IOH4B
CONDITIONS
MIN
2
TYP
2.2
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -18 mA
IOL = 18 mA
VOH = 1.7 V
VOL = 0.7 V
0.33
-41
37
0.4
-28
V
mA
mA
IOL4B
29
45
-5
Rise Time1
Fall Time1
Duty Cycle1
Tr4B
Tf4 B
Dt4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.3
1.1
54
60
1
1.6
1.6
55
250
3
ns
ns
%
ps
%
%
Skew1
Jitter, One Sigma1
Jitter, Absolute1
1
tsk4B
VT = 1.25 V
Tj1s4B
VT = 1.25 V
Tjabs4B
VT = 1.25 V
5
1Guaranteed by design, not 100% tested in production.
11
ICS9148-32
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.1
0.1
-62
57
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-22
V
IOH1
mA
mA
IOL1
16
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.1
50
2
ns
ns
%
ps
ps
ps
2
dt1
55
tsk1
tj1s1
tjabs1
VT = 1.5 V
140
17
500
150
500
Jitter, One Sigma1
Jitter, Absolute1
VT = 1.5 V
VT = 1.5 V
-500
70
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP MAX UNITS
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
3.1
0.17
-44
42
V
V
VOL5
0.4
-22
IOH5
mA
mA
IOL5
29
47
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
1.1
54
1
2
2
ns
ns
%
%
%
dt5
57
3
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
3
5
1Guaranteed by design, not 100% tested in production.
12
ICS9148-32
Electrical Characteristics - 48, 24 MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP MAX UNITS
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
3
V
V
VOL5
0.14
-44
42
0.4
-22
IOH5
mA
mA
IOL5
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.2
1.2
52
1
4
4
ns
ns
%
%
%
dt5
55
3
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
3
5
1Guaranteed by design, not 100% tested in production.
13
ICS9148-32
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
MAX.
.110
.016
.092
.0135
.0085
MIN.
.620
.720
NOM. MAX.
A
A1
A2
B
AC
AD
.625
.725
.630
.730
48
56
C
.006
D
See Variations
E
.292
.296
.299
e
H
h
L
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
.032
N
See Variations
5°
0°
8°
X
.085
.093
.100
This table in inches
Ordering Information
ICS9148F-32
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
14
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