ICS9148M-47 [ICSI]
Pentium/ProTM System Clock Chip; 奔腾/ ProTM系统时钟芯片
| 型号： | ICS9148M-47 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Pentium/ProTM System Clock Chip |
| 文件： | 总9页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9148-47
TM
Pentium/Pro System Clock Chip
General Description
Features
The ICS9148-47 is part of a reduced pin count two-chip clock
solution for designs using an Intel BX style chipset.
Companion SDRAM buffers are ICS9179-11 and 12.
Generates system clocks for CPU, PCI, IOAPIC ,
14.314MHz, 48and24MHz.
Supports single or dual processor systems
Skew from CPU (earlier) to PCI clock 1 to 4ns
Separate 2.5V and 3.3V supply pins
2.5Voutputs:CPU, IOAPIC
3.3Voutputs:PCI, REF
No power supply sequence requirements
28 pin SOIC
There are two PLLs, with the first PLL capable of spread
spectrum operation. Spread spectrum typically reduces system
EMI by 8-10dB. The second PLL provides support for USB
(48MHz) and 24MHz requirements. CPU frequencies up to
100MHz are supported.
The I2C interface allows stop clock programming, frequency
selection, and spread spectrum operation to be programmed.
Clock outputs include two CPU (2.5V or 3.3V), seven PCI
(3.3V),oneREF(3.3V),oneIOAPIC(2.5Vor3.3V),one48MHz,
and one selectable 48/24MHz.
Spread Sectrum operation optional for PLL1
CPU frequencies to 100MHz are supported.
Pin Configuration
Block Diagram
28 pin SOIC
Power Groups
VDD = Supply for PLL core
VDD1=REF0,X1,X2
VDD2=PCICLK_F,PCICLK(0:5)
VDD3=48MHz
VDDL=CPUCLK(0:1)
VDDL1=IOAPIC
Ground Groups
GND = Ground Source Core
GND1=REF0,X1,X2
GND2=PCICLK_F,PCICLK(0:5)
GND3=48MHz
GNDL=CPUCLK(0:1)
Pentium is a trademark on Intel Corporation.
9148-47Rev D08/04/98
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148-47
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
XTAL_IN 14.318MHz Crystal input, has internal 33pF load
cap and feed back resistor from X2
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
1
X1
IN
2
3
4
X2
GND2
PCICLK_F
PCICLK (0:5)
VDD2
OUT
PWR
OUT
OUT
PWR
PWR
OUT
Free Running PCI output
5, 6, 7, 8, 10, 11
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Poer for 48MHz
6, 9
12
13
VDD3
48MHz
Fixed CLK output @ 48MHz
Fixed CLK output; 24MHz if pin 27 =1 at power up, 48MHz
if pin 27=0 at power up.
Ground for 48MHz
Select pin for enabling 100MHz or 66.6MHz
H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz)
Clock input for I2C input
Data input for I2C input
Ground for CPUCLK (0:1)
Power for PLL core
CPU and Host clock outputs nominally 2.5V
Power for CPU outputs, nominally 2.5V
IOAPIC clock output 14.318MHz.
14
15
16
24/48MHz
GND3
OUT
PWR
IN
SEL100/66.6#
17
18
19
20
21, 22
23
24
25
26
SCLK
SDATA
GND
IN
IN
PWR
PWR
OUT
PWR
OUT
PWR
PWR
VDD
CPUCLK (1:0)
VDDL
IOAPIC
VDDL
VDD1
Power for IOAPIC
Power for REF outputs.
14.318MHz clock output/Latched input at power up. When
low, pin 14 is 48MHz.
Ground for REF outputs, X1, X2.
27
28
REF0/SEL 48#
GND1
OUT/IN
PWR
2
ICS9148-47
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C
programming application note.
How to Write:
Send the address D2(H) .
Send two additional dummy bytes, a command code
and byte count.
Send the desired number of data bytes.
See the diagram below:
Clock Generator
Address (7 bits)
+ 8 bits
dummy
command code
+ 8 bits
dummy Byte
count
Data Byte
1
Data Byte
N
ACK
ACK
ACK
ACK
ACK
A(6:0) & R/W#
D2(H)
Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must
be sent.
How to Read:
Send the address D3(H).
Send the byte count in binary coded decimal
Read back the desired number of data bytes
See the diagram below:
Clock Generator
Address (7 bits)
Byte
Count
Data Byte
1
Data Byte
N
ACK
ACK
ACK
A(6:0) & R/W#
D3(H)
The following specifications should be observed:
1. Operating voltage for I2C pins is 3.3V
2. Maximum data transfer rate (SCLK) is 100K bits/sec.
3
ICS9148-47
Serial Bitmap
Byte3:Functionality&FrequencySelect
& Spread Slect Register
Byte5:
Description
Bit Value = 0 Bit Value = 1
Disabled
Enabled
(low)
Disabled
Enabled
(low)
Bit
7
Description
(Reserved)
PWD
0
Bit Pin# Pin Name PWD
Bit
654
000
001
010
011
100
101
110
111
Spread
Percentage
7
6
4
PCICLK_F
PCICLK5
1
1
CPU
PCI
68.5
75.0
83.3
66.6
103
112
133.3
100
34.25
37.5
41.6
33.3
34.3
37.3
44.43
33.33
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
±0.5% Center
11
Disabled
Enabled
(low)
5
4
3
10
-
PCICLK4
-
1
0
1
6:4
0
(Reserved)
Disabled
(low)
(Reserved)
8
PCICLK3
Enabled
Disabled
(low)
Disabled
(low)
Disabled
(low)
2
1
0
7
6
5
PCICLK2
PCICLK1
PCICLK0
1
1
1
Enabled
Enabled
Enabled
0 - Frequency is selected by hardware select
SEL100/66.6#
1 - Frequency is selected by 6:4 above
(Reserved)
00 - Normal operation
01 - Test mode
10 - Spread sprectrum ON
11 - Tristate all outputs
3
2
0
Notes: 1 = Enabled; 0 = Disabled, outputs held low
10
00
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte4:
Byte6:
Description
Bit Value = 0 Bit Value = 1
Description
Bit Value = 0 Bit Value = 1
Bit Pin# Pin Name PWD
Bit Pin# Pin Name PWD
7
6
-
-
-
-
0
0
(Reserved)
(Reserved)
Disabled
(low)
(Reserved)
(Reserved)
(Reserved)
(Disabled)
(low)
(Reserved)
(Reserved)
7
6
5
4
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Disabled
(low)
(Reserved)
(Disabled)
(low)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
5
24
IOAPIC
1
Enabled
4
3
2
-
-
-
-
-
-
0
0
0
(Reserved)
(Reserved)
(Reserved)
2
1
0
21
-
CPUCLK1
-
1
0
1
Enabled
(Reserved)
Enabled
1
27
REF0
1
Enabled
22
CPUCLK0
(Disabled)
(low)
0
27
REF0
1
Enabled
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes:
1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
For pin 27, there are 2 output stages together for 1 pin. These 2
latches must be both 0 or 1 simultaneously or there will be a short to
ground if one is disabled and the other is running.
4
ICS9148-47
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
IIH
VIN = VDD
0.1
2.0
-100
60
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
A
µ
IIL2
-200
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
170
170
650
mA
Supply Current
Power Down
66
A
µ
IDD3.3PD
CL = 0 pF; With input address to Vdd or GND
3
Supply Current
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
14.318
36
MHz
pF
CIN
Logic Inputs
5
45
3
CINX
Ttrans
Ts
X1 & X2 pins
27
1
pF
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
ns
5
TSTAB
3
4
TAGP-PCI1 VT = 1.5 V;
3.5
1Guaranteed by design, not 100% tested in production.
5
ICS9148-47
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V+/-5%, VDDL = 2.5 V+/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
IDD2.5OP66
CONDITIONS
MIN
TYP MAX
UNITS
mA
CL = 0 pF; Select @ 66.8 MHz
16
23
72
Supply Current
IDD2.5OP100 CL = 0 pF; Select @ 100 MHz
100
mA
Power Down Supply
Current
CL = 0 pF; With input address to Vdd
IDD2.5PD
10
100
A
µ
or GND
tCPU-AGP
0
1
0.5
2.6
1
4
ns
Skew1
tCPU-PCI2
V = 1.5 V; V = 1.25 V
T
TL
ns
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
2.3
0.2
-41
37
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
IOL2B
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.25
1
1.6
1.6
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
48
55
%
1
Skew
tsk2B
VT = 1.25 V
30
175
250
150
+250
ps
1
Jitter, Cycle-to-cycle tjcyc-cyc2B VT = 1.25 V
150
40
ps
1
Jitter, One Sigma
Jitter, Absolute
tj1s2B
VT = 1.25 V
VT = 1.25 V
ps
1
tjabs2B
-250
140
ps
1Guaranteed by design, not 100% tested in production.
6
ICS9148-47
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.1
0.1
-62
57
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-22
V
IOH1
mA
mA
IOL1
16
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.1
50
2
ns
ns
%
ps
ps
ps
2
dt1
55
tsk1
tj1s1
tjabs1
VT = 1.5 V
140
17
500
150
500
Jitter, One Sigma1
Jitter, Absolute1
VT = 1.5 V
VT = 1.5 V
-500
70
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF
PARAMETER
SYMBOL
VOH4B
VOL4B
IOH4B
CONDITIONS
MIN
2
TYP
2.2
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -18 mA
IOL = 18 mA
VOH = 1.7 V
VOL = 0.7 V
0.33
-41
37
0.4
-28
V
mA
mA
IOL4B
29
45
-5
Rise Time1
Fall Time1
Duty Cycle1
Tr4B
Tf4 B
Dt4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.3
1.1
54
60
1
1.6
1.6
55
250
3
ns
ns
%
ps
%
%
Skew1
Jitter, One Sigma1
Jitter, Absolute1
1
tsk4B
VT = 1.25 V
Tj1s4B
VT = 1.25 V
Tjabs4B
VT = 1.25 V
5
1Guaranteed by design, not 100% tested in production.
7
ICS9148-47
Electrical Characteristics - 48, 24 MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP
3
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.14
-44
42
0.4
-22
V
IOH5
mA
mA
IOL5
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.2
1.2
52
1
4
4
ns
ns
%
%
%
dt5
55
3
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
3
5
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP
3.1
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.17
-44
42
0.4
-22
V
IOH5
mA
mA
IOL5
29
47
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
1.1
54
1
2
2
ns
ns
%
%
%
dt5
57
3
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
3
5
1Guaranteed by design, not 100% tested in production.
8
ICS9148-47
LEAD COUNT
DIMENSION L
28L
0.704
SOIC Package
Ordering Information
ICS9148M-47
Example:
ICS XXXX M - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
9
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