ICS9148YF-17-T [ICSI]
Frequency Generator & Integrated Buffers for PENTIUM/ProTM; 频率发生器和缓冲器集成奔腾/ ProTM
| 型号： | ICS9148YF-17-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| 文件： | 总15页 (文件大小：467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Incꢀ
ICS9148-17
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
Features
3ꢀ3Voutputs: SDRAM,AGP, PCI, REF, 48/24MHz
The ICS9148-17 generates all clocks required for high speed
RISCorCISCmicroprocessorsystemssuchasIntel PentiumPro
orCyrixꢀEightdifferentreferencefrequencymultiplyingfactors
are externally selectable with smooth frequency transitionsꢀ
2ꢀ5Vor3ꢀ3Voutputs:CPU
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
CPU to PCI skew = 2 to 6ns
No external load cap for CL=18pF crystals
250psmaxCPU, PCIclockskew
Smooth CPU frequency transition among all CPU
frequenciesꢀ
Features include four CPU, six PCI, two AGP (=2xPCI) and
Twelve SDRAM clocksꢀ Two reference outputs are available
equal to the crystal frequencyꢀ One 48 MHz for USB, and one
24MHzclockforSuperIOꢀBuiltin±1ꢀ5%, 0ꢀ6%centerordown
spread spectrum modulation to reduce EMIꢀ Serial
programming I2C interface allows changing functions, stop
clock programing and frequency selectionꢀ Additionally, the
device meets the Pentium power-up stabilization, which
requires that CPU and PCI clocks be stable within 2ms after
power-upꢀ
I2C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%ꢀ
48pin300milSSOPpackage
3ꢀ3V operation, 5V tolerant inputsꢀ
Pin Configuration
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loadsꢀ CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50±5% duty cycleꢀ The REF and 24 and 48
MHz clock outputs typically provide better than 0ꢀ5V/ns slew
ratesꢀ
Block Diagram
PLL2
48MHz
24MHz
/2
X1
X2
XTAL
OSC
REF (0:1)
AGP(0:1)
STOP
STOP
2
PLL1
Spread
Spectrum
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3ꢀ3V on indicated inputs
CPUCLK (0:3)
SDRAM (0:11)
4
12
5
CPU_STOP
FS(0:2)
MODE
CPU3.3#_2.5
3
LATCH
PCI
CLOCK
DIVDER
STOP
PCICLK (0:4)
PCICLK_F
5
Power Groups
POR
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
Control
Logic
PCI_STOP
CPU_STOP#
PCI_STOP#
Config.
Reg.
SDATA
SCLK
VDD4=AGP(0:1)
VDDL=CPUCLK(0:3)
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9148-17 Rev G 4/27/00
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148-17
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
PWR
OUT
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
1
VDD1
REF0
2
Indicates whether VDDL is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V
CPU1. Latched input.
CPU3.3#_2.51,2
IN
PWR
IN
3,9,16,22,27,
33,39,45
GND
X1
Ground.
Crystal input, has internal load cap (33pF) and feedback
resistor from X2.
4
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF).
5
X2
OUT
6,14
VDD2
PWR
OUT
IN
Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V
Free running PCI clock
PCICLK_F
FS11, 2
7
8
Frequency select pin. Latched input
PCI clock output.
PCICLK0
FS21, 2
OUT
IN
Frequency select pin. Latched input
PCI clock outputs.
10, 11, 12, 13
15, 47
PCICLK (1:4)
AGP (0:1)
OUT
OUT
Advanced Graphic Port outputs, powered by VDD4.
Halts CPUCLK (0:3) clocks and AGP (0:1) clocks at logic 0 level, when
input low (in Mobile Mode, MODE=0)
CPU_STOP#1
SDRAM 11
PCI_STOP#1
SDRAM 10
SDRAM (0:9)
IN
17
18
OUT
IN
SDRAM clock output
Halts PCICLK (0:5) clocks at logic 0 level, when input low
(in mobile mode, MODE=0)
OUT
OUT
SDRAM clock output
20, 21,28, 29, 31,
32, 34, 35,37,38
SDRAM clock outputs.
Supply for SDRAM (0:11), Core, 24MHz and 48MHz clocks,
nominal 3.3V.
19,30,36
VDD3
PWR
23
24
SDATA
SCLK
IN
IN
Data input for I2C serial input.
Clock input of I2C input
24MHz output clock.
24MHz
OUT
25
26
Pin 17, 18 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched input.
MODE1, 2
IN
48MHz
OUT
48MHz output clock
FS01, 2
IN
Frequency select pin. Latched input
CPU clock outputs, powered by VDDL.
Supply for CPU (0:3), either 2.5V or 3.3V nominal
14.318MHz reference clock.
40, 41, 43, 44
CPUCLK (0:3)
VDDL
OUT
PWR
OUT
PWR
42
46
48
REF1
VDD4
Supply for AGP (0:1)
Notes:
1: Internal Pull-up Resistor of 240K to 3ꢀ3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-resetꢀ Use 10Kohm resistor to
program logic Hi to VDD or GND for logic lowꢀ
2
ICS9148-17
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
Pin 17
Pin 18
CPU_STOP#
(INPUT)
PCI_STOP#
(INPUT)
0
SDRAM 11
(OUTPUT)
SDRAM 10
(OUTPUT)
1
Power Management Functionality
PCICLK_F,
REF,
24/48MHz
and SDRAM
AGP,
CPUCLK
Outputs
PCICLK
(0:5)
Crystal
OSC
CPU_STOP# PCI_STOP#
VCO
0
1
1
1
1
0
Stopped Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Buffer Selected for
Input level
operation at:
(Latched Data)
1
0
2.5V VDD
3.3V VDD
Functionality
VDD1, 2, 3, 4=3ꢀ3V±5%,VDDL = 2ꢀ5V±5% or 3ꢀ3 ±5%, TA= 0 to 70°C
Crystal (X1, X2) = 14ꢀ31818MHz
CPU, SDRAM
PCI
(MHz)
33.4
30
32
32
37.5
34.25
33.4
30
AGP
(MHz)
66.8
60
64
64
REF, IOAPIC
(MHz)
FS2
FS1
FS0
(MHz)
100.2
90
83.3
75
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
75
75
68.5
66.8
60
68.5
66.8
60
3
ICS9148-17
General I2C serial interface information
The information in this section assumes familiarity with I2C programmingꢀ
For more information, contact ICS for an I2C programming application noteꢀ
How to Write:
Controller (host) sends a start bitꢀ
Controller (host) sends the write address D2(H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bitꢀ
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a timeꢀ
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1ꢀ
The ICS clock generator is a slave/receiver, I2C componentꢀ It can read back the data stored in the latches for verificationꢀ
Read-BackwillsupportIntelPIIX4"Block-Read"protocolꢀ
2ꢀ
3ꢀ
4ꢀ
5ꢀ
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3ꢀ3V logic levelsꢀ
The data byte format is 8 bit bytesꢀ
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controllerꢀ The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferredꢀ The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytesꢀ The data is loaded until a Stop sequence is issuedꢀ
6ꢀ
At power-on, all registers are set to a default condition, as shownꢀ
4
ICS9148-17
Serial Configuration Command Bitmap
Byte0:FunctionalityandFrequencySelectRegister(default=0)
Bit
Description
0 - ±1.5% Spread Spectrum Modulation
1 - ±0.6% Spread Spectrum Modulation
PWD
0
Bit 7
Bit 6,5,4 CPU Clock
PCI
AGP
111
110
101
100
011
010
001
000
100.2
90
33.4
30
66.8
60
Note 1ꢀ Default at Power-up will be for latched logic inputs
to define frequencyꢀ Bits 4, 5, 6 are default to 000,
and if bit 3 is written to a 1 to use bits 6:4, then
these should be defined to desired frequency at same
write cycleꢀ
Bit
6:4
83.3
75
32
64
Note 1
0,0,0
32
64
75
68.5
66.8
60
75
37.5
34.25
33.4
30
68.5
66.8
60
Note: PWD = Power-Up Default
0 - Frequency is selected by hardware select,
Bit 3
Latched Inputs
0
1 - Frequency is selected by Bit 6:4 (above)
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
I2C is a trademark of Philips Corporation
Bit 2
Bit 1
Bit 0
0
0
0
5
ICS9148-17
Byte 1: CPU,Active/Inactive Register
(1 = enable, 0 = disable)
Byte2:PCIActive/InactiveRegister
(1 = enable, 0 = disable)
Bit
Pin # PWD
Description
Latched FS1#
PCICLK_F (Act/Inact)
AGP0 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Bit
Pin #
-
-
-
PWD
Description
Version bit
(Reserved)
(Reserved)
(Reserved)
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
1
1
1
1
1
1
7
1
1
1
1
1
1
1
15
14
12
11
10
8
-
40
41
43
44
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: SDRAMActive/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
28
29
31
32
34
35
37
38
PWD
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Bit
Pin #
PWD
-
1
1
1
Description
Latched FS0#
(Reserved)
(Reserved)
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
-
-
-
-
Bit 3
Bit 2
17
18
1
1
Bit 1
Bit 0
20
21
1
1
Byte5:Peripheral Active/InactiveRegister
(1 = enable, 0 = disable)
Bit
Pin #
-
-
-
47
-
-
46
2
PWD
-
Description
Latched FS2#
(Reserved)
(Reserved)
AGP1(Act/Inact)
(Reserved)
(Reserved)
REF1 (Act/Inact)
REF0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
Notes:
1ꢀ Inactive means outputs are held LOW and are disabled
from switchingꢀ
2ꢀ Latched Frequency selects will be Inverted logic level of
the input frequency select pin conditionsꢀ
6
ICS9148-17
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizerꢀ It is used to turn off the CPU clocks for low power operationꢀ
CPU_STOP# is synchronized by the ICS9148-17ꢀ The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocksꢀAll other clocks will continue to run while the CPU clocks are disabledꢀ The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulseꢀ CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocksꢀ
Notes:
1ꢀ All timing is referenced to the internal CPU clockꢀ
2ꢀ CPU_STOP# is an asynchronous input and metastable conditions may existꢀ This signal is synchronized
to the CPU clocks inside the ICS9148-17ꢀ
3ꢀ All other clocks except CPU and AGP clocks continue to run undisturbedꢀ
7
ICS9148-17
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-17ꢀ It is used to turn off the PCICLK (0:5) clocks for low power operationꢀ
PCI_STOP# is synchronized by theICS9148-17 internallyꢀThe minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocksꢀ PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteedꢀ PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clockꢀ
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-running)
CPU_STOP#
(High)
PCI_STOP#
PCICLK
(External)
Notes:
1ꢀ All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 deviceꢀ)
2ꢀ PCI_STOP# is an asynchronous input, and metastable conditions may existꢀ This signal is required to be synchronized
inside the ICS9148ꢀ
3ꢀ All other clocks continue to run undisturbedꢀ
8
ICS9148-17
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is usedꢀ With no jumper is installed
the pin will be pulled highꢀ With the jumper in place the pin
will be pulled lowꢀ If programmability is not necessary, than
only a single resistor is necessaryꢀThe programming resistors
should be located close to the series termination resistor to
minimize the current loop areaꢀ It is more important to locate
the series termination resistor close to the driver than the
programming resistorꢀ
The I/O pins designated by (input/output) on the ICS9148-17
serve as dual signal functions to the deviceꢀ During initial
power-up, they act as input pinsꢀ The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latchꢀ At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output functionꢀ
In this mode the pins produce the specified buffered clocks
to external loadsꢀ
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potentialꢀ A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating periodꢀ
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
9
ICS9148-17
Absolute Maximum Ratings
Supply Voltage ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 7ꢀ0V
Logic Inputs ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ GND 0ꢀ5 V to VDD +0ꢀ5 V
Ambient Operating Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 0°C to +70°C
Storage Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the deviceꢀ These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not impliedꢀ Exposure to absolute maximum rating conditions for extended periods
may affect product reliabilityꢀ
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
VIL
VSS-0.3
V
IIH
VIN = VDD
0.1
2.0
5
µA
µA
µA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
-100
100
IDD3.3OP CL = 0 pF; 66.8 MHz
160
Supply Current
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
14.318
36
MHz
pF
pF
ms
ms
ms
ps
CIN
Logic Inputs
5
45
2
CINX
Ttrans
Ts
X1 & X2 pins
27
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
TSTAB
2
500
6
TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads
TCPU-PCI1 VT = 1.5 V; CPU Leads
-500
2
200
5
ns
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
CL = 0 pF; 66.8 MHz
MIN
TYP
10
MAX
20
UNITS
mA
Operating
IDD2.5OP
Supply Current
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
-500
2
200
5
500
6
ps
ns
Skew1
1Guaranteed by design, not 100% tested in production.
10
ICS9148-17
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
2.5
TYP
2.6
0.35
-29
37
MAX
UNITS
V
VOH2A IOH = -28 mA
VOL2A IOL = 27 mA
0.4
-23
V
IOH2A
IOL2A
VOH = 2.0 V
mA
mA
ns
VOL = 0.8 V
33
45
1
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.75
1.1
50
2
1
Fall Time
tf2A
2
ns
1
Duty Cycle
dt2A
55
%
1
Skew
tsk2A
VT = 1.5 V
50
250
150
250
ps
1
Jitter, One Sigma
Jitter, Absolute
tj1s2A
VT = 1.5 V
65
ps
1
tjabs2A
VT = 1.5 V
-250
165
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
OH = -8 mA
MIN
2
TYP
2.2
0.3
-20
26
MAX
UNITS
V
Output High Voltage VOH2B
I
Output Low Voltage VOL2B IOL = 12 mA
Output High Current IOH2B VOH = 1.7 V
0.4
-16
V
mA
mA
ns
Output Low Current
Rise Time
IOL2B VOL = 0.7 V
tr2B1
tf2B1
dt2B1
tsk2B1
19
40
VOL = 0.4 V, VOH = 2.0 V
1.5
1.6
47
1.8
1.8
55
Fall Time
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
ns
Duty Cycle
%
Skew
VT = 1.25 V
60
250
ps
Jitter, Single Edge
Displacement2
Jitter, One Sigma
Jitter, Absolute
tjsed2B1
tj1s2B1
tjabs2B1
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
200
65
250
150
300
ps
ps
ps
-300
160
1 Guaranteed by design, not 100% tested in production.
2 Edge displacement of a period relative to a 10-clock-cycle rolling average period.
11
ICS9148-17
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
3
MAX
UNITS
V
VOL1
IOL = 23 mA
0.2
-60
50
0.4
-40
V
IOH1
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
41
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.8
1.6
51
2
2
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
55
250
%
1
Skew
tsk1
VT = 1.5 V
130
ps
Jitter, One Sigma1
Jitter, Absolute1
tj1s1a
tj1s1b
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
40
150
250
ps
ps
200
tabs1a VT = 1.5 V, synchronous
tjabs1b VT = 1.5 V, asynchronous
-250
-650
135
500
250
650
ps
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
MAX
UNITS
V
3
IOL = 23 mA
0.2
-60
50
0.4
-40
V
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
41
45
Tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.75
1.5
50
2
2
Fall Time1
Duty Cycle1
Tf1
ns
Dt1
55
%
Skew1
Tsk1
VT = 1.5 V
200
50
500
150
+250
400
ps
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Absolute1
Tj1s1
Tjabs1
Tjabs1
VT = 1.5 V
ps
VT = 1.5 V (with synchronous PCI)
VT = 1.5 V (with asynchronous PCI)
-250
-400
ps
ps
1Guaranteed by design, not 100% tested in production.
12
ICS9148-17
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
3
MAX
UNITS
V
VOL1
IOL = 23 mA
0.2
-60
50
1.1
1
0.4
-40
V
IOH1
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
41
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.4 V
2
2
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
49
130
2
55
250
3
%
1
Skew
tsk1
VT = 1.5 V
ps
Jitter, One Sigma1
Jitter, Absolute1
tj1s1
tabs1a
tjabs1b
VT = 1.5 V
%
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
-5
-6
2.5
4.5
5
%
6
%
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz, REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH5
CONDITIONS
IOH = -16 mA
MIN
2.4
TYP
MAX
UNITS
V
2.6
0.3
-32
25
2
VOL5
IOL = 9 mA
0.4
-22
V
IOH5
VOH = 2.0 V
mA
mA
ns
IOL5
VOL = 0.8 V
16
1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4
4
1
Fall Time
tf5
1.9
54
1
ns
1
Duty Cycle
dt5
45
-5
57
3
%
1
Jitter, One Sigma
Jitter, Absolute
tj1s5
VT = 1.5 V
%
1
tjabs5
VT = 1.5 V
-
5
%
1Guaranteed by design, not 100% tested in production.
13
ICS9148-17
GeneralLayoutPrecautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
tracesꢀ
2) Make all power traces and vias as
wide as possible to lower inductanceꢀ
Notes:
1 All clock outputs should have series
terminating resistorꢀ Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputsꢀ
3 Optional crystal load capacitors are
recommendedꢀ
CapacitorValues:
C1, C2 : Crystal load values determined by user
C3:100pFceramic
All unmarked capacitors are 0ꢀ01µF ceramic
14
ICS9148-17
Ordering Information
ICS9148yF-17-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
15
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