ICS9148YF-111 [ICSI]
Frequency Generator & Integrated Buffers for PENTIUM/ProTM; 频率发生器和缓冲器集成奔腾/ ProTM
| 型号： | ICS9148YF-111 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| 文件： | 总18页 (文件大小：544K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9148-111
Integrated
Circuit
Systems, Inc.
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
Recommended Application:
ALI (Aladdin V ) mobile.
Pin Configuration
Output Features:
•
•
•
•
•
•
3 - CPUs @ 2.5V/3.3V, up to 100MHz.
3 - AGPCLK @ 3.3V
13 - SDRAM @ 3.3V, up to 100MHz.
6 - PCI @ 3.3V, including one free running.
1 - 48MHz, @ 3.3V fixed.
1 - REF @ 3.3V, 14.318MHz.
Features:
•
•
Up to 100MHz frequency support
Support power management: CPU, PCI, AGP stop and,
Power down Mode from I2C programming.
•
•
•
Spread spectrum for EMI control (0 to -0.6%, ± 0.25%).
Uses external 14.318MHz crystal
FS pins for frequency select
Key Specifications:
•
•
•
•
•
•
•
CPU – CPU: <250ps
SDRAM - SDRAM: <250ps
AGP-AGP: <250ps
48-Pin 300mil SSOP
PCI – PCI: <500ps
CPU-SDRAM <500ps
CPU(early)-PCI: 1-4ns, Center 2-6ns
CPU-AGP <500ps
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Block Diagram
Functionality
CPU,
PCI
AGP
REF,
IOAPIC
(MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
FS2 FS1 FS0 SDRAM (MHz) (MHz)
(MHz)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
100
95.25
83.3
75
91.5
96.22
66.8
60
33.33 66.67
31.75 63.50
33.30 66.60
30.00 60.00
30.50 61.00
32.07 64.15
33.40 66.80
30.00 60.00
9148-111 Rev A 10/19/99
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9148-111
Pin Configuration
PIN NUMBER
PIN NAME
VDD1
REF0
TYPE
PWR
OUT
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.
Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V
CPU1. Latched input2
1
2
CPU3.3#_2.51,2
IN
PWR
IN
3,9,16,22,27,
33,39,45
GND
X1
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
4
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew
(CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
5
6
X2
OUT
PWR
OUT
VDD2
PCICLK_F
7
FS11, 2
IN
PCICLK0
FS21, 2
OUT
IN
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input
8
10, 11, 12, 13
PCICLK(1:4)
VDD5
BUFFERIN
OUT
PWR
IN
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Supply for fixed PLL, 48MHz, AGP0
Input pin for SDRAM buffers.
14
15
Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile
Mode, MODE=0)
SDRAM clock output
Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode,
MODE=0)
SDRAM clock output
CPU_STOP#1
SDRAM 11
PCI_STOP#1
SDRAM 10
SDRAM (0:9)
IN
17
18
OUT
IN
OUT
OUT
28, 29, 31, 32, 34,
35,37,38
SDRAM clock outputs.
This asynchronous input halts AGP(1:2) clocks at logic "0" level when input
low (in Mobile Mode, MODE=0) Does not affect AGP0
SDRAM clock output
This asyncheronous Power Down input Stops the VCO, crystal & internal
clocks when active, Low. (In Mobile Mode, MODE=0)
SDRAM clock output
AGP_STOP#
SDRAM9
PD#
IN
20
OUT
IN
21
SDRAM8
VDD3
OUT
PWR
Supply for SDRAM (0:11), CPU Core, 48MHz clocks,
nominal 3.3V.
19,30,36
23
24
SDATA
SCLK
IN
IN
Data input for I2C serial input.
Clock input of I2C input
Advanced Graphic Port output, powered by VDD4. Not affected by
AGP_STOP#
AGP0
OUT
25
Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock for USB timing.
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Feedback SDRAM clock output.
Supply for CPU (0:3), either 2.5V or 3.3V nominal
Advanced Graphic Port outputs, powered by VDD4.
Supply for AGP (0:2)
MODE1, 2
48MHz
FS01, 2
IN
OUT
IN
26
41, 43, 44
40
42
46, 47
48
CPUCLK(0:3)
SDRAM12
VDDL
AGP (1:2)
VDD4
OUT
OUT
PWR
OUT
PWR
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9148-111
General Description
Power Groups
The ICS9148-111 is a single chip clock solution for Desktop/
VDD1 = REF (0:1), X1, X2
Notebook designs using the ALI (Aladdin V ) mobile style
VDD2=PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:12), supply for PLL core
VDD4 =AGP(1:2)
chipset. It provides all necessary clock signals for such a
system.
VDD5 = Fixed PLL, 48MHz ,AGP0
VDDL= CPUCLK (0:2)
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-111
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
Pin 17
Pin 18
Pin 20
Pin 21
CPU_STOP#
(INPUT)
SDRAM 11
(OUTPUT)
PCI_STOP#
(INPUT)
SDRAM 10
(OUTPUT)
AGP_STOP#
(INPUT)
SDRAM 9
(OUTPUT)
PD#
0
(INPUT)
SDRAM 8
(OUTPUT)
1
Power Management Functionality
AGP,
CPUCLK
Outputs
PCICLK_F,
REF, 48MHz
and SDRAM
PCICLK
(0:5)
Crystal
OSC
AGP_STOP# CPU_STOP# PCI_STOP#
VCO
AGP(1:2)
1
1
1
0
0
1
1
1
1
1
0
1
Stopped Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped Low
Running
Running
Running Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Buffer Selected for
Input level
operation at:
(Latched Data)
1
0
2.5V VDD
3.3V VDD
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3
ICS9148-111
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2(H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
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4
ICS9148-111
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
Must be 0 for normal operation
Bit 7
0
0 -- +/- 0.25% Spread Spectrum Modulation
1 -- +/- 0.6% Spread Spectrum Modulation
Bit6 Bit5 Bit4
CPU Clock
100
PCI
AGP
33.33
31.75
33.30
30.00
30.50
32.07
33.40
30.00
66.67
63.50
66.60
60.00
61.00
64.15
66.80
60.00
111
110
101
100
011
010
001
000
95.25
83.3
75
91.5
96.22
66.8
60
Bit 6:4
Note 1
0 - Frequency is selected by hardware select, Latched inputs
1 - Frequency is selected by Bit 6:4 (above)
Must be 0 for normal operation
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0 - Normal
Bit 3
Bit 2
0
0
Bit 1
Bit 0
0
0
1 - Spread Spectrum Enabled
0 - Running
1 - Tristate all outputs
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if
bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle.
Note: PWD = Power-Up Default
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin # PWD
Description
(Reserved)
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Bit
Pin #
-
-
-
40
-
41
43
44
PWD
Description
(Reserved)
(Reserved)
(Reserved)
SDRAM12 (Act/Inact)
(Reserved)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
7
-
13
12
11
10
8
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
Third party brands and names are the property of their respective owners.
5
ICS9148-111
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
28
29
31
32
34
35
37
38
PWD
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Bit
Pin #
25
-
-
-
PWD
Description
AGP0 (Active/Inactive)
(Reserved)
(Reserved)
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 3
Bit 2
17
18
1
1
Bit 1
Bit 0
20
21
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 6: Optional Register for Possible
Furture Requirements
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
PWD
Description
(Reserved)
Bit
Pin #
-
-
-
47
-
-
46
2
PWD
Description
(Reserved)
(Reserved)
(Reserved)
AGP1 (Act/Inact)
(Reserved)
(Reserved)
AGP2 (Act/Inact)
REF0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
1. Inactive means outputs are held LOW and are disabled
from switching.
Third party brands and names are the property of their respective owners.
6
ICS9148-111
Shared Pin Operation -
Input/Output Pins
Pins 2, 7, 8, 25 & 26 on the ICS9148-111 serve as dual signal
functions to the device. During initial power-up, they act as
input pins. The logic level (voltage) that is present on these
pins at this time is read and stored into a 4-bit internal data
latch. At the end of Power-On reset, (see AC characteristics
for timing values), the device changes the mode of operations
for these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
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7
ICS9148-111
Fig. 2a
Fig. 2b
Third party brands and names are the property of their respective owners.
8
ICS9148-111
AGP_STOP# Timing Diagram
AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP clocks. for low power operation.
AGP_STOP# is synchronized by the ICS9148-111. The AGPCLKs will always be stopped in a low state and start in such a
manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK and AGPCLK off latency
is less than 4 AGPCLKs. This function is available only with MODE pin latched low.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. AGP_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9148-111.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
5. Only applies if MODE pin latched 0 at power up.
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9
ICS9148-111
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-111. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-111.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
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10
ICS9148-111
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-111. It is used to turn off the PCICLK (0:5) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9148-111 internally. The minimum that the PCICLK (0:5) clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full
high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK
clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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11
ICS9148-111
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148-111 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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12
ICS9148-111
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD=3.3 V +\- 5%, VDDL = 2.5 V +/- 5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
VSS-0.3
TYP
MAX UNITS
VDD+0.3
V
V
VIL
0.8
5
IIH
VIN = VDD
0.1
2.0
µA
µA
µA
mA
mA
µA
MHz
pF
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
-100
115
IDD3.3OP66
IDD3.3OP100
IDD3.3PD
Fi
Select @ 66.8MHz; CL=0; all outputs running
Select @ 100MHz; CL=0; all outputs running
PD# = 0; Full capacitive loads
VDD = 3.3 V
160
190
600
16
5
Supply Current
140
Power down Current
150
Input frequency
Input Capacitance1
12
27
14.318
CIN
Logic Inputs
CINX
X1 & X2 pins
36
45
2
pF
Transition Time1
Settling Time1
Clk Stabilization1
TTrans
TS
To first crossing of target Freq.
From first crossing to 1% of target Freq.
0.65
0.35
<1.5
2.5
ms
ms
ms
ns
3
TSTAB From VDD = 3.3 V to 1% target Freq.
TCPU-PCI VT=1.5 V; f=66/100 MHz; VDD=VDDL
TCPU-PCI VT=1.5 V; f=83/75 MHz; VDD=VDDL
TAGP-PCI VT = 1.5 V; AGP leads
2
2
2
4
Skew1
4.25
400
5
ns
700
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
IDD2.5OP66
IDD2.5OP100
CONDITIONS
MIN
TYP
15
MAX UNITS
30
35
mA
mA
Operating
Select @ 66.8MHz; CL=0; all outputs running
Select @ 100MHz; CL=0; all outputs running
Supply Current
18
1Guaranteed by design, not 100% tested in production.
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13
ICS9148-111
Electrical Characteristics - CPU3.3
TA = 0 - 70º C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2.5
TYP
2.6
0.34
-29
52
MAX UNITS
V
IOH = -28 mA
IOL = 24 mA
VOH =2.0 V
VOL = 0.8 V
0.4
-23
V
mA
mA
ns
IOL2B
33
45
1
tr2B
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
2
2
1
Fall Time
tf2B
0.9
52
ns
1
Duty Cycle
dt2B
55
%
1
Skew
Jitter, Single Edge
Displacement2
tsk2B
VT = 1.5 V
90
150
285
175
320
550
ps
ps
ps
VT = 1.5 V; f=66/100 MHz
VT = 1.5 V; f=75/83 MHz
tjsrd2B1
1Guaranteed by design, not 100% tested in production.
2Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Electrical Characteristics - CPU2.5
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
2.2
0.22
-20
39
MAX UNITS
V
IOH = -8.0 mA
IOL = 12 mA
VOH =1.7 V
VOL = 0.7 V
0.4
-16
V
mA
mA
ns
IOL2B
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1
1.6
1.6
55
1
Fall Time
tf2B
0.9
51
ns
1
Duty Cycle
dt2B
%
1
Skew
tsk2B
VT = 1.25 V
110
170
175
340
ps
Jitter, Single Edge
Displacement2
tjsrd2B1
VT = 1.25 V; f=66/100 MHz
ps
VT = 1.25 V; f=75/83 MHz
310
680
ps
1Guaranteed by design, not 100% tested in production.
2Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Third party brands and names are the property of their respective owners.
14
ICS9148-111
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
VOL1
IOH1
CONDITIONS
MIN
2.4
TYP
3
MAX UNITS
V
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
0.32
-60
54
0.4
-40
V
mA
mA
ns
IOL1
41
45
Rise Time1
Fall Time1
Duty Cycle1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.6
1.3
51
2
2
tf1
dt1
tsk1
ns
55
250
%
Skew1
VT = 1.5 V
100
ps
Jitter, Single Edge
Displacement2
VT = 1.5 V
tjsrd1
220
500
ps
1Guaranteed by design, not 100% tested in production.
2Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH3
CONDITIONS
MIN
2.4
TYP
2.9
MAX UNITS
V
IOH = -24 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
VOL3
0.35
-68
53
0.4
-40
V
mA
mA
ns
IOH3
IOL3
41
48
1
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.4
2
2
1
Fall Time
Tf3
1.4
ns
1
Duty Cycle
Dt3
VT = 1.5 V
54
60
%
VT = 1.5 V, Sdram 0,8,9,12 Window
VT = 1.5 V, Sdram 2,4,5,6 Window
VT = 1.5 V, Sdram 1,3,7,10,11 Window
VT = 1.5 V
140
120
140
3.5
Skew1
Tsk1
250
4.5
ps
ns
Tprop
Propagation Delay
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
15
ICS9148-111
Electrical Characteristics - AGP
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3
MAX UNITS
V
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.32
-60
54
0.4
-40
V
IOH1
mA
mA
IOL1
41
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
1.3
2
ns
Fall Time1
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V, AGP0
1.2
51
53
2
ns
%
%
45
48
55
58
Duty Cycle1
dt1
VT = 1.5 V, AGP1:2
Skew1
tsk1
VT = 1.5 V
110
660
250
ps
ps
Jitter, Single Edge
Displacement2
VT = 1.5 V, AGP0
1200
tjsrd1
VT = 1.5 V, AGP1:2
310
650
ps
1Guaranteed by design, not 100% tested in production.
2Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Electrical Characteristics - REF0, 48MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
2.6
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.24
-32
28
0.4
-22
V
IOH5
mA
mA
IOL5
16
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.5
2.1
4
4
ns
ns
dt5
VT = 1.5 V, REF0
VT = 1.5 V, 48M
VT = 1.5 V, REF0
50
46
55
55
60
56
%
%
ps
Jitter, Single Edge
Displacement2
tjsrd5
430
750
VT = 1.5 V, 48M
VT = 1.5 V, REF0
VT = 1.5 V, 48M
790
350
520
1200
550
ps
ps
ps
-550
-700
Jitter, Absolute1
tjabs5
700
1Guaranteed by design, not 100% tested in production.
2Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Third party brands and names are the property of their respective owners.
16
ICS9148-111
General Layout Precautions:
1) Use a ground plane on the top routing
layer of the PCB in all areas not used
by traces.
Ferrite
Bead
C2
22µF/20V
Tantalum
VDD
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Ferrite
Bead
C2
22µF/20V
Tantalum
2
3
VDD
C1
4
5
Notes:
C1
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and series
terminating resistor. Not shown in all
places to improve readability of
diagram.
6
7
2.5V Power Route
8
9
3.3V Power Route
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2 Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
3.3V Power Route
1
Clock Load
Component Values:
C1 : Crystal load values determined by user
C2 : 22µF/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 15pF capacitor
C3
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0.01µF ceramic
= Routed Power
= Ground Connection Key (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
Connections to VDD:
= Clock Load
Third party brands and names are the property of their respective owners.
17
ICS9148-111
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
NOM. MAX.
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
MIN.
.620
A
A1
A2
B
AC
.625
.630
48
C
D
E
See Variations
.296
.292
.299
e
H
h
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
SSOP Package
L
.032
N
See Variations
5°
.093
0°
.085
8°
.100
X
Ordering Information
ICS9148yF-111
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
18
information being relied upon by the customer is current and accurate.
相关型号：
ICS9148YF-37LF-T
Processor Specific Clock Generator, 100MHz, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48
IDT
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