ICS9148YF-46 [ICSI]
Pentium/ProTM System Clock Chip; 奔腾/ ProTM系统时钟芯片
| 型号： | ICS9148YF-46 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Pentium/ProTM System Clock Chip |
| 文件： | 总9页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9148-46
TM
Pentium/Pro System Clock Chip
General Description
Features
The ICS9148-46 is part of a reduced pin count two-chip clock
solution for designs using an Intel BX style chipset.
CompanionSDRAMbuffersareICS9179-03, and-12.
Generates system clocks for CPU, PCI, 14.314 MHz,
48and24MHz.
Supports single or dual processor systems
Skew from CPU (earlier) to PCI clock 1 to 4ns
Separate 2.5V and 3.3V supply pins
2.5V outputs: CPU
3.3Voutputs:PCI, REF
No power supply sequence requirements
28 pin SSOP
There are two PLLs, with the first PLL capable of spread
spectrum operation. Spread spectrum typically reduces system
EMI by 8-10dB. The second PLL provides support for USB
(48MHz) and 24MHz requirements. CPU frequencies up to
100MHz are supported.
The I2C interface allows stop clock programming, frequency
selection, and spread spectrum operation to be programmed.
ClockoutputsincludetwoCPU(2.5Vor3.3V), fivePCI(3.3V),
two REF (3.3V), one 48MHz, and one selectable 48_24MHz.
Spread Sectrum operation optional for PLL1
CPU frequencies to 100MHz are supported.
Pin Configuration
Block Diagram
28 pin SSOP
Power Groups
VDD = Supply for PLL core
VDD1=REF(0:1),X1,X2
VDD2=PCICLK_F,PCICLK(0:3)
VDD3=48MHz,24/48MHz
VDDL=CPUCLK(0:1)
Ground Groups
GND=GroundSourceCore, CPUCLK(0:1)
GND1=REF(0:1),X1,X2
GND2=PCICLK_F,PCICLK(0:5)
GND3=48MHz,24/48MHz
Pentium is a trademark on Intel Corporation.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9148-46 Rev E 4/20/99
information being relied upon by the customer is current and accurate.
ICS9148-46
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
PWR
DESCRIPTION
Ground for REF (0:1), X1, X2.
1
GND1
XTAL_IN 14.318MHz Crystal input, has internal 33pF
load cap and feed back resistor from X2
2
X1
IN
3
4
5
X2
GND2
PCICLK_F
PCICLK (0:3)
VDD2
OUT
PWR
OUT
OUT
PWR
PWR
OUT
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output. Not affected by PCI_STOP#
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Poer for 48MHz
6, 7, 9, 10
8
11
12
VDD3
48MHz
Fixed CLK output @ 48MHz
Fixed CLK output; 24MHz if pin 27 =1 at power up,
48MHz if pin 27=0 at power up.
Ground for 48MHz
13
14
24_48MHz
GND3
OUT
PWR
Select pin for enabling 100MHz or 66.6MHz
H=100MHz, L=66.6MHz (PCI always synchronous
33.3MHz)
Clock input for I2C input
Data input for I2C input
15
SEL100/66.6#
IN
16
17
SCLK
SDATA
IN
IN
Asynchronous input when driven active (LOW) disables
internal clocks, stops VCO early. All outputs are placed
in a LOW state at the end of the curent cycle.
18
PD#
IN
Asynchronous input when driven active (LOW) stops
CPUCLK(0:1) in a LOW state.
Asynchronous input when driven active (LOW) stops
PCICLK(0:3) in a LOW state. PCICLK_F is not affected.
19
20
CPU_STOP#
PCI_STOP#
IN
IN
21
22
23, 24
25
26
27
GND
VDD
CPUCLK (1:0)
VDDL
PWR
PWR
OUT
PWR
OUT
PWR
OUT
IN
Ground for CPUCLK (0:1) and the core
Power for PLL core
CPU and Host clock outputs nominally 2.5V
Power for CPU outputs, nominally 2.5V
14.318MHz Reference clock output
Power for REF outputs.
REF1
VDD1
REF0
SEL 48#
14.318MHz clock output
Latched input at power up. When low, pin 13 is 48MHz.
28
2
ICS9148-46
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
3
ICS9148-46
Serial Bitmap
Byte3:Functionality&FrequencySelect
& Spread Slect Register
Byte5:
Description
Bit Value = 0 Bit Value = 1
Disabled
Enabled
(low)
Disabled
Enabled
(low)
Bit
Description
0: Center Spread ±0.255%
1: Down Spread 0 to -0.6%
PWD
Bit Pin# Pin Name PWD
7
0
7
6
5
PCICLK_F
PCICLK3
1
1
Bit
CPU
PCI
654
000
001
010
011
100
101
110
111
10
68.5
75.0
83.3
66.6
103
112
133.3
100
34.25
37.5
41.6
33.3
34.3
37.3
44.43
33.33
Disabled
Enabled
(low)
5
4
3
9
-
PCICLK2
-
1
0
1
6:4
(Reserved)
Disabled
(low)
(Reserved)
0
7
PCICLK1
Enabled
Disabled
(low)
2
6
PCICLK0
1
Enabled
0 - Frequency is selected by
1
0
-
-
-
-
0
0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
3
2
hardware select SEL100/66.6#
1 - Frequency is selected by 6:4 above
(Reserved)
0
Notes: 1 = Enabled; 0 = Disabled, outputs held low
00 - Normal operation
01 - Test mode
10 - Spread sprectrum ON
11 - Tristate all outputs
10
00
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte4:
Byte6:
Description
Bit Value = 0 Bit Value = 1
Description
Bit Value = 0 Bit Value = 1
Bit Pin# Pin Name PWD
Bit Pin# Pin Name PWD
7
6
5
4
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Disabled
(low)
(Reserved)
(Disabled)
(low)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
7
6
5
4
3
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Disabled)
(low)
(Reserved)
(Disabled)
(low)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
2
1
0
23
-
CPUCLK1
-
1
0
1
Enabled
(Reserved)
Enabled
2
1
0
26
-
REF1
-
1
0
1
Enabled
(Reserved)
Enabled
24
CPUCLK0
28
REF0
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
4
ICS9148-46
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
Input High Voltage
VDD+0.3
V
V
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
VIL
VSS-0.3
0.8
5
IIH
VIN = VDD
0.1
2.0
-100
60
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
A
µ
IIL2
-200
A
µ
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
170
170
650
mA
mA
Supply Current
Power Down
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
66
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
3
A
µ
Supply Current
Input frequency
Fi
VDD = 3.3 V;
14.318
36
MHz
pF
CIN
Logic Inputs
5
45
3
Input Capacitance1
CINX
Ttrans
Ts
X1 & X2 pins
27
1
pF
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
ns
5
TSTAB
3
4
TAGP-PCI1 VT = 1.5 V;
3.5
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V+/-5%, VDDL = 2.5 V+/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
IDD2.5OP66
CONDITIONS
MIN
TYP
16
MAX UNITS
CL = 0 pF; Select @ 66.8 MHz
72
mA
mA
Supply Current
IDD2.5OP100 CL = 0 pF; Select @ 100 MHz
23
100
Power Down Supply
Current
CL = 0 pF; With input address to
IDD2.5PD
10
100
A
µ
Vdd or GND
tCPU-AGP
0
1
0.5
2.6
1
4
ns
ns
Skew1
tCPU-PCI2
VT = 1.5 V; VTL = 1.25 V
1Guaranteed by design, not 100% tested in production.
5
ICS9148-46
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP MAX UNITS
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
2.3
0.2
-41
37
V
V
0.4
-19
mA
mA
ns
IOL2B
19
45
1
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.25
1
1.6
1.6
tr2B
1
Fall Time
ns
tf2B
1
Duty Cycle
48
55
%
dt2B
1
Skew
VT = 1.25 V
30
175
250
150
+250
ps
tsk2B
1
Jitter, Cycle-to-cycle
Jitter, One Sigma
Jitter, Absolute
VT = 1.25 V
150
40
ps
tjcyc-cyc2B
1
VT = 1.25 V
ps
tj1s2B
1
VT = 1.25 V
-250
140
ps
tjabs2B
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
VOH1
VOL1
IOH1
CONDITIONS
MIN
2.4
TYP MAX UNITS
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew1
Jitter, One Sigma1
Jitter, Absolute1
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
3.1
0.1
-62
57
V
V
0.4
-22
mA
mA
ns
IOL1
16
45
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
2
tf1
dt1
1.1
50
2
ns
%
ps
ps
ps
55
tsk1
tj1s1
tjabs1
VT = 1.5 V
140
17
500
150
500
VT = 1.5 V
VT = 1.5 V
-500
70
1Guaranteed by design, not 100% tested in production.
6
ICS9148-46
Electrical Characteristics - REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
MIN
2.6
TYP MAX UNITS
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Jitter, One Sigma1
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
3.1
0.17
-44
42
V
V
0.4
-22
mA
mA
ns
IOL5
29
47
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
2
2
tf5
1.1
54
1
ns
%
%
%
dt5
57
3
tj1s5
VT = 1.5 V
Jitter, Absolute1
tjabs5
VT = 1.5 V
3
5
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48, 24 MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
MIN
2.6
TYP MAX UNITS
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Jitter, One Sigma1
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
3
V
V
0.14
-44
42
0.4
-22
mA
mA
ns
IOL5
16
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.2
4
4
tf5
1.2
52
1
ns
%
%
%
dt5
55
3
tj1s5
VT = 1.5 V
Jitter, Absolute1
tjabs5
VT = 1.5 V
3
5
1Guaranteed by design, not 100% tested in production.
7
ICS9148-46
GeneralLayoutPrecautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
3 Optional crystal load capacitors are
recommended.
CapacitorValues:
C1, C2 : Crystal load values determined by user
All unmarked capacitors are 0.01µF ceramic
8
ICS9148-46
COMMON
DIMENSIONS
D
VARIATIONS
SYMBOL
MIN.
NOM.
MAX.
N
MIN.
NOM.
MAX.
A
A1
A2
b
0.068
0.002
0.066
0.010
0.004
0.073
0.005
0.078
0.008
0.070
0.015
0.008
14
16
20
24
28
30
0.239
0.239
0.278
0.318
0.397
0.397
0.244
0.244
0.284
0.323
0.402
0.402
0.249
0.249
0.289
0.328
0.407
0.407
0.068
0.012
c
0.006
D
E
See Variations
0.209
0.205
0.212
e
0.0256 BSC
0.307
H
L
0.301
0.025
0.311
0.037
0.030
N
See Variations
4°
0°
8°
28 Pin SSOP Package
Ordering Information
ICS9148yF-46
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
9
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