ICS9248-50 [ICSI]
Frequency Timing Generator for Pentium II Systems; 频率时序发生器奔腾II系统
| 型号： | ICS9248-50 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for Pentium II Systems |
| 文件： | 总11页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-50
Frequency Timing Generator for Pentium II Systems
General Description
Features
•
Generates the following system clocks:
The ICS9248-50 is the Main clock solution for Notebook
designs using the Intel 440BX style chipset. Along with an
SDRAM buffer such as the ICS9179-03, it provides all
necessary clock signals for such a system.
- 2 CPU (2.5V) up to 100MHz.
- 6 PCI (3.3V) @ 33.3MHz (Includes one free running).
- 2 REF clks (3.3V) at 14.318MHz.
Skew characteristics:
Spread spectrum may be enabled by driving pin 26, SPREAD#
active (Low) at power-on. Spread spectrum typically reduces
systemEMIby8dBto10dB. ThissimplifiesEMIqualification
without resorting to board design iterations or costly shielding.
The ICS9248-50 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.
•
- CPU – CPU<175ps
- PCI – PCI < 500ps
- CPU(early) – PCI = 1.5ns – 4ns.
•
•
•
•
Supports Spread Spectrum modulation for CPU and PCI
clocks, 0.5% down spread
Efficient Power management scheme through stop
clocks and power down modes.
Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal.
28-pin (209 mil) SSOP and (6.1mm) TSSOP package
Block Diagram
Pin Configuration
28-Pin SSOP & TSSOP
Power Groups
VDD, GND=PLLcore
VDDREF, GNDREF=REF(0:1), X1, X2
VDDPCI, GNDPCI=PCICLK_F, PCICLK(0:4)
VDD48, GND48 = 48MHz, 48/24MHz
Pentium is a trademark on Intel Corporation.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-50 Rev - H 03/19/01
information being relied upon by the customer is current and accurate.
ICS9248-50
Pin Descriptions
Pin number
Pin name
Type
Description
1
GNDREF
Power Ground for 14.318 MHz reference clock outputs
2
X1
Input 14.318 MHz crystal input
3
X2
Output 14.318 MHz crystal output
4
PCICLK_F
PCICLK (1:5)
GNDPCI
VDDPCI
VDD48
Output 3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
5,6,9,10,11
Output 3.3 V PCI clock outputs, generating timing requirements for Pentium II
ꢀ
7
8
12
13
Power Ground for PCI clock outputs
Power 3.3 V power for the PCI clock outputs
Power 3.3 V power for 48/24 MHz clocks
Output 3.3 V 48 MHz clock output, fixed frequency clock typically used with USB devices
48 MHz
3.3 V 48 or 24 MHz output and Tri-state option, active low = tri state mode for testing,
active high = normal operation
Power Ground for 48/24 MHz clocks
14
15
TS#/48/24MHz
GND48
Output
control for the frequency of clocks at the CPU & PCICLK output pins. If logic "0" is
used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100 MHz
frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both
16
SEL 100/66#
Input
selected cases.
Asynchronous active low input pin used to power down the device into a low power
17
18
PD#
Input
Input
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
CPU_STOP#
19
20
VDD
Power Isolated 3.3 V power for core
Synchronous active low input used to stop the PCICLK in active low state. It will not
PCI-Stop#
Input
effect PCICLK_F or any other outputs.
21
22
GND
GNDL
Power Isolated ground for core
Power Ground for CPU clock outputs
23,24
25
CPUCLK(1:0)
VDDL
Output 2.5 V CPU clock outputs
Power 2.5 V power for CPU clock outputs
3.3 V 14.318 MHz reference clock output and power-on spread spectrum enable
26
REF1/SPREAD# Output option. Active low = spread spectrum clocking enable. Active high = spread spectrum
clocking disable.
3.3 V 14.318 MHz reference clock output and power-on 48/24 MHz select option.
Active low = 48 MHz output at pin 14. Active high = 24 MHz output at pin 14.
Power 3.3 V power for 14.318 MHz reference clock outputs.
27
28
REF0/SEL48#
VDDREF
Output
2
ICS9248-50
Select Functions
(Functionality determined by TS# and SEL100/66# pin, see below)
PCI,
PCI_F
Functionality
CPUCLK
REF0
Tristate
HI - Z
HI - Z
HI - Z
Testmode
TCLK/21
TCLK/61
TCLK1
Notes:
1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
SEL 100/66#
TS#
Function
Tri-State
0
0
0
0
1
1
1
1
0
-
(Reserved)
-
(Reserved)
1
0
-
Active 66.6MHz CPU, 33.3 PCI
Test Mode
(Reserved)
-
(Reserved)
1
Active 100MHz CPU, 33.3 PCI
Power Management
Clock Enable Configuration
CPU_STOP# PCI_STOP# PWR_DWN#
CPUCLK
Low
PCICLK PCICLK_F
REF
Crystal
Off
VCOs
Off
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
Stopped
Low
33.3MHz
Running Running Running
Running Running Running
Running Running Running
Running Running Running
Low
33.3 MHz 33.3MHz
Low 33.3MHz
100/66.6MHz
100/66.6MHz 33.3 MHz 33.3MHz
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running
clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging
circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-50 Power Management Requirements
Latency
SIGNAL
SIGNAL STATE
No. of rising edges of free running
PCICLK
CPU_ STOP#
0 (Disabled)2
1 (Enabled)1
0 (Disabled)2
1
1
1
PCI_STOP#
PD#
1 (Enabled)1
1 (Normal Operation)3
0 (Power Down)4
1
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
3
ICS9248-50
CPU_STOP#Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-50. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a
low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4
CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9248-50.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP#Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-50. It is used to turn off the PCICLK (0:4) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-50 internally. The minimum that the PCICLK (0:4) clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with
a full high pulse width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
4
ICS9248-50
PD#Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9248-50 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When
PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The
power on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP#
and CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
5
ICS9248-50
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
IIH
VIN = VDD
0.1
2.0
-100
60
µ
µ
µ
A
A
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
180
180
mA
mA
Operating
66
Supply Current
IDD2.5OP 66 CL = 0 pF; Select @ 66.8 MHz
IDD2.5OP 100 CL = 0 pF; Select @ 100 MHz
16
23
72
mA
mA
100
Power Down
Supply Current
Input frequency
IDD3.3PD
CL = 0 pF; With input address to Vdd or GND
70
600
A
µ
Fi
CIN
VDD = 3.3 V;
11
27
14.318
16
5
MHz
pF
Input Capacitance1
Logic Inputs
CINX
X1 & X2 pins
36
3
45
3
pF
Transition Time1
Clk Stabilization1
Skew1
Ttrans
TSTAB
TCPU-PCI
To 1st crossing of target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ns
3
1.5
4
VT = 1.5 V; VTL = 1.25 V
6
ICS9248-50
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
1.8
TYP
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
2.3
0.31
0.4
-27
V
mA
mA
ns
IOL2B
27
0.4
0.4
44
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.15
1.4
1.6
1.6
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
48
55
%
1
Skew
tsk2B
VT = 1.25 V
134
10
175
10.5
200
+250
ps
Jitter
period(norm) VT = 1.25 V; 100MHz
10
ns
1
Jitter
tjcyc-cyc2B
VT = 1.25 V
VT = 1.25 V
186
150
ps
1
tjabs2B
Jitter, Absolute
-250
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF/48MHz/24MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP
3.1
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.17
-44
42
0.4
-22
V
IOH5
mA
mA
IOL5
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
1.1
4
4
ns
ns
dt5
tj1
53
55
%
ps
ps
ps
ps
VT = 1.5 V, REF
185
385
169
469
250
800
250
800
5
σ
Jitter1
Jitter1
tjabs5
tj1
VT = 1.5 V, REF
5
VT = 1.5 V, 48 MHz
VT = 1.5 V, 48 MHz
σ
tjabs5
7
ICS9248-50
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.1
TYP
3.3
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.1
0.4
-22
57
V
IOH1
mA
mA
IOL1
16
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.6
1.8
50
2
2
ns
ns
%
dt1
55
tsk1
tjcyc-cyc
tj1s
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
222
186
52
500
500
150
500
ps
ps
ps
ps
Jitter1
tjabs
200
1Guaranteed by design, not 100% tested in production.
8
ICS9248-50
General Layout Precautions:
1) Use a ground plane on the top layer of the
PCB in all areas not used by traces.
2) Make all power traces and vias as wide as
possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in
all places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
3 Optional crystal load capacitors are
recommended.
CapacitorValues:
C1, C2 : Crystal load values determined by user
All unmarked capacitors are 0.01µF ceramic
9
ICS9248-50
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
2.00
-
MIN
-
MAX
.079
-
A
A1
A2
b
0.05
1.65
0.22
0.09
.002
.065
.009
.0035
1.85
0.38
0.25
.073
.015
.010
c
SEE VARIATIONS
SEE VARIATIONS
D
E
7.40
5.00
8.20
5.60
.291
.197
.323
.220
E1
e
0.65 BASIC
0.0256 BASIC
L
0.55
0.95
.022
.037
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
MIN
MAX
3.30
6.50
6.50
7.50
7.50
8.50
8.50
10.50
10.50
12.90
8
2.70
5.90
5.90
6.90
6.90
7.90
7.90
9.90
9.90
12.30
.106
.232
.232
.271
.271
.311
.311
.390
.390
.484
.130
.256
.256
.295
.295
.335
.335
.413
.413
14
16
18
20
22
24
28
30
38
.508
6/1/00 Rev B
MO-150 JEDEC
Doc.# 10-0033
Ordering Information
ICS9248yF-50-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
10
information being relied upon by the customer is current and accurate.
ICS9248-50
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
MIN
-
MAX
.047
.006
.041
.012
.008
A
A1
A2
b
0.05
0.80
0.19
0.09
.002
.032
.007
.0035
c
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319
D
E
E1
e
6.00
6.20
0.65 BASIC
0.75
.236
.244
0.0256 BASIC
L
0.45
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
0°
-
8°
0°
-
8°
α
aaa
0.10
.004
VARIATIONS
D mm.
D (inch)
N
MIN
9.60
MAX
9.80
MIN
.378
MAX
6.10 mm. Body, 0.65 mm. pitch TSSOP
(0.0256 mil)
28
.386
7/6/00 Rev B
(240 mil)
MO-153 JEDEC
Doc.# 10-0038
Ordering Information
ICS9248yG-50-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
11
information being relied upon by the customer is current and accurate.
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