ICS9248YF-72 [ICSI]
Frequency Timing Generator for PENTIUM II Systems; 频率时序发生器奔腾II系统
| 型号： | ICS9248YF-72 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for PENTIUM II Systems |
| 文件： | 总12页 (文件大小：554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-72
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Timing Generator for PENTIUM II Systems
General Description
Features
The ICS9248-72 is a main clock synthesizer chip for Pentium
II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used
with a Direct Rambus Clock Generator(DRCG) chip such as
theICS9211-01.
Up to 200MHz frequency support.
Power Down feature.
Spread Spectrum for EMI control
(0 to 0.5% down spread , + 0.25% center spread)
I2Cinterface.
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dBto10dB. ThissimplifiesEMIqualificationwithoutresorting
to board design iterations or costly shielding. The ICS9248-
72 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
VDDL=2.5V,VDD=3.3V
Key Specification
CPU Output Jitter: <250ps
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCIOutputJitter:<500ps
Ref Output Jitter. <1000ps
CPUOutputSkew:<175ps
IOAPIC Output Skew <250ps
PCI Output Skew: <500ps
3V66OutputSkew<250ps
The CPU/2 clocks are inputs to the DRCG.
CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
Block Diagram
Pin Configuration
48-pin SSOP
* 250K ohm pull-up to VDD on indicated inputs.
1.These pins will have 2X drive strength
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
9248-72RevB7/28/99
ICS9248-72
Preliminary Product Preview
Power Groups:
VDDREF,GNDREF=REF,X1,X2
GNDPCI,VDDPCI=PCICLK
VDD66,GND66=3V66
VDD48,GND48=48MHz
VDDCOR,GNDCOR=PLLCore
VDDLCPU/2,GNDLCPU/2=CPU/2
VDDLIOAPIC,GNDIOAPIC=IOAPIC
Pin Descriptions
Pin number
Pin name
IOAPIC[2:0]
REF0
Type
Description
1, 45, 46
Output 2.5VIOAPIC clock outputs
Output 3.3V, 14.318 MHz reference clock output.
Power 3.3 Vpower
2
3, 24, 29, 33
VDD
4
5
X1
X2
GND
Input 14.318 MHz crystal input
Output 14.318 MHz crystal output
Power Ground
6, 14, 20, 26, 32
FS [2:1]
PCICLK[1:0]
VDDPCI
IN
Frequency select pins. Latched Inputs determins the CPU&PCI frequencies.
8, 7
Output 3.3 VPCI clock outputs, generating timing requirements for
Power 3.3 Vpower for the PCI clock outputs
9,17
19, 18, 16, 15, 13,
12, 11, 10
PCICLK[9:2]
3V66
Output 3.3 VPCI clock outputs
23, 22, 21
Output 3.3 V66 MHz clock output, fixed frequency clock typically used with AGP
control for the frequency of clocks at the CPUoutput pins. If logic "0" is used the
Input 100 MHz frequency is selected. If Logic "1" is used, the 133 MHz frequency is
selected. The PCI clock is multiplexed to run at 33.3 MHz for both selected cases.
25
27
28
SEL 133/100#
FS0
IN
Frequency select pin. Latched Inputs determins the CPU&PCI frequencies.
3.3 V48 MHz clock output, fixed frequency clock typically used with USB
devices
48 MHz
Output
48/24 MHz select option. Active low = 48 MHz output. Active High = 24
SEL24/48
IN
MHz
3.3V 48 or 24 MHz clock output, fixed frequency clock typically used with
USB devices.
24_48MHz#
Output
30
31
SCLK
IN
Clock input of I2C input
Asynchronous active lowinput pin used to power down the device into a low
PD#
Input power state. The internal clocks are disabled and the VCOand the crystal are
stopped.
Data input for I2C serial input.
IN
0utput 2.5 VCPUand Host clock outputs
Power 2.5 V power for the CPU and Host clock outputs
Power Ground for the CPUand Host clock outputs
Output output running at 1/2 CPUclock frequency.Synchronous to the CPUoutputs.
Power 2.5 Vpower for the CPU/2 clock outputs
Power Ground for IOAPIC clocks
34
36, 35
37, 40
41
42
43
SDATA
CPUCLK[1:0]
VDDLCPU
GNDLCPU/2
CPU/2
VDDLCPU/2
GNDLIOAPIC
GNDREF
47
48
Power Ground for 14.318 MHz reference clock outputs
2
ICS9248-72
Preliminary Product Preview
Functionality
VDD =3.3V±5%,VDDL = 2.5V±5% TA=0 to 70°C
Crystal(X1,X2)=14.31818MHz
FS2
(MHz)
1
FS1
(MHz)
FS0
(MHz)
CPU
CPU/2
(MHz)
66.65
69.01
71.45
73.98
76.24
78.49
81.01
89.99
50.11
52.49
56.99
59.99
64.25
100.00
85.01
33.40
PCI
(MHz)
33.325
34.505
35.725
36.99
38.12
39.245
40.505
30.00
33.405
35
37.83
40.00
32.125
33.33
28.33
33.40
3V66
(MHz)
66.65
69.01
71.45
73.98
76.24
78.49
81.01
60.00
66.81
70.00
75.66
80.00
64.25
66.66
56.66
66.80
IOAPIC
(MHz)
16.66
17.25
17.86
18.49
19.06
19.62
20.25
15.00
16.70
17.50
18.91
20.00
16.06
16.66
14.16
16.7
SEL133/100#
(MHz)
133.30
138.01
142.91
147.95
152.49
156.99
162.02
180.00
100.23
105.00
113.99
120.00
128.51
200.01
170.03
66.82
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
ICS9248-72 Power Management Features:
REF.
48MHz
PD#
CPUCLK CPU/2 IOAPIC 3V66 PCI PCI_F
Osc VCOs
0
1
LOW
ON
LOW
ON
LOW
ON
LOW LOW LOW
ON ON ON
LOW
ON
OFF
ON
OFF
ON
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
Power Management Requirements:
Latency
Singal
Singal State
No. of rising edges
of PCICLK
1 (normal operation)
0 (power down)
3mS
PD#
2max.
Note:
1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/
high to the first valid clock comes out of the device.
2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
3
ICS9248-72
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
4
ICS9248-72
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0:FunctionalityandFrequencySelectRegister(default=0)
Bit
Description
PWD
Bit
CPUCLK
CPU/2
3V66
PCICLK
IOAPIC
0
7
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
6
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
5
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
4
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
133.30
138.01
142.91
147.95
152.49
156.99
162.02
180.00
100.23
105.00
113.99
120.00
128.51
200.01
170.03
66.82
66.65
69.01
71.45
73.98
76.24
78.49
81.01
89.99
50.11
52.49
56.99
59.99
64.25
100.00
85.01
33.40
66.65
69.01
71.45
73.98
76.24
78.49
81.01
60.00
66.81
70.00
75.66
80.00
64.25
66.66
56.66
66.80
33.325
34.505
35.725
36.99
38.12
39.245
40.505
30.00
33.405
35
16.66
17.25
17.86
18.49
19.06
19.62
20.25
15.00
16.70
17.50
18.91
20.00
16.06
16.66
14.16
16.7
Bit
(7:4)
XXXX
Note1
37.83
40.00
32.125
33.33
28.33
33.40
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 7:4
0- Spread spectrum center spread type ±0.25%
1- Spread spectrum down spread type 0 to - 0.5%
0- Normal
1- Spread spectrum enable
Bit3
Bit2
Bit1
Bit0
0
1
1
0
0= Running
1= Tristate all outputs
Note1: Default at power-up will be for latched logic inputs to define frequency.
5
ICS9248-72
Preliminary Product Preview
Byte1:CPU, CPU/2, 48MHzRegister
(1 = enable, 0 = disable)
Byte2:PCICLKActive/InactiveRegister
(1 = enable, 0 = disable)
Bit
Pin # PWD
Description
Bit
Pin #
27
28
-
42
-
39
36
35
PWD
Description
48MHz
24_48 MHz
(Reserved)
CPU/2
(Reserved)
CPUCLK 2
CPUCLK 1
CPUCLK 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16
15
13
12
11
10
8
1
1
1
1
1
1
1
1
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
-
1
-
1
1
1
7
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte3:3V66, REF RegisterActive/Inactive
(1 = enable, 0 = disable)
Byte4:IOAPIC, REFRegisterActive/Inactive
(1 = enable, 0 = disable)
Bit
Pin #
-
23
22
21
-
-
19
18
PWD
0
1
1
1
X
X
1
Description
(Reserved)
3V66_2
3V66_1
3V66_0
Bit
Pin #
PWD
0
1
1
1
Description
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
45
46
-
-
-
IOAPIC2
IOAPIC1
IOAPIC0
(Reserved)
FS0#
FS2#
0
(SEL24 48#)#
PCICLK9
PCICLK8
X
X
1
FS1#
REF (X2)
1
2
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte5:CPU, IOAPICRegisterActive/Inactive
(1 = enable, 0 = disable)
Bit
Pin #
PWD
Description
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
6
ICS9248-72
Preliminary Product Preview
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP#
are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in
the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the
LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
7
ICS9248-72
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Group Offset
Group
Offset
Measurement Loads
CPU @ 20pF, 3V66 @ 30pF
3V66 @ 30pF, PCI @ 30pF
Measure Points
CPU @1.25V, 3V66 @ 1.5V
3V66 @ 1.5V, PCI @ 1.5V
CPU to 3V66
3V66 to PCI
CPU to IOAPIC
0.0-1.5ns CPU leads
1.5-4.0ns 3V66 leads
1.5-4.0ns CPU leads
CPU @ 20pF, IOAPIC @ 20pF CPU @1.25V, IOAPIC @ 1.5V
Note: 1. All offsets are to be measured at rising edges.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
-5
0.8
5
A
µ
IIH
VIN = VDD
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
A
µ
IIL2
IDD3.3OP CL = 0 pF; Select
mA
Supply Current
Power Down
A
µ
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
Supply Current
Input frequency
Pin Inductance
Fi
VDD = 3.3 V;
14.318
MHz
nH
pF
Lpin
CIN
7
5
6
Input Capacitance1
Logic Inputs
Cout
CINX
Ttrans
Ts
Out put pin capacitance
X1 & X2 pins
pF
27
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
mS
mS
mS
nS
TSTAB
3
t
PZH,tPZH output enable delay (all outputs)
1
1
10
10
Delay
tPLZ,tPZH
output disable delay (all outputs)
nS
1Guarenteed by design, not 100% tested in production.
8
ICS9248-72
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
13.5
2
TYP MAX UNITS
1
RDSP2B
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
45
Ω
V
VOH2B
VOL2B
IOH2B
IOL2B
0.4
-27
30
V
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 0.4 V, VOL = 2.0 V
VT = 1.25 V
-27
27
mA
mA
ns
1
tr2B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
ns
1
Skew
tsk2B
VT = 1.25 V
175
250
ps
1
Jitter
VT = 1.25 V
ps
tjcyc-cyc
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - CPU/2
TA = 0 - 70C, VDDL = 2.5 V+/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output LowCurrent
Rise Time
SYMBOL
CONDITIONS
MIN
13.5
2
TYP MAX UNITS
1
RDSP2B
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
45
Ω
V
VOH2B
VOL2B
IOH2B
IOL2B
0.4
-27
30
V
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V, VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 0.4 V, VOL = 2.0 V
VT = 1.25 V
-27
27
mA
mA
ns
1
tr2B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
ns
1
Jitter
VT = 1.25 V
250
ps
tjcyc-cyc
1Guarenteed by design, not 100% tested in production.
9
ICS9248-72
Preliminary Product Preview
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
2.0
2.0
55
1
Fall Time
tf1
1
Duty Cycle
dt1
1
Skew
tsk1
VT = 1.5 V
VT = 1.5 V
250
500
ps
ps
tjcyc-cyc
Jitter
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V+/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output LowVoltage
Output High Current
Output LowCurrent
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-23
27
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -29
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
29
0.5
0.5
45
1
tr1
2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
VT = 1.5 V
500
500
ps
ps
tjcyc-cyc
Jitter
1Guarenteed by design, not 100% tested in production.
10
ICS9248-72
Preliminary Product Preview
Electrical Characteristics - 48M, REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output LowCurrent
Duty Cycle
SYMBOL
CONDITIONS
MIN
20
TYP MAX UNITS
1
RDSP5
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = 1 mA
60
60
Ω
Ω
1
RDSN5
20
VOH5
VOL5
IOH5
IOL5
2.4
V
IOL = -1 mA
0.4
-23
V
VOH @MIN=1 V, VOH@MAX= 3.135 V
VOL@MIN=1.95 V, VOL@MIN=0.4 V
VT = 1.5 V
-29
29
45
mA
mA
%
27
1
dt5
55
1
Jitter
tjcyc-cyc
VT = 1.5 V; Fixed Clocks
500
1000
N/A
ps
ps
ps
1
tjcyc-cyc
VT = 1.5 V; Ref Clocks
VT = 1.5 V,Fixed Clocks
Tsk
Skew
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 40 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
13.5
2
TYP MAX UNITS
1
RDSP2B
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
45
Ω
V
VOH2B
VOL2B
IOH2B
IOL2B
0.4
-27
30
V
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 0.4 V, VOL = 2.0 V
VT = 1.25 V
-27
27
mA
mA
ns
1
tr2B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
ns
1
Skew
tsk2B
VT = 1.25 V
250
500
ps
1
tjcyc-cyc
VT = 1.25 V
Jitter
ps
1Guarenteed by design, not 100% tested in production.
11
ICS9248-72
Preliminary Product Preview
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
MIN.
.620
NOM. MAX.
A
A1
A2
B
AC
.625
.630
48
C
D
E
See Variations
.296
.292
.299
e
H
h
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
48 Pin SSOP Package
L
.032
N
See Variations
0°
5°
8°
X
.085
.093
.100
Ordering Information
ICS9248yF-72
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
RevisionDesignator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
12
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