ICS9248YF-73-T [ICSI]
Frequency Timing Generator for Pentium II Systems; 频率时序发生器奔腾II系统
| 型号： | ICS9248YF-73-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for Pentium II Systems |
| 文件： | 总15页 (文件大小：357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-73
Frequency Timing Generator for Pentium II Systems
General Description
The ICS9248-73 is a single chip clock for Intel Pentium II.
Features
Generates the following system clocks:
- 2 - CPUs @ 2.5V , up to 150MHz.
-1-IOAPIC@2.5V, PCI/2MHz.
- 9 - SDRAMs @ 3.3V, up to 150MHz.
-2-3V66@3.3V,2xPCIMHz.
-8-PCIs@3.3V.
-2-48MHz, @3.3Vfixed.
It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board
design iterations or costly shielding. The ICS9248-73
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
-1-REF@3.3V,14.318MHz.
-1-24_48MHz, @3.3Vfixed.
Supports spread spectrum modulation ,
down spread 0 to -0.5%, ±0.25% center spread.
I2C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Block Diagram
Pin Configuration
48-Pin 300 mil SSOP
*120K ohm pull-up to VDD on indicated inputs.
**60K ohm pull-up to VDD on indicated inputs.
1. These pins will have 2x drive strength
Power Groups
GNDREF,VDDREF =REF&Crystal
GND3V66,VDD3V66 =3V66
GNDPCI,VDDPCI=PCICLK
GNDCOR,VDDCOR=PLLcore
GND48,VDD48 =48MHz
GNDSDR,VDDSDR=SDRAM
GNDLCPU,VDDLCPU=CPUCLK
GNDAPIC,VDDAPIC=IOAPIC
PentiumII is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-73 Rev B 2/10/00
information being relied upon by the customer is current and accurate.
ICS9248-73
Pin Descriptions
PIN
NUMBER
PIN NAME
TYPE
DESCRIPTION
SEL_3V66
REF0
IN
This pin selects the 3V66 output frequency.
1
OUT 3.3V, 14.318MHz reference clock output.
2, 9, 10,
18, 25, 30, 38
VDD
X1
PWR 3.3V power supply
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
3
4
IN
Crystal output, nominally 14.318MHz.
Has internal load cap (33pF)
X2
OUT
5, 6, 14, 21,
29, 42, 34,
GND
PWR Ground pins for 3.3V supply
7, 8
3V66 (0:1)
OUT 3.3V clock outputs for HUB running at 2XPCI MHz
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
PCICLK0
FS0
11
IN
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
IN Logic input frequency select bit. Input latched at power on.
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
IN Logic input to select output.
Logic input frequency select bit. Input latched at power on.
PCICLK1
12
13
FS1
PCICLK2
SEL24_48#
15, 16, 17,
19, 20
PCICLK (3:7)
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
22
PD#
IN
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
23
24
SCLK
IN
IN
Clock input of I2C input
SDATA
48MHz
FS3
Data input for I2C serial input.
OUT 3.3V Fixed 48MHz clock output for USB
IN Logic input frequency select bit. Input latched at power on.
26
27
28
48MHz
24_48MHz
FS2
OUT 3.3V Fixed 48MHz clock output for USB
OUT 24 or 48MHz output controlled by SEL24_48#.
IN
Logic input frequency select bit. Input latched at power on.
29
31
GND48
SDRAM_F
PWR Ground for 48MHz outputs
OUT 3.3V free running 100MHz SDRAM not affected by I2C
41, 40, 39, 37,
36, 35, 33, 32,
3.3V output running 100MHz. All SDRAM outputs can be turned off
SDRAM (0:7)
GNDL
OUT
through I2C
43
PWR Ground for 2.5V power supply for CPU & APIC
2.5V Host bus clock output, up to 150MHz depending on FS (0:3)
pins Refer page 3.
45, 44
CPUCLK (0:1)
OUT
47
IOAPIC
VDDL
OUT 2.5V clock outputs running at PCI/2 MHz.
PWR 2.5V power suypply for CPU, IOAPIC
48, 46
2
ICS9248-73
Frequency Selection
3V66 MHz
SEL_3V66=0
CPU SDRAM PCI
MHz MHz MHz
FS3 FS2 FS1 FS0
IOAPIC MHz
SEL_3V66=1
66.82
67.26
70.00
66.89
80.00
82.66
88.86
66.65
70.00
75.00
76.66
70.00
75.00
83.31
60.00
63.33
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.23 100.23 33.41
100.90 100.90 33.63
105.00 105.00 35.00
66.89 100.33 33.44
120.00 120.00 40.00
124.00 124.00 41.33
133.30 133.30 44.43
133.30 133.30 33.32
140.00 140.00 35.00
150.00 150.00 37.50
114.99 114.99 38.33
70.00 105.00 35.00
75.00 112.50 37.50
83.31 124.96 41.65
66.82
67.26
16.70
16.81
17.50
16.72
20.00
20.67
22.21
16.66
17.50
18.75
19.16
17.50
18.75
20.83
15.00
15.83
70.00
66.89
64.00*
64.00*
64.00*
66.65
70.00
64.00*
64.00*
70.00
64.00*
64.00*
60.00
90.00
95.00
90.00
95.00
30.00
31.67
63.33
Note:
* These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation.
Clock Enable Configuration
REF,
PD#
CPUCLK SDRAM IOAPIC
66MHz
PCICLK
Osc
VCOs
48MHz
LOW
ON
0
1
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
OFF
ON
OFF
ON
3
ICS9248-73
Byte0:Functionalityandfrequencyselectregister(Default=0)
(1 = enable, 0 = disable)
Bit
PWD
0
Description
0 - ±0.25% Center Sperad Spectrum
1-Down Spread Spectrum 0 to -0.5%
Bit 7
3V66 MHz
SEL_3V66=0 SEL_3V66=1
Bit
(2, 6:4)
CPUCLK SDRAM PCICLK
MHz
IOAPIC MHz
MHz
MHz
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
100.23
100.90
105.00
66.89
100.23
100.90
105.00
100.33
120.00
124.00
133.30
133.30
140.00
150.00
114.99
105.00
112.50
124.96
90.00
33.41
33.63
35.00
33.44
40.00
41.33
44.43
33.32
35.00
37.50
38.33
35.00
37.50
41.65
30.00
31.67
66.82
67.26
66.82
67.26
70.00
66.89
80.00
82.66
88.86
66.65
70.00
75.00
76.66
70.00
75.00
83.31
60.00
63.33
16.70
16.81
17.50
16.72
20.00
20.67
22.21
16.66
17.50
18.75
19.16
17.50
18.75
20.83
15.00
15.83
70.00
66.89
120.00
124.00
133.30
133.30
140.00
150.00
114.99
70.00
64.00*
64.00*
64.00*
66.65
Bit
(2, 6:4)
XXXX
Note 1
70.00
64.00*
64.00*
70.00
75.00
64.00*
64.00*
60.00
83.31
90.00
95.00
95.00
63.33
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 6:4
Bit 3
Bit 1
Bit 0
0
0
0
0 - Normal
1 - Spread spectrum enable
0 - Running
1 - Tristate all outputs
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are default to 0000.
* These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation.
4
ICS9248-73
Byte 2: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
FS3#
Bit
Pin# PWD
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
28
27
26
-
X
X
X
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
32
33
35
36
37
39
40
41
1
1
1
1
1
1
1
1
FS0#
FS2#
24-48MHz
48MHz
48MHz
0
(Reserved)
SDRAM_F
31
1
Byte 3: Control Register
(1 = enable, 0 = disable)
Byte 4: Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Bit
Pin# PWD
Description
(Reserved)
3V66_0
3V66_1
SEL_3V66#
IOAPIC
FS1#
CPUCLK1
CPUCLK0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
19
17
16
15
13
12
11
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
7
0
1
8
1
-
47
-
44
45
X
1
X
1
1
1
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
5
ICS9248-73
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
µA
IIH
VIN = VDD
0.1
2.0
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
A
µ
IIL2
-200
-100
300
300
14
IDD3.3OP66 Select @ 66MHz; Max discrete cap loads
IDD3.3OP100 Select @ 100MHz; Max discrete cap loads
IDD2.5OP66 Select @ 66MHz; Max discrete cap loads
IDD2.5OP100 Select @ 100MHz; Max discrete cap loads
IDD3.3PD CL = 0 pF; PWRDWN# = 0
380
mA
mA
mA
Operating Supply
Current
70
21
100
Power Down
Supply Current
Input frequency
Input Capacitance1
5
10
Fi
VDD = 3.3 V
12
27
14.318
16
5
MHz
pF
pF
ms
ms
ms
ns
CIN
Logic Inputs
CINX
TTrans
TS
X1 & X2 pins
36
1
45
3
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
3
TStab
3
t
PZH, tPZH Output enable delay (all outputs)
1
1
10
10
Delay
tPLZ, tPZH
Output diable delay (all outputs)
ns
1Guaranteed by design, not 100% tested in production.
6
ICS9248-73
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
2.36
0.33
-34
25
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
IOL2B
19
0.4
0.4
40
43
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V; Freq>= 140MHz
VT = 1.25 V; Freq< 140MHz
VT = 1.25 V
1.5
1.4
48
2
1
Fall Time
tf2B
1.8
50
ns
1
dt2B
%
Duty Cycle
48
53
%
1
Skew
tsk2B
50
175
ps
1
tjcyc-cyc2B VT = 1.25 V; CPU @ 66.8 MHz
VT = 1.25 V; CPU @ 100.23 MHz
500
130
Jitter, Cycle-to-cycle
250
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.1
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.18
-55
43
0.4
-22
V
IOH1
mA
mA
IOL1
25
0.5
0.5
45
Rise Time1
Fall Time1
Duty Cycle1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.55
1.4
2
2
ns
ns
dt1
tsk1
48
50
55
%
ps
ps
ps
Skew1
Jitter, Cycle-to-cycle1
Jitter, Cycle-to-cycle1
VT = 1.5 V
175
500
500
tjcyc-cyc1 VT = 1.5 V; 3V66 Freq > 75MHz
tjcyc-cyc1 VT = 1.5 V; 3V66 Freq < 75MHz
100
350
1Guaranteed by design, not 100% tested in production.
7
ICS9248-73
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH4B
VOL4B
IOH4B
CONDITIONS
MIN
2
TYP
2.3
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -8 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.36
-24
23
0.4
-16
V
mA
mA
IOL4B
19
0.4
0.4
45
Rise Time1
Fall Time1
Duty Cycle1
Tr4B
Tf4 B
Dt4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.4
1.45
50
2.1
2.2
55
ns
ns
%
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc4B VT = 1.25 V
140
500
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH3
CONDITIONS
MIN
2.4
TYP
2.9
0.32
-73
50
MAX UNITS
V
IOH = -25 mA
IOL = 20 mA
VOH = 2.0 V
VOL = 0.8 V
VOL3
0.4
-40
V
mA
mA
ns
IOH3
IOL3
41
0.4
0.4
45
1
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.95
1
2
2
1
Fall Time
Tf3
ns
1
Duty Cycle
Dt3
53
55
250
250
%
Skew1
Tsk1
VT = 1.5 V
85
ps
ps
1
tjcyc-cyc3B VT = 1.25 V
Jitter, Cycle-to-cycle
110
1Guarenteed by design, not 100% tested in production.
8
ICS9248-73
Electrical Characteristics - 48MHz/FS3; REF0
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
3.1
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 10 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.19
-55
42
0.4
-22
V
IOH5
mA
mA
IOL5
25
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V, 48MHz/FS3
VT = 1.5 V, REF
1.1
1
4
4
ns
ns
dt5
dt5
45
45
51
52
55
55
%
%
ps
ps
Duty Cycle1
Jitter, Cycle-to-cycle1
Jitter, Cycle-to-cycle1
tjcyc-cyc5 VT = 1.5 V, 48MHz/FS3
tjcyc-cyc5 VT = 1.5 V, REF
190
310
500
1000
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz; 24_48MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
2.9
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 10 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.35
-28
22
0.4
-20
V
IOH5
mA
mA
IOL5
16
1.5
1.5
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2.4
2.2
50
4
4
ns
ns
%
ps
dt5
55
500
Jitter, Cycle-to-cycle1
tjcyc-cyc5 VT = 1.5 V
240
1Guaranteed by design, not 100% tested in production.
9
ICS9248-73
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs
PARAMETER
SYMBOL
VOH1
VOH1
VOL1
VOL1
IOH1
CONDITIONS
IOH = -11 mA; Pci0 & Pci1
IOH = -11 mA
MIN
2.4
TYP
3.2
3.1
0.12
0.2
-110
-55
82
MAX UNITS
Output High Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
Output High Current
Output High Current
Output Low Current
Output Low Current
V
V
2.4
IOL = 9.4 mA; Pci0 & Pci1
IOL = 9.4 mA
0.4
0.4
-22
-22
V
V
VOH = 2.0 V; Pci0 & Pci1
VOH = 2.0 V
mA
mA
mA
mA
ns
IOH1
IOL1
VOL = 0.8 V; Pci0 & Pci1
VOL = 0.8 V
25
25
IOL1
42
tr1
VOL = 0.4 V, VOH = 2.4 V; PCI0:1, CL=60pF
VOL = 0.4 V, VOH = 2.4 V; PCI2:7
VOH = 2.4 V, VOL = 0.4 V; PCI0:1, CL=60pF
VOH = 2.4 V, VOL = 0.4 V; PCI2:7
0.5
0.5
0.5
0.5
1.5
1.7
1.4
1.7
2.3
2.3
2
Rise Time1
ns
tf1
ns
Fall Time1
2
ns
Duty Cycle1
dt1
VT = 1.5 V
45
50
55
%
ps
ps
ps
ps
tsk1
VT = 1.5 V; CL=60pF for Pci0 & PCI1
VT = 1.5 V; CL=50pF for Pci0 & PCI1
VT = 1.5 V; CL=40pF for Pci0 & PCI1
545
360
455
130
Skew1
500
500
Jitter, Cycle-to-cycle1
tjcyc-cyc1 VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
10
ICS9248-73
Group Offset Waveforms
Group Skews at common Transition Edges
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V+/-5%, VDDL = 2.5 V+/-5% (unless otherwise stated)
CL = 20 pF for CPU and IOAPIC
CL = 50 pF for PCI0 & PCI1, CL = 30 pF for other PCIs, SDRAM and 3V66
GROUP
SYMBOL
tCPU-SDRAM VT = 1.5 V; VTL = 1.25 V
SDRAM leads CPU by 2.5ns for CPU66
CPU leads SDRAM by 5.0ns for CPU100
tCPU-3V66 VT = 1.5 V; VTL = 1.25 V
CONDITIONS
MIN
0
TYP
100
MAX UNITS
CPU to SDRAM
500
500
ps
ps
CPU to 3V66
CPU leads 3V66 by 7.5ns for CPU66
CPU leads 3V66 by 0.0ns for CPU100
0
100
IOAPIC to PCI
3V66 to PCI
tIOAPIC-PCI VT = 1.5 V; VTL = 1.25 V
t3V66-PCI VT = 1.5 V
0
360
2.5
500
4
ps
ns
1.5
Guaranteed by design, not 100% tested in production.
11
ICS9248-73
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
12
ICS9248-73
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
13
ICS9248-73
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9248-
73 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K
Via to Gnd
Device
Pad
8.2K
Clock trace to load
Series Term. Res.
Fig. 1
14
ICS9248-73
Pin 1
.093
DIA. PIN (Optional)
D/2
Index
Area
E/2
PARTING LINE
H
L
DETAIL “A”
TOP VIEW
BOTTOM VIEW
-e-
B
A2
c
A
C
.004
SEE
DETAIL “A”
-E-
SEATING
PLANE
-D-
-C-
END VIEW
A1
SIDE VIEW
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.087
.008
.005
NOM.
.102
.012
.090
MAX.
.110
.016
.094
.0135
.010
MIN.
.620
NOM.
.625
MAX.
.630
A
A1
A2
B
AC
48
-
-
c
D
E
e
H
h
L
See Variations
.295
0.025 BSC
.291
.299
“For current dimensional specifications, see JEDEC 95.”
Dimensions in inches
.395
.010
.020
-
.420
.016
.040
.013
-
N
See Variations
0°
-
8°
48 Pin 300 mil SSOP Package
Ordering Information
ICS9248yF-73-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
15
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