ICS9248YF-78 [ICSI]
Frequency Timing Generator for Pentium II Systems; 频率时序发生器奔腾II系统
| 型号： | ICS9248YF-78 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for Pentium II Systems |
| 文件： | 总13页 (文件大小：606K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-78
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Timing Generator for Pentium II Systems
General Description
The ICS9248-78 is a single chip clock for Intel Pentium II.
Features
Generates the following system clocks:
- 2 - CPUs @ 2.5V, up to 150MHz.
-1-IOAPIC@2.5V, PCI/2MHz.
- 9SDRAMs(3.3V), upto150MHz.
-2-3V66@3.3V,2xPCIMHz.
-8-PCIs@3.3V.
-1-48MHz, @3.3Vfixed.
It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board
design iterations or costly shielding. The ICS9248-78
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
-2-REF@3.3V,14.318Hz.
-1-24MHz, @3.3Vfixed.
Supports spread spectrum modulation ,
down spread 0 to -0.5%, ±0.25% center spread.
I2C support for power management.
Efficient power management scheme through PD#.
Uses external 14.138 MHz crystal.
Block Diagram
Pin Configuration
48-Pin 300 mil SSOP
1. These pins will have 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Power Groups
GNDREF,VDDREF=REF,Crystal
GND3V66,VDD3V66=3V66
GNDPCI,VDDPCI=PCICLKs
GNDCOR,VDDCOR=PLLCORE
GND48,VDD48=48
GNDSDR,VDDSDR=SDRAM
GNDLCPU,VDDLCPU=CPUCLK
GNDLPCI,VDDLAPIC=IOAPIC
Pentium II is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
9248-78RevA7/21/99
ICS9248-78
Preliminary Product Preview
Pin Descriptions
PIN
PIN NAME
REF1
TYPE
DESCRIPTION
NUMBER
1
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply
2, 9, 10, 18,
25, 29, 37
VDD
X1
Crystal input, has internal load cap (33pF) and feedback
3
4
IN
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
X2
OUT
cap (33pF)
5, 6, 14, 21, 28,
33, 41
GND
PWR Ground pins for 3.3V supply
7, 8
3V66 (1:0)
PCICLK01
OUT 3.3V clock outputs for HUB running at 2XPCI MHz
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
11
FS0
PCICLK11
IN
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
IN Logic input frequency select bit. Input latched at power on.
Logic input frequency select bit. Input latched at power on.
12
FS1
13, 15, 16,
17, 19, 20
PCICLK (2:7)
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
22
PD#
IN
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
23
24
SCLK
SDATA
48MHz
FS3
IN
IN
Clock input of I2C input
Data input for I2C serial input.
OUT 3.3V Fixed 48MHz clock output for USB
26
IN
IN
Logic input frequency select bit. Input latched at power on.
Logic input frequency select bit. Input latched at power on.
FS2
27
30
24MHz
OUT 3.3V fixed 24MHz output
OUT 3.3V free running SDRAM not affected by I2C
SDRAM_F
40, 39, 38, 36,
35, 34, 32, 31
SDRAM (7:0)
OUT 3.3V outputs
42
GNDL
PWR Ground for 2.5V power supply for CPU & APIC
OUT 2.5V Host bus clock output.
43, 44
CPUCLK (1:0)
45, 47
46
VDDL
PWR 2.5V power suypply for CPU, IOAPIC
OUT 2.5V clock outputs running at PCI/2 MHz
IOAPIC
SEL_3V66
REF01
IN
This pin selects the 3V66 output frequency.
48
OUT 3.3V, 14.318MHz reference clock output.
Note:
1. These pins will have 2X drive strength.
2
ICS9248-78
Preliminary Product Preview
Frequency Selection
3V66 MHz
CPU SDRAM PCI
MHz MHz MHz
FS3 FS2 FS1 FS0
IOAPIC MHz
SEL_3V66=0
66.82
SEL_3V66=1
66.82
67.26
70.00
66.89
80.00
82.66
88.86
66.65
70.00
75.00
76.66
70.00
75.00
83.31
60.00
63.33
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.23 100.23 33.41
100.90 100.90 33.63
105.00 105.00 35.00
66.89 100.33 33.44
120.00 120.00 40.00
124.00 124.00 41.33
133.30 133.30 44.43
133.30 133.30 33.32
140.00 140.00 35.00
150.00 150.00 37.50
114.99 114.99 38.33
70.00 105.00 35.00
75.00 112.50 37.50
83.31 124.96 41.65
16.70
16.81
17.50
16.72
20.00
20.67
22.21
16.66
17.50
18.75
19.16
17.50
18.75
20.83
15.00
15.83
67.26
70.00
66.89
64.00*
64.00*
64.00*
66.65
70.00
64.00*
64.00*
70.00
64.00*
64.00*
60.00
90.00
95.00
90.00
95.00
30.00
31.67
63.33
Note:
* These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation.
Clock Enable Configuration
REF,
PD#
CPUCLK
SDRAM
IOAPIC
66MHz
PCICLK
Osc
VCOs
48MHz
LOW
ON
0
1
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
OFF
ON
OFF
ON
3
ICS9248-78
Preliminary Product Preview
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
4
ICS9248-78
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
5
ICS9248-78
Preliminary Product Preview
Byte0:Functionalityandfrequencyselectregister(Default=0)
(1 = enable, 0 = disable)
Bit
PWD
0
Description
0 - ±0.25% Center Sperad Spectrum
1-Down Spread Spectrum 0 to -0.5%
Bit 7
3V66 MHz
SEL_3V66=0 SEL_3V66=1
Bit
(2, 6:4)
CPUCLK SDRAM PCICLK
MHz
IOAPIC MHz
MHz
MHz
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
100.23
100.90
105.00
66.89
100.23
100.90
105.00
100.33
120.00
124.00
133.30
133.30
140.00
150.00
114.99
105.00
112.50
124.96
90.00
33.41
33.63
35.00
33.44
40.00
41.33
44.43
33.32
35.00
37.50
38.33
35.00
37.50
41.65
30.00
31.67
66.82
67.26
66.82
67.26
70.00
66.89
80.00
82.66
88.86
66.65
70.00
75.00
76.66
70.00
75.00
83.31
60.00
63.33
16.70
16.81
17.50
16.72
20.00
20.67
22.21
16.66
17.50
18.75
19.16
17.50
18.75
20.83
15.00
15.83
70.00
66.89
120.00
124.00
133.30
133.30
140.00
150.00
114.99
70.00
64.00*
64.00*
64.00*
66.65
Bit
(2, 6:4)
Note 1
70.00
64.00*
64.00*
70.00
75.00
64.00*
64.00*
60.00
83.31
90.00
95.00
95.00
63.33
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 6:4
Bit 3
Bit 1
Bit 0
0
1
0
0 - Normal
1 - Spread spectrum enable
0 - Running
1 - Tristate all outputs
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are default to 0000.
* These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation.
6
ICS9248-78
Preliminary Product Preview
Byte 2: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
FS3#
Bit
Pin# PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
27
-
X
X
X
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
31
32
34
35
36
38
39
40
1
1
1
1
1
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
FS0#
FS2#
24MHz (Act/Inact)
(Reserved)
48MHz (Act/Inact)
(Reserved)
1
26
-
1
1
1
1
1
30
1
SDRAM_F (Act/Inact)
Byte 3: Control Register
(1 = enable, 0 = disable)
Byte 4: Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
Bit
Pin# PWD
Description
(Reserved)
3V66_0 (Act/Inact)
3V66_1 (Act/Inact)
SEL_3V66
IOAPIC (Act/Inact0)
FS1#
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
19
17
16
15
13
12
11
1
1
1
1
1
PCICLK7 (Act/Inact)
PCICLK6 (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
7
0
1
8
1
-
46
-
43
44
X
1
X
1
1
1
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
7
ICS9248-78
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
-5
0.8
5
A
µ
IIH
VIN = VDD
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
2.0
-100
60
A
µ
IIL2
-200
IDD3.3OP CL = 0 pF; Select @ 66M
100
600
mA
Supply Current
Power Down
A
µ
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
400
Supply Current
Input frequency
Pin Inductance
Fi
VDD = 3.3 V;
14.318
MHz
nH
pF
pF
pF
ms
ms
ms
ns
Lpin
CIN
7
5
Input Capacitance1
Logic Inputs
Cout
CINX
Ttrans
Ts
Out put pin capacitance
X1 & X2 pins
6
27
45
3
Transition Time1
Settling Time1
Clk Stabilization1
Delay
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
TSTAB
3
tPZH,tPZH output enable delay (all outputs)
tPLZ,tPZH
1Guarenteed by design, not 100% tested in production.
1
1
10
10
output disable delay (all outputs)
ns
8
ICS9248-78
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
13.5
13.5
2
TYP MAX UNITS
1
RDSP2B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
45
45
Ω
Ω
1
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
V
IOL = 1 mA
0.4
-27
30
V
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 0.4 V, VOL = 2.0 V
VT = 1.25 V
-27
27
mA
mA
ns
ns
ns
ps
ps
1
tr2B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf2B
1
Duty Cycle
dt2B
50
1
Skew
tsk2B
VT = 1.25 V
175
250
1
tjcyc-cyc
VT = 1.25 V
Jitter
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.4
0.4
45
1
tr1
1.6
1.6
55
1
Fall Time
tf1
1
Duty Cycle
dt1
1
Skew
tsk1
VT = 1.5 V
175
500
ps
ps
Jitter
tjcyc-cyc
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
9
ICS9248-78
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
1
RDSP4B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -5.5 mA
IOL = 9.0 mA
9
9
2
30
30
Ω
Ω
1
RDSN4B
VOH4\B
VOL4B
IOH4B
V
0.4
-21
31
V
VOH@ min = 1.4 V, VOH@ MAX = 2.5 V
VOL@ MIN = 1.0 V, VOL@ MAX= 0.2
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
-36
36
mA
mA
ns
ns
%
IOL4B
1
tr4B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf4B
1
Duty Cycle
dt4B
Jitter
tjcyc-cyc
VT = 1.25 V
500
ps
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP MAX UNITS
1
RDSP3
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
24
24
Ω
Ω
1
RDSN3
10
VOH3
VOL3
IOH3
IOL3
2.4
V
IOL = 1 mA
0.4
-46
53
V
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-54
54
mA
mA
ns
ns
%
1
Tr3
0.4
0.4
45
1.6
1.6
55
1
Fall Time
Tf3
1
Duty Cycle
Dt3
1
Skew
Tsk3
VT = 1.5 V
250
250
ps
ps
Jitter
tjcyc-cyc VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
10
ICS9248-78
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
500
500
ps
ps
Jitter
tjcyc-cyc
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 48M, REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output LowCurrent
Rise Time
SYMBOL
CONDITIONS
MIN
20
TYP MAX UNITS
1
RDSP5
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = 1 mA
60
60
Ω
Ω
1
RDSN5
20
VOH5
VOL5
IOH5
IOL5
2.4
V
IOL = -1 mA
0.4
-23
27
V
VOH @MIN=1 V, VOH@MAX= 3.135 V
VOL@MIN=1.95 V, VOL@MIN=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
mA
mA
ns
ns
%
1
tr5
1.8
1.7
4
1
Fall Time
tf5
4
1
Duty Cycle
dt5
45
55
1
Jitter
tjcyc-cyc
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
VT = 1.5 V
500
1000
250
ps
ps
ps
1
tjcyc-cyc
Skew
Tsk
1Guarenteed by design, not 100% tested in production.
11
ICS9248-78
Preliminary Product Preview
Group Offset Waveforms
Group Skews at Common Transition Edges:
CPU & IOAPIC load (lumped) = 20pf; PCI, SDRAM, 3V66 LOAD (LUMPED) = 30pf.
GROUP
SYMBOL
SCPU1-3V66
CONDITIONS
MIN
TYP
MAX UNITS
CPU (at 66MHz) to
3V66
CPU (at 100MHz) to
SDRAM
CPU @ 1.25V, 3V66 @ 1.5V (Note: 180°
offset between CPU & 3V66
CPU @ 1.25V, SDRAM @ 1.5V (Note: 180°
offset between CPU & 66MHz
0
500
500
ps
ps
SCPU2-SDRAM
0
3V66 to PCI
S3V66-PCI 3V66 @ 1.5V, PCI @ 1.5V
SIOAPIC-PCI IOAPIC @ 1.25V, PCI @1.5V
1.5
0
2.1
4
ns
ps
IOAPIC to PCI
500
12
ICS9248-78
Preliminary Product Preview
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
NOM. MAX.
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
MIN.
.620
A
A1
A2
B
AC
.625
.630
48
C
D
E
See Variations
.296
.292
.299
e
H
h
L
N
0.025 BSC
.406
.013
.032
See Variations
5°
.400
.010
.024
.410
.016
.040
0°
8°
X
.085
.093
.100
Ordering Information
ICS9248yF-78
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
13
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