ICS9248YF-80-T [ICSI]
General Purpose 133MHz System Clock; 通用133MHz的系统时钟
| 型号： | ICS9248YF-80-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | General Purpose 133MHz System Clock |
| 文件： | 总7页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-80
General Purpose 133MHz System Clock
General Description
The ICS9248-80 is a general purpose system clock. It
provides 8 output CLKs, 1 REF CLK and excellent power
management features through CLK_STOP#.
Features
Extended temperature range (-20°C to +70°C)
Output features:
- 8 CLK outputs @ 3.3V, up to 133.34MHz.
-1-REFoutput@3.3V,14.31818MHz.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board
design iterations or costly shielding. The ICS9248-80
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Spread Spectrum for EMI control
I2C interface to stop clocks, select spread and frequency.
Excellent power managment feature through CLK_STOP#
and individual stop clocks through I2C.
Input is from a 14.31818MHz crystal.
Block Diagram
Pin Configuration
28-Pin 209 mil SSOP
* These inputs have a 120K internal pull-up to 3.3V.
** These inputs have a 120K internal pull-down to GND.
PentiumII is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9248-80 Rev A 3/21/00
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-80
Pin Descriptions
Pin number
Pin name
Type
OUT
Description
14.318MHz reference clock outputs at 3.3V
Gnd pin for REF clocks
1
REF
2
GNDREF
X1
PWR
IN
3
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
3.3V power input
Logic - input for frequency selection
Ground
4
5
X2
OUT
PWR
IN
VDD
6, 7, 14, 27
8, 11
9, 18, 24
10
FS (0:3)
GND
PWR
PWR
IN
VDDO
CLK_STOP#
SDATA
3.3V power for CLK outputs
Stops all clock outputs
Data input for I2C serial input.
12
IN
Clock input of I2C input
13
SCLK
IN
15, 21
16, 17, 19, 20,
22, 23, 25, 26
28
GNDO
PWR
Ground for CLK outputs
CLK (0:7)
VDDREF
OUT
PWR
Clock outputs up to 133.34MHz
Power pin for REF clocks
Frequency Selection
CLK
FS3
FS2
FS1
FS0
(MHz)
133.34
125.01
120.00
114.99
109.99
105.00
100.00
95.00
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
90.00
85.01
75.00
70.00
66.67
60.00
54.99
33.33
2
ICS9248-80
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
3
ICS9248-80
Byte0:Functionalityandfrequencyselectregister(Default=0)
(1=Running, 0=StoppedLow)
Bit
Description
0: 0 to -0.5% down spread
PWD
Bit7
0
1: 0 to -1.0% down spread
Bits
CLK frequency
2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
133.34
125.01
120.00
114.99
109.99
105.00
100.00
95.00
91.00
85.01
75.00
70.00
66.67
60.00
54.99
33.33
Bit (2, 6:4)
Note 1
0: Frequency is selected by hardware FS(0:3)
1: frequency is selected by bits 2, 6:4 of I2C
Bit3
Bit1
Bit0
0
0
0
0: Normal
1: Spread
0: Outputs running
1: Outputs tri-stated
Notes:
1. Default is for frequency control thru hardware pins.
Byte1:CLKoutputcontrolregister
(1=Running, 0=StoppedLow)
Bit
Pin#
16
17
19
20
22
23
25
26
PWD
Description
CLK7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
CLK6
CLK5
CLK4
CLK3
CLK2
CLK1
CLK0
4
ICS9248-80
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 20°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = -20°C - +70º C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating Supply Current
Input frequency
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
IIH
VIN = VDD
0.1
2.0
µA
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
-100
50
IDD2.5OP CL = 0 pF; Select @ 66 MHz
100
5
mA
MHz
pF
Fi
VDD = 3.3 V;
14.318
CIN
Logic Inputs
Input Capacitance1
CINX
TTrans
TS
X1 & X2 pins
6
pF
Transition Time1
Settling Time1
Clk Stabilization1
To first crossing of target Freq.
From first crossing to 1% of target Freq.
From VDD = 3.3 V to 1% target Freq.
1.3
0.3
< 3
2
ms
ms
TSTAB
3
ms
1Guaranteed by design, not 100% tested in production.
5
ICS9248-80
Electrical Characteristics - CLK
TA = -20°C - +70º C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH3
CONDITIONS
MIN
2
TYP
MAX UNITS
V
IOH = -1 mA
IOL = 1 mA
VOL3
0.4
27
V
mA
mA
ns
IOH3
VOH@Min = 1.0 V,VOH@Max = 2375 V
VOL@Min = 1.2 V,VOL@Max = 0.3 V
VOL = 0.4 V, VOH = 2.0 V
-27
27
IOL3
30
1
Tr3
1.33
1.4
58
1
Fall Time
Tf3
VOH = 2.0 V, VOL = 0.4 V
ns
1
Duty Cycle
Dt3
VT = 1.25 V
45
55
%
Skew1
Tsk1
tjcyc
VT = 1.25 V
VT = 1.25 V
250
250
ps
ps
Jitter, cyc-cyc
Jitter, Absolute1
tjabs1
VT = 1.25 V
250
ps
1Guarenteed by design, not 100% tested in production.
6
ICS9248-80
Country of origin location and ejector pin on
package bottom is optional and depends on
assembly location.
Pin 1
D/2
Index
Area
E1 /2
PARTING LINE
E
L
DETAIL “A”
TOP VIEW
BOTTOM VIEW
e
b
A2
c
A
C
.004
SEE
DETAIL “A”
E1
SEATING
PLANE
D
-C-
END VIEW
A1
SIDE VIEW
COMMON
DIMENSIONS
D
VARIATIONS
SYMBOL
MIN.
NOM.
MAX.
N
MIN.
NOM.
MAX.
A
A1
A2
b
-
-
0.078
-
14
16
20
24
28
30
0.232
0.232
0.272
0.311
0.390
0.390
0.244
0.244
0.284
0.323
0.402
0.402
0.256
0.256
0.295
0.335
0.413
0.413
0.002
0.065
0.009
0.004
-
0.069
0.073
0.015
0.010
0.012
c
-
D
E1
e
See Variations
0.209
0.197
0.220
0.0256 BSC
0.307
Dimensions in inches
E
0.291
0.022
0.323
0.037
L
0.030
N
See Variations
4°
209 mil SSOP Package
0°
8°
Ordering Information
ICS9248yF-80-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
7
information being relied upon by the customer is current and accurate.
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