ICS9250-23 [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩; 频率发生器和缓冲器集成的赛扬和PII / III⑩
| 型号： | ICS9250-23 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 文件： | 总15页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9250-23
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
Pin Configuration
810/810E type chipset
Output Features:
•
•
•
•
•
•
•
2 - CPUs @ 2.5V, up to 166MHz.
13 - SDRAM @ 3.3V, up to 166MHz.
2 - 3V66 @ 3.3V, 2x PCI MHz.
8 - PCI @3.3V.
1 - 48MHz, @3.3V fixed.
1 - 24MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Features:
•
•
•
Up to 166MHz frequency support
Support power management through PD#.
Spread spectrum for EMI control (± 0.25%)
center spread.
•
•
Uses external 14.318MHz crystal
FS pins for frequency select
Key Specifications:
•
•
CPU Output Jitter: <250ps
IOAPIC Output Jitter: <500ps
56-Pin 300 mil SSOP
•
•
•
•
•
•
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
1. These pins will have 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
CPU Output Skew: <175ps
PCI Output Skew: <500ps
3V66 Output Skew <175ps
Block Diagram
For group skew timing, please refer to the
Group Timing Relationship Table.
Power Groups
GNDREF, VDDREF = REF, Crystal
GND3V66,VDD3V66=3V66
GNDPCI, VDDPCI=PCICLKs
GNDCOR,VDDCOR=PLLCORE
GND48, VDD48=48
GNDSDR, VDDSDR = SDRAM
GNDLCPU, VDDLCPU=CPUCLK
GNDLPCI, VDDLAPIC=IOAPIC
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9250-23 Rev A 4/3/01
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9250-23
General Description
The ICS9250-23 is a single chip clock solution for desktop designs using the 810/810E style chipset. It provides all necessary
clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-23
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN
PIN NAME
REF1
TYPE
DESCRIPTION
NUMBER
1
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply.
2, 9, 10, 18, 25,
32, 33, 37, 45
VDD
X1
Crystal input, has internal load cap (33pF) and feedback
3
4
IN
resistor from X2.
Crystal output, nominally 14.318MHz. Has internal load
X2
OUT
cap (33pF)
5, 6, 14, 21,
28, 29, 36,
41, 49
GND
PWR Ground pins for 3.3V supply.
8, 7
3V66 [1:0]
PCICLK01
FS0
OUT 3.3V Fixed 66MHz clock outputs for HUB.
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS.
11
IN
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS.
IN Logic input frequency select bit. Input latched at power on.
Logic input frequency select bit. Input latched at power on.
PCICLK11
12
FS1
20, 19, 17, 16,
15, 13
PCICLK [7:2]
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS.
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
22
PD#
IN
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
23
24
SCLK
SDATA
48MHz
FS3
IN
Clock input of I2C input.
I/O
Data pin for I2C circuitry 5V tolerant.
OUT 3.3V Fixed 48MHz clock output for USB.
34
35
IN
IN
Logic input frequency select bit. Input latched at power on.
Logic input frequency select bit. Input latched at power on.
FS2
24MHz
SDRAM_F
OUT 3.3V fixed 24MHz output.
OUT 3.3V free running 100MHz SDRAM not affected by I2C.
38
26, 27, 30, 31,
39, 40, 42, 43, SDRAM [11:0]
44, 46, 47, 48
3.3V output running 100MHz. All SDRAM outputs can be turned off
OUT
through I2C.
50
GNDL
PWR Ground for 2.5V power supply for CPU & APIC.
51, 52
CPUCLK [1:0]
OUT 2.5V Host bus clock output. Output frequency derived from FS pins.
53, 55
54
VDDL
IOAPIC
FS4
PWR 2.5V power suypply for CPU, IOAPIC.
OUT 2.5V clock outputs running at 16.67MHz.
IN
Logic input frequency select bit. Input latched at power on.
56
REF01
OUT 3.3V, 14.318MHz reference clock output.
Third party brands and names are the property of their respective owners.
2
ICS9250-23
Frequency Selection
CPU
MHz
SDRAM
MHz
PCI
MHz
FS4 FS3 FS2 FS1 FS0
3V66 MHz
IOAPIC MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
69.00
70.00
71.00
66.90
72.00
75.00
76.60
85.00
68.00
103.50
105.00
106.50
100.35
108.00
112.50
114.90
127.50
102.00
111.00
140.00
133.33
150.00
155.00
166.00
166.00
111.77
104.78
109.51
100.90
117.00
123.75
133.33
142.50
102.25
105.00
107.50
100.68
110.00
112.00
115.29
125.32
69.00
70.00
71.00
66.90
72.00
75.00
76.60
85.00
68.00
74.00
70.00
66.67
75.00
77.50
83.00
111.00
74.52
69.86
73.01
67.27
78.50
82.50
88.89
95.00
68.50
70.00
72.00
67.45
73.33
74.67
77.24
83.34
34.50
35.00
35.50
33.45
36.00
37.50
38.40
42.50
34.00
37.00
35.00
33.33
37.50
38.75
41.50
55.80
37.26
34.93
36.50
33.63
39.25
41.25
44.44
47.50
34.25
35.00
36.00
33.73
36.67
37.33
38.62
41.67
17.25
17.50
17.75
16.73
18.00
18.75
19.20
21.25
17.00
18.50
17.50
16.67
18.75
19.38
22.75
27.90
18.63
17.46
18.25
16.82
19.63
20.62
22.22
23.75
17.13
17.50
18.00
16.86
18.33
18.67
19.30
20.83
74.00
140.00
133.33
150.00
155.00
166.00
166.00
111.77
104.78
109.51
100.90
117.00
123.75
133.33
142.50
136.00
140.00
143.00
133.90
146.67
149.33
153.30
166.67
Clock Enable Configuration
REF,
PD#
CPUCLK
SDRAM
IOAPIC
66MHz
PCICLK
Osc
VCOs
48MHz
LOW
ON
0
1
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
OFF
ON
OFF
ON
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3
ICS9250-23
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Third party brands and names are the property of their respective owners.
4
ICS9250-23
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. When no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, then
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used both to provide the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
5
ICS9250-23
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Address
D2(H)
Address
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
D3(H)
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
6
ICS9250-23
Byte 0: Functionality and frequency select register (Default=0)
(1 = enable, 0 = disable)
Bit
PWD
Description
CPUCLK
MHz
SDRAM
MHz
3V66
MHz
IOAPIC
MHz
Bit (2,7:4)
PCICLK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
69.00
70.00
71.00
66.90
72.00
75.00
76.60
85.00
68.00
74.00
103.50
105.00
106.50
100.35
108.00
112.50
114.90
127.50
102.00
111.00
69.00
70.00
71.00
66.90
72.00
75.00
76.60
85.00
68.00
74.00
34.50
35.00
35.50
33.45
36.00
37.50
38.40
42.50
34.00
37.00
17.25
17.50
17.75
16.73
18.00
18.75
19.20
21.25
17.00
18.50
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
140.00
133.33
150.00
140.00
133.33
150.00
70.00
66.67
75.00
35.00
33.33
37.50
17.50
16.67
18.75
00100
Note 1
Bit
(2, 7:4)
0
1
1
0
1
155.00
155.00
77.50
38.75
19.38
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
166.00
166.00
111.77
104.78
109.51
100.90
117.00
123.75
133.33
142.50
136.00
140.00
143.00
133.90
146.67
149.33
153.30
166.67
166.00
166.00
111.77
104.78
109.51
100.90
117.00
123.75
133.33
142.50
102.25
105.00
107.50
100.68
110.00
112.00
115.29
125.32
83.00
111.00
74.52
69.86
73.01
67.27
78.50
82.50
88.89
95.00
68.50
70.00
72.00
67.45
73.33
74.67
77.24
83.34
41.50
55.80
37.26
34.93
36.50
33.63
39.25
41.25
44.44
47.50
34.25
35.00
36.00
33.73
36.67
37.33
38.62
41.67
22.75
27.90
18.63
17.46
18.25
16.82
19.63
20.62
22.22
23.75
17.13
17.50
18.00
16.86
18.33
18.67
19.30
20.83
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,6:4
0- Normal
Bit 3
Bit 1
Bit 0
0
1
0
1- Spread spectrum enable ± 0.25% Center Spread
0- Running
1- Tristate all outputs
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.
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7
ICS9250-23
Byte 2: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
FS3#
Bit
Pin# PWD
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
0
0
0
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
39
40
42
43
44
46
47
48
1
1
1
1
1
FS0#
FS2#
24MHz
(Reserved)
48MHz
-
35
-
34
-
1
1
1
(Reserved)
SDRAM_F
38
Byte 3: Control Register
(1 = enable, 0 = disable)
Byte 4: Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Bit
Pin# PWD
Description
(Reserved)
3V66_0
3V66_1
FS4#
IOAPIC
FS1#
CPUCLK1
CPUCLK0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
19
17
16
15
13
12
11
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
7
1
1
1
0
1
0
1
1
8
-
54
-
1
1
1
51
52
Byte 5: Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
-
-
26
27
30
31
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
Third party brands and names are the property of their respective owners.
8
ICS9250-23
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
GroupTiming RelationshipTable
Group
CPU 66MHz
CPU 100MHz
Offset Tolerance
5.0ns 500ps
CPU 133MHz
Offset Tolerance
0.0ns 500ps
Offset
Tolerance
500ps
CPU to SDRAM
CPU to 3V66
2.5ns
7.5ns
0.0ns
500ps
5.0ns
0.0ns
500ps
500ps
500ps
N/A
0.0ns
0.0ns
500ps
500ps
500ps
N/A
SDRAM to 3V66
500ps
3V66 to PCI
USB & DOT
1.5-3.5ns
Asynch
500ps
N/A
1.5-3.5ns
Asynch
1.5-3.5ns
Asynch
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
-5
0.8
5
A
IIH
VIN = VDD
µ
µ
µ
A
A
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
Cl = 0 pF; Select @ 66M
-5
IIL2
-200
IDD3.3V
IDDL2.5V
119
3
280
mA
Supply Current
Cl = 0 pF; Select @ 66M
25
600
A
µ
Power Down Current
Input frequency
Input Capacitance1
IDD3.3VPD Cl = 0 pF; With Input to Vdd or Gnd
Fi
VDD = 3.3 V
14.318
MHz
CIN
Logic Inputs
5
45
3
pF
CINX
TTrans
TS
X1 & X2 pins
27
pF
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
ns
1
3
TStab
3
TPZH,TPZL output enable delay(all outputs)
TPHZ,TPLZ
1
1
10
10
Delay1
output disable delay(all outputs)
ns
1Guaranteed by design, not 100% tested in production.
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9
ICS9250-23
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless
Electrical Characteristics - IOAPIC
PARAMETER
SYMBOL
VOH2B
CONDITIONS
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
Output High Voltage
IOH = -1 mA
PARAMETER
SYMBOL
VOH4B
VOL4B
IOH4B
CONDITIONS
MIN
TYP
MAX UNITS
Output Low Voltage
V
I = 1 mA
Output High Voltage
Output Low Voltage
Output High Current
IOH = -18 mA
IOL = 9 mA
2.4OL2B 2.9 OL
V
V
VOH
= 1 V
@0M.I4N
-22
IOH2B
Output High Current
0.25
V
OH@MAX = 2.375V
mA
VOH = 2.0 V
-58
34.1
VOL@MIN = 1.2 V
IOL2B
31
Output Low Current
VOL@MIN = 1.0 V
VOL@MAX =0.3V
IOL4B
Output Low Current
mA
VOL@MAX =0.2V
7.85
31
1
Rise Time
Fall Time
Duty Cycle
Skew
tr2B
0.4
V
= 1 V, V = 2.0 V
Rise Time1
Fall Time1
1
Tr4B
Tf4B
Dt4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
1.28 OL
2
OHns
tf2B
VOH = 2.0 V, VOL = 0.4 V
1
0.4
dt2B
1.2
1.6
VT = 1.25 V
ns
%
VT = 1.25 V
Duty Cycle1
1
VT = 1.25 V
VT = 1.25 V
45
tsk2B
49.6 55
1
1
Jitter, Cycle-to-Cycle
tjcyc-cyc4B
432
750
ps
Jitter, Cycle-to-Cycle
Jitter, Cycle-to-Cycle
tjcyc-cyc2B
VT = 1.25 V (CPU 133, SDRAM 100
1
1Guaranteed by design, not 100% tested in production.
tjcyc-cyc
VT = 1.25 V (all other select B)
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
10
ICS9250-23
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs
PARAMETER
Output High Voltage
Output Low Voltage
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.25
0.03
-71
-10
74
MAX UNITS
V
IOH = -1 mA
IOL = 1 mA
VOL1
0.55
-33
V
VOH@MIN = 1 V
IOH1
Output High Current
mA
VOH@MAX = 3.135V
VOL@MIN = 1.95 V
VOL@MAX =0.4V
-33
38
IOL1
Output Low Current
mA
22
30
2
2
Rise Time1
Fall Time1
Duty Cycle1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.5
0.5
45
1.65
1.53
51.1
331
185
tr1
tf1
dt1
tsk1
tjcyc-cyc1
ns
ns
%
55
Skew1
VT = 1.5 V
VT = 1.5 V
500
500
ps
ps
Jitter, Cycle-to-Cycle
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
SYMBOL
VOH1
CONDITIONS
IOH = -1 mA
IOL = 1 mA
VOL1
VOH@MIN = 1 V
IOH1
Output High Current
V
OH@MAX = 3.135V
VOL@MIN = 1.95 V
VOL@MAX =0.4V
IOL1
tr1
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
tf1
dt1
tsk1
Jitter1
tjcyc-cyc1
,Cycle-to-Cycle
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
ICS9250-23
EElleeccttrriiccaallCChhaararcatcetreisrtisictsic-s 4-82M4HMz,HRzEF
T = 0 - 70º C; V = 3.3 V +/-5%, V
= 2.5 V +/-5%; C = 20 pF (unless
LL
TAA = 0 - 70º C; VDDDD = 3.3 V +/-5%, VDDDDLL = 2.5 V +/-5%; C = 20 pF (unle
PARAMETER
PARAMETER
OOuuttppuutt HHiigghh VVoollttaaggee
OOuuttppuutt LLooww VVoollttaaggee
SYMBOL
SYMBOL
CONDITIONS
CONDITIONS
VVOH5
IIOHH == --11 mmA
IIOLL == 11 mmAA
OH5
VV
OL5
OL5
VVOOHH@ MIN ==11 VV
OH@MAX
@MIN
I
IOH5
OH5
OOuuttppuutt HHiigghh CCuurrrreenntt
VOH@MAX == 33..113355VV
VVOOL@@MMIINN == 11..9955VV
I
OOuuttppuutt LLooww CCuurrrreenntt
RRiissee TTiimmee11
IOL5
OL5
VOL@MAX ==0..44VV
OL@MAX
ttr5
VVOL == 00..44 VV,,VVOH ==22..44VV
r5
OL
OH
1
FFaallll TTiimmee1
ttff55
VVOH == 22.44 VV,,VVOL ==00..44VV
OH OL
1
DDuuttyy CCyyccllee1
ddt5
VVT ==11..55VV
t5
T
1
1
Jitter
V = 1.5 V, 24MHz
VT = 1.5 V, 24MHz
t
Jitter ,C, Cyycclele--ttoo--CCyyccllee
tjcyc-cyc5
T
jcyc-cyc5
1
Jitter1
VT = 1.5 V, 48MHz
tjcyc-cyc5
tjcyc-cyc5
, Cycle-to-Cycle
Jitter1
Guaranteed by design, not 100% tested in production.
VT = 1.5 V, REF
, Cycle-to-Cycle
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
ICS9250-23
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF
PARAMETER
Output High Voltage
Output Low Voltage
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.28
0.03
-85
-12
63
27
1.25
1.53
MAX UNITS
V
IOH = -1 mA
IOL = 1 mA
VOL1
0.4
-54
V
VOH@MIN = 2 V
IOH1
Output High Current
mA
VOH@MAX = 3.135V
-46
54
VOL@MIN = 1 V
VOL@MAX =0.4V
IOL1
Output Low Current
mA
53
1.6
1.6
Rise Time1
Fall Time1
Duty Cycle1
Skew
tr1
tf1
dt1
tsk1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
0.4
0.4
45
ns
ns
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
53.2
267
176
55
380
%
ps
Jitter1
tjcyc-cyc1
250
ps
, Cycle-to-Cycle
1Guaranteed by design, not 100% tested in production.
(No Skew Window is needed for Group Skew spec.)
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%
24MHz, 48MHz, REF, CPU & IOAPIC load = 20 pF; PCI, SDRAM & 3V66 load = 30 pF.
Refer to Group Offset Waveform diagram for definition of transition edges.
Group Skews (CPU = 66 MHz; SDRAM = 100MHz)
PARAMETER
SYMBOL
Tsk1 CPU-SDRAM
Tsk1 CPU-3V66
Tsk1 SDRAM-3V66
Tsk1 3V66-PCI
CONDITIONS
MIN
TYP
MAX UNITS
Skew1
Skew1
Skew1
Skew1
CPU @ 1.25 V, SDRAM @ 1.5 V 2.0
3.0
8
ns
ns
ps
ns
CPU to SDRAM
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM @1.5V, 3V66 @ 1.5 V
3V66 @1.5V, PCI @ 1.5 V
7
CPU to 3V66
SDRAM to 3V66
3V66 to PCI
-500
1.5
394
500
3.5
2.58
Group Skews (CPU = 100 MHz; SDRAM = 100MHz)
PARAMETER
SYMBOL
Tsk1 CPU-SDRAM
Tsk1 CPU-3V66
Tsk1 SDRAM-3V66
Tsk1 3V66-PCI
CONDITIONS
MIN
TYP
MAX UNITS
Skew1
Skew1
Skew1
Skew1
CPU @ 1.25 V, SDRAM @ 1.5 V 4.5
5.5
5.5
500
3.5
ns
ns
ps
ns
CPU to SDRAM
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM @1.5V, 3V66 @ 1.5 V
3V66 @1.5V, PCI @ 1.5 V
4.5
-500
1.5
4.63
396
CPU to 3V66
SDRAM to 3V66
3V66 to PCI
2.58
Group Skews (CPU = 133 MHz; SDRAM = 100MHz)
PARAMETER
SYMBOL
Tsk1 CPU-SDRAM
Tsk1 CPU-3V66
Tsk1 SDRAM-3V66
Tsk1 3V66-PCI
CONDITIONS
MIN
TYP
-322
-284
389
MAX UNITS
Skew1
Skew1
Skew1
Skew1
CPU @ 1.25 V, SDRAM @ 1.5 V -500
500
500
500
3.5
ps
ps
ps
ns
CPU to SDRAM
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM @1.5V, 3V66 @ 1.5 V
3V66 @1.5V, PCI @ 1.5 V
-500
-500
1.5
CPU to 3V66
SDRAM to 3V66
3V66 to PCI
2.61
Third party brands and names are the property of their respective owners.
13
ICS9250-23
0ns
25ns
50ns
75ns
CPU 66 Period
CPU/ITP/HCLK [66MHz (2.5V)]
CPU/ITP/HCLK [100MHz (2.5V)]
CPU 100 Period
SDRAM 100 Period
SDRAM [11:0, F] & DCLKWR [100MHz (3.3V)]
3V66-PCI
3V66 Link (ICH / MGCH) [66MHz (3.3V)]
PCI [7:0] LPC/SIO [33MHz (3.3V)]
Ref Clock [14.318MHz (3.3V)]
USB [48MHz (3.3V)]
APIC (CPU/MCH) [16.67MHz (2.5V)]
Group Offset Waveforms
Third party brands and names are the property of their respective owners.
14
ICS9250-23
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
a
hh xx 4455°°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
α
A1
VARIATIONS
- CC --
D mm.
D (inch)
e
SEATING
PLANE
N
MIN
18.31
MAX
18.55
MIN
.720
MAX
b
56
.730
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS9250yF-23
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
15
information being relied upon by the customer is current and accurate.
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