ICSSSTV16857 [ICSI]
DDR 14-Bit Registered Buffer; DDR 14位寄存缓冲器
| 型号： | ICSSSTV16857 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DDR 14-Bit Registered Buffer |
| 文件： | 总8页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICSSSTV16857
DDR 14-Bit Registered Buffer
Recommended Application:
DDR Memory Modules
Product Features:
Pin Configuration
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
•
•
•
•
Differential clock signal
Meets SSTL_2 signal data
Supports SSTL_2 class I & II specifications
low-voltage operation
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDD = 2.3V to 2.7V
•
48 pin TSSOP package
Q7
VDDQ
GND
Q8
Q9
Truth Table1
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
D9
D10
D11
D12
VDD
GND
D13
D14
Inputs
CLK#
Q Outputs
Q
RESET#
CLK
D
X or
Floating
X or
Floating
X or
Floating
L
L
H
H
H
H
L
H
L
Q0(2)
↑
↑
↓
↓
48-Pin TSSOP & TVSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
L or H
L or H
X
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
Notes:
1.
H = High Signal Level
L = Low Signal Level
↑ = Transition LOW-to-HIGH
↓ = Transition HIGH -to LOW
X = Irrelevant
2.
Output level before the indicated
steady state input conditions were
established.
Block Diagram
38
39
CLK
CLK#
34
RESET#
R
1
Q1
CLK
48
35
D1
VREF
D1
To 13 Other Channels
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
16857 Rev D 07/09/01
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICSSSTV16857
General Description
The 14-bit ICSSTV16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels
except for the RESET# input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the
positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS
levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and
when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and
clock are switched off.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
24, 23, 20, 19, 18,
15, 14, 11, 10, 7, 6,
5, 2, 1
Q (14:1)
OUTPUT
Data output
3, 8, 13, 22,
27, 36, 46
GND
PWR
PWR
Ground
4, 9, 12, 16, 21
VDDQ
Output supply voltage
25, 26, 29, 30, 31,
32, 33, 40, 41, 42,
43, 44, 47, 48
D (14:1)
INPUT
Data input
38
39
CLK
CLK#
VDD
INPUT
INPUT
PWR
Positive clock input
Negative clock input
Core supply voltage
Reset (active low)
28, 37, 45
34
RESET#
VREF
INPUT
INPUT
35
Input reference voltage
Third party brands and names are the property of their respective owners.
2
ICSSSTV16857
Absolute Maximum Ratings
Notes:
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5
Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDDQ +0.5
Input Clamp Current . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . . . 50mA
Continuous Output Current . . . . . . . . . . . . . . . . . 50mA
VDD, VDDQ or GND Current/Pin . . . . . . . . . . . . 100mA
1. The input and output negative voltage
ratings may be excluded if the input
and output clamp ratings are observed.
2. This current will flow only whtn the
output is in the high state level
V0 >VDDQ
.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Package Thermal Impedance3 . . . . . . . . . . . . . . . . . . . . 55°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Recommended Operating Conditions
DESCRIPTION
PARAMETER
MIN
2.3
TYP
2.5
MAX
2.7
UNITS
Supply Voltage
VDD
VDDQ
VREF
VTT
VI
I/O Supply Voltage
2.3
2.5
2.7
Reference Voltage VREF = 0.5X VDDQ
Termination Voltage
1.15
1.25
VREF
1.35
VREF -0.04
0
VREF -0.04
VDD
Input Voltage
VIH
VIH
VIL
DC Input High Voltage
AC Input High Voltage
VREF +0.15
VREF +0.31
Data Inputs
V
DC Input Low Voltage
VREF -0.15
VREF -0.31
VIL
AC Input Low Voltage
VIH
VIL
Input High Voltage Level
Input Low Voltage Level
Common mode Input Range
Differential Input Voltage
1.7
RESET#
0.7
VICR
VID
0.97
0.36
1.53
CLK, CLK#
Cross Point Voltage of Differential Clock
Pair
(VDDQ/2)
+0.2
VIX
(VDDQ/2) -0.2
High-Level Output Current
IOH
-20
mA
Low-Level Output Current
IOL
TA
20
70
Operating Free-Air Temperature
0
°C
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
3
ICSSSTV16857
Electrical Characteristics - DC
TA = 0 - 70º C; VDD = 2.5 V +/-200mV, VDDQ=2.5V 200mV; (unless otherwise stated)
SYMBOL
VIK
PARAMETERS
CONDITIONS
II = -18mA
VDD
2.3V
MIN
TYP
MAX
-1.2
UNITS
V
IOH = -100µA
2.3V-2.7 VDD -0.2 2.5
VOH
IOH= -16mA
2.3V
2.3-2.7V
2.3V
1.95
2
0
IOL = 100µA
0.2
0.35
±5
VOL
II
IOL = 16mA
0.16
All Inputs
VI = VDD or GND
RESET# = GND
VI = VIH (AC#) or VIL (AC)
RESET# = VDD
2.7V
µA
µA
Standby (Static)
0.01
IDD
,
Operating (Static)
TBD
mA
RESET = VDD, VI = VIH(AC)
Dynamic operating or VIL (AC), CK and CK#
clock only
switching 50% duty cycle.
RESET# = VDD, VI = VIH(AC)
or VIL (AC), CK and CK#
TBD µA/clock MHz
IO = 0
2.7V
IDDD
TBD
µA/ clock
MHz/data
Dynamic Operating switching 50% duty cycle.
per each data input One data input switching at
half clock frequency, 50%
duty cycle
rOH
rOL
Output High
Output Low
[rOH - rOL] each
separate bit
Data Inputs
CK and CK#
IOH = -20mA
IOL = 20mA
2.3-2.7V
2.3-2.7V
7
7
15
10
20
20
Ω
Ω
rO(∆)
IO = 20mA, TA = 25° C
VI = VREF ±310mV
VICR = 1.25V, VI(PP) = 360mV
2.5V
2.5V
4
Ω
2.5
2.5
3.5
3.5
Ci
pF
Notes:
1 - Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
4
ICSSSTV16857
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
VDD=2.5±0.2V
UNITS
MIN
1.1
TYP
133
2.4
MAX
200
2.8
5
fclock
tPD
tRST
tSL
Clock frequency
MHz
ns
Clock to output time
Reset to output time
3.1
ns
Output slew rate
1
1.5
4
V/ns
ns
Setup time, fast slew rate 2, 4
Data before CKD , CK#E
Data after CKD , CK#E
0.75
0.9
0.018
Setup time, slow slew rate 3, 4
tSU
ns
Hold time, fast slew rate 2,4
Hold time, slow slew rate 3, 4
0.75
0.9
0.145
ns
Th
ns
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate =1V/ns.
4 - CLK, CLK# signals input slew rates are =1V/ns.
3 - For data signal input slew rate =0.5V/ns and < 1V/ns.
Switching Characteristics
(over recomm ended operating free-air temperature range, unless otherwise noted)
SYMBOL
From
To
VDD=2.5±0.2V
UNITS
(Input)
(Output)
MIN
1.1
TYP
133
2.4
MAX
200
2.8
5
fclock
tPD
MHz
ns
CLK, CLK#
RESET#
Q
Q
tph1
3.1
ns
Third party brands and names are the property of their respective owners.
5
ICSSSTV16857
VTT
RL 5W0
=
From Output
Under Test
Test Point
CL = 30 pF
(see Note 1)
Load Circuit
LVCMOS
RESET#
Input
VDD
0 V
VDD/2
VDD/2
VI(pp)
Timing
Input
VICR
VICR
tinact
tact
IDDH
tPHL
tPHL
IDD
90%
(see note 2)
10%
VOH
VOL
IDDL
VTT
VTT
Voltage and Current Waveforms
Inputs Active and Inactive Times
Output
Voltage Waveforms - Propagation Delay Times
tw
VIH
VIL
Input
VREF
VREF
Voltage Waveforms - Pulse Duration
LVCMOS
RESET#
Input
VIH
VIL
VI(pp)
V
DD/2
Timing
Input
VICR
tPHL
VOH
VOL
Output
th
tSU
VTT
Voltage Waveforms - Propagation Delay Times
VIH
VIL
VREF
Input
VREF
Voltage Waveforms - Setup and Hold Times
Parameter Measurement Information (VDD = 2.5V ±±.2Vꢀ
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz, Zo=50Ω, input
slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF -310mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPLH and tPHL are the same as tpd
Third party brands and names are the property of their respective owners.
6
ICSSSTV16857
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
E1
e
6.00
6.20
.236
.244
a
0.50 BASIC
0.020 BASIC
D
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
e
SEATING
PLANE
48
b
Reference Doc.: JEDEC Publication 95, MO-153
aaa
C
10-0039
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
(240 mil)
Ordering Information
ICSSSTV16857yG-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
7
information being relied upon by the customer is current and accurate.
ICSSSTV16857
c
N
In Millimeters
In Inches
L
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.13
0.09
MAX
1.20
0.15
1.05
0.23
0.20
MIN
--
.002
.032
.005
.0035
MAX
.047
.006
.041
.009
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
22
α
4.30
4.50
.169
.177
D
0.40 BASIC
0.016 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
aaa
0°
--
8°
0.08
0°
--
8°
.003
A
A2
A1
VARIATIONS
D mm.
D (inch)
- CC --
N
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
e
SEATING
PLANE
48
b
Reference Doc.: JEDEC Publication 95, MO-153
aaa
C
10-0037
4.40 mm. Body, 0.40 mm. pitch TSSOP
(16 mil)
(173 mil)
Ordering Information
ICSSSTV16857yL-T
Example:
ICS XXXX y L - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
L=TSSOP (TVSOP)
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
8
information being relied upon by the customer is current and accurate.
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