74LVCH162823APA [IDT]

TSSOP-56, Tube;


型号：	74LVCH162823APA
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	TSSOP-56, Tube
文件：	总7页 (文件大小：78K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVCH162823A

3.3VCMOS18-BITBUSINTERFACEREGISTERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

3.3V CMOS 18-BIT

IDT74LVCH162823A

BUS INTERFACE REGISTER

WITH 5 VOLT TOLERANT I/O

AND BUS-HOLD

FEATURES:

DESCRIPTION:

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

TheLVCH162823A18-bitbusinterfaceregisterisbuiltusingadvanced

dual metal CMOS technology. This high-speed, low-power register with

clock enable (CLKEN) and clear (CLR) controls is ideal for parity bus

interfacinginhigh-performancesynchronoussystems. Thecontrolinputs

are organized to operate the device as two 9-bit registers or one 18-bit

are designed with hysteresis for improved noise margin.

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4µ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

All pins of the LVCH162823A can be driven from either 3.3V or 5V

devices. Thisfeatureallowstheuseofthisdeviceasatranslatorinamixed

3.3V/5V supply system.

• Available in TSSOP and TVSOP packages

The LVCH162823A has series resistors in the device output structure

which will significantly reduce line noise when used with light loads. This

driver has been developed to drive ±12mA at the designated threshold

levels.

DRIVE FEATURES:

• Balanced Output Drivers: ±12mA

• Low switching noise

The LVCH162823A has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs

and eliminates the need for pull-up/down resistors.

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

1OE

2OE

1CLR

2CLR

CLK

CLKEN

1Q1

2Q1

2D1

TO EIGHT OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JANUARY 2004

DSC-4683/2

IDT74LVCH162823A

3.3VCMOS18-BITBUSINTERFACEREGISTERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

1CLK

1CLR

1OE

1Q1

°C

1CLKEN

1D1

IOUT

DC Output Current

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

GND

ICC

ISS

Continuous Current through each

VCC or GND

±100

1D2

1D3

V^CC

1Q2

1Q3

V^CC

1Q4

1Q5

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

1D4

1D5

1D6

1Q6

GND

1D7

1Q7

1Q8

1Q9

2Q1

2Q2

1D8

1D9

2D1

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

2D2

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

2D3

GND

2D4

2D5

2D6

VCC

COUT

CI/O

6.5

2Q3

GND

6.5

NOTE:

2Q4

1. As applicable to the device type.

2Q5

2Q6

VCC

2D7

2D8

2Q7

2Q8

FUNCTIONTABLE⁽¹⁾

GND

Inputs

Outputs

2D9

2Q9

xOE

xCLR xCLKEN xCLK

xDx

xQx

Function

HighZ

2CLKEN

2OE

↑

2CLK

2CLR

Clear

TSSOP/ TVSOP

TOP VIEW

Q⁽²⁾

Hold

Load

PINDESCRIPTION

Pin Names

Description

NOTES:

xDx

xCLK

xCLKEN

xCLR

xOE

DataInputs⁽¹⁾

Clock Inputs

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High Impedance

↑ = LOW-to-HIGH transition

Clock Enable Inputs (Active LOW)

Asynchronous Clear Inputs (Active LOW)

OutputEnableInput(ActiveLOW)

3-StateOutputs

2. Output level before indicated steady-state input conditions were established.

xQx

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

IDT74LVCH162823A

3.3VCMOS18-BITBUSINTERFACEREGISTERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

±5

µA

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

±50

µA

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

3.6 ≤ VIN ≤ 5.5V⁽²⁾

—

500

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

µA

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µA

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-Hold Input Overdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

—

µA

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74LVCH162823A

3.3VCMOS18-BITBUSINTERFACEREGISTERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 4mA

IOH = – 6mA

IOH = – 4mA

IOH = – 8mA

IOH = – 6mA

IOH = – 12mA

IOL = 0.1mA

IOL = 4mA

VCC – 0.2

VCC = 2.3V

VCC = 2.7V

VCC = 3V

1.9

1.7

2.2

—

2.4

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.55

0.4

0.6

0.55

0.8

IOL = 6mA

VCC = 2.7V

VCC = 3V

IOL = 4mA

IOL = 8mA

IOL = 6mA

IOL = 12mA

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

—

Unit

CPD

PowerDissipationCapacitanceOutputsenabled

PowerDissipationCapacitanceOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

—

IDT74LVCH162823A

3.3VCMOS18-BITBUSINTERFACEREGISTERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

tPLH

Parameter

Min.

Max.

Unit

PropagationDelay

xCLK to xQx

PropagationDelay

xCLR to xQx

1.5

tPHL

1.5

tPZH

tPZL

tPHZ

tPLZ

tSU

OutputEnableTime

xOE to xQx

OutputDisableTime

xOE to xQx

6.5

Set-up Time HIGH or LOW, xDx to xCLK

—

Hold Time HIGH or LOW, xDx to xCLK

1.5

3.5

tSU

Set-up Time HIGH or LOW, xCLKEN to xCLK

3.5

Hold Time HIGH or LOW, xCLKEN to xCLK

xCLK Pulse Width HIGH or LOW

xCLR Pulse Width LOW

1.5

—

tREM

Recovery Time xCLR to xCLK

OutputSkew⁽²⁾

—

tSK(o)

—

500

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVCH162823A

3.3VCMOS18-BITBUSINTERFACEREGISTERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V

Unit

tPHL

tPLH

VLOAD

VIH

2 x Vcc

Vcc

VOH

VOL

OUTPUT

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

VIH

VLZ

VHZ

OPPOSITE PHASE

INPUT TRANSITION

150

LVC Link

Propagation Delay

DISABLE

ENABLE

VLOAD

Open

GND

VIH

VCC

CONTROL

INPUT

tPZL

tPLZ

500Ω

VIN

VLOAD/2

VOUT

VLOAD/2

OUTPUT

NORMALLY

LOW

Pulse ^{(1, 2)}

Generator

SWITCH

CLOSED

D.U.T.

VLZ

VOL

tPHZ

tPZH

SWITCH

OPEN

500Ω

VOH

VHZ

OUTPUT

NORMALLY

HIGH

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

DATA

INPUT

tSU

SWITCHPOSITION

VIH

TIMING

INPUT

Test

Switch

V^LOAD

GND

Open Drain

Disable Low

Enable Low

tREM

ASYNCHRONOUS

CONTROL

Disable High

Enable High

SYNCHRONOUS

CONTROL

tSU

All Other Tests

Open

LVC Link

VIH

Set-up, Hold, and Release Times

LOW-HIGH-LOW

INPUT

tPLH1

tPHL1

PULSE

VOH

OUTPUT 1

VOL

tSK (x)

HIGH-LOW-HIGH

PULSE

tSK (x)

VOH

VOL

LVC Link

OUTPUT 2

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVCH162823A

3.3VCMOS18-BITBUSINTERFACEREGISTERWITH5VTOLERANTI/O

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

IDT

LVC

Device Type Package

XXXX

Bus-Hold

Family

Temp. Range

Thin Shrink Small Outline Package

Thin Very Small Outline Package

18-Bit Bus Interface Register

823A

162

Double-Density with Resistors, ±12mA

Bus-hold

-40°C to +85°C

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for Tech Support:

logichelp@idt.com

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www.idt.com

74LVCH162823APA [IDT]

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