843031I-01 [IDT]
FemtoClock Crystal-to-3.3V, 2.5V LVPECL Clock Generator;
| 型号： | 843031I-01 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FemtoClock Crystal-to-3.3V, 2.5V LVPECL Clock Generator |
| 文件： | 总16页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FemtoClock® Crystal-to-3.3V, 2.5V LVPECL
Clock Generator
843031I-01
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The 843031I-01 is an 10Gb Ethernet Clock Generator. The
843031I-01 uses an 18pF parallel resonant crystal.The 843031I-01
has excellent <1ps phase jitter performance, over the 1.875MHz -
20MHz integration range. The 843031I-01 is packaged in a small
8-pin TSSOP, making it ideal for use in systems with limited board
space.
• One differential 3.3V or 2.5V LVPECL output
• Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
• Output frequencies: 280MHz – 340MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 312.5MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.46ps (typical)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
COMMON CONFIGURATION TABLE
Inputs
Output Frequency
(MHz)
Multiplication
Value M/N
Crystal Frequency (MHz)
M
N
25
25
2
12.5
312.5
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
1
2
3
4
8
7
6
5
VCCA
VEE
VCC
Q
XTAL_OUT
XTAL_IN
nQ
OE
XTAL_IN
OSC
XTAL_OUT
Q
VCO
Phase
Detector
N = ÷2 (fixed)
nQ
843031I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
M = ÷25 (fixed)
G Package
Top View
843031I-01 REVISION A 10/15/15
1
©2015 Integrated Device Technology, Inc.
843031I-01 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
2
V
Power
Power
Analog supply pin.
Negative supply pin.
CCA
V
EE
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
3, 4
Input
5
6, 7
8
OE
Input
Output
Power
Pullup Output Enable pin. LVCMOS/LVTTL interface levels.
Differential clock outputs. LVPECL interface levels.
Power supply pin.
nQ, Q
V
CC
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
C
R
Input Capacitance
Input Pullup Resistor
4
pF
IN
51
kΩ
PULLDOWN
TABLE 3. OE FUNCTION TABLE
Input
OE
0
Outputs
Q/nQ
Hi-Z
1
Enabled
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
2
REVISION A 10/15/15
843031I-01 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
CC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to V + 0.5V
I
CC
Outputs, I
O
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
101.7°C/W (0 mps)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V = 3.3V 5ꢀ, TA = -40°C TO 85°C
CC
Symbol Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
V
V
I
Power Supply Voltage
3.135
3.465
3.465
12
V
V
CC
Analog Supply Voltage
Analog Supply Current
Power Supply Current
V
– 0.12
3.3
CCA
CC
mA
mA
CCA
I
105
EE
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V = 2.5V 5ꢀ, TA = -40°C TO 85°C
CC
Symbol Parameter
Test Conditions
Minimum
Typical
2.5
Maximum Units
V
V
I
Power Supply Voltage
2.375
2.625
2.625
12
V
V
CC
Analog Supply Voltage
Analog Supply Current
Power Supply Current
V
– 0.12
2.5
CCA
CC
mA
mA
CCA
I
90
EE
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, V = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
CC
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V
V
V
V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
2
V
V
+ 0.3
+ 0.3
V
V
CC
CC
CC
CC
CC
V
Input High Voltage
IH
1.7
-0.3
-0.3
CC
0.8
V
V
I
Input Low Voltage
IL
0.7
5
V
Input High Current
Input Low Current
V
= V = 3.465V or 2.625V
µA
µA
IH
CC
IN
I
V
= 3.465V or 2.625V, V = 0V
-150
IL
CC
IN
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
REVISION A 10/15/15
3
843031I-01 DATA SHEET
TABLE 4D. LVPECL DC CHARACTERISTICS, V = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
CC
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
V
- 1.4
- 2.0
V
V
- 0.9
- 1.7
V
V
V
OH
CC
CC
V
OL
CC
CC
V
0.6
1.0
SWING
NOTE 1: Outputs terminated with 50Ω to V - 2V.
CC
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
25
Mode of Oscillation
Frequency
22.4
27.2
40
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
7
pF
300
mW
NOTE: It is not recommended to overdrive the crystal input with an external clock.
TABLE 6A. AC CHARACTERISTICS, V = 3.3V 5ꢀ, TA = -40°C TO 85°C
CC
Symbol Parameter
Output Frequency
Test Conditions
Minimum Typical Maximum Units
f
280
312.5
340
MHz
OUT
RMS Phase Jitter ( Random);
NOTE 1
312.5MHz @ Integration Range:
1.875MHz - 20MHz
tjit(Ø)
t / t
0.46
ps
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
150
48
500
52
ps
ꢀ
R
F
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditons.
NOTE 1: Please refer to the Phase Noise Plots following this section.
TABLE 6B. AC CHARACTERISTICS, V = 2.5V 5ꢀ, TA = -40°C TO 85°C
CC
Symbol Parameter
Output Frequency
Test Conditions
Minimum Typical Maximum Units
f
280
312.5
340
MHz
OUT
RMS Phase Jitter ( Random);
NOTE 1
312.5MHz @ Integration Range:
1.875MHz - 20MHz
tjit(Ø)
t / t
0.48
ps
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
150
48
500
52
ps
ꢀ
R
F
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditons.
NOTE 1: Please refer to the Phase Noise Plots following this section.
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
4
REVISION A 10/15/15
843031I-01 DATA SHEET
TYPICAL PHASE NOISE AT 312.5MHZ AT 3.3V
0
-10
312.5MHz
RMS Phase Jitter (Random)
-20
1.875Mhz to 20MHz = 0.46ps (typical)
10Gb Ethernet Filter
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Raw Phase Noise Data
Phase Noise result by adding
10Gb Ethernet Filter to raw data
100
1K
10K
100K
1M
10M
100M
OFFSET FREQUENCY (HZ)
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
REVISION A 10/15/15
5
843031I-01 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
6
REVISION A 10/15/15
843031I-01 DATA SHEET
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The 843031I-01
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V and V should
3.3V or 2.5V
V
CC
10Ω
.01μF
.01μF
CC
CCA
be individually connected to the power supply plane through
vias, and 0.01µF bypass capacitors should be used for each
V
CCA
pin. Figure 1 illustrates this for a generic V pin and also shows
10μF
CC
that V requires that an additional10Ω resistor along with a
CCA
10µF bypass capacitor be connected to the V pin.
CCA
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The 843031I-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
FIGURE 2. CRYSTAL INPUt INTERFACE
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
REVISION A 10/15/15
7
843031I-01 DATA SHEET
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 4A
and 4B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it would
be recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component process
variations.
FOUT and nFOUT are low impedance follower outputs that generate
ECL/LVPECL compatible outputs. Therefore, terminating resistors
(DC current path to ground) or current sources must be used for
functionality.These outputs are designed to drive 50Ω transmission
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
8
REVISION A 10/15/15
843031I-01 DATA SHEET
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to V - 2V. For V = 2.5V, the V - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination
is shown in Figure 5C.
CC
CC
CC
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
R1
250
R3
250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
-
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driver
R2
62.5
R4
62.5
R3
18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
REVISION A 10/15/15
9
843031I-01 DATA SHEET
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 843031I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843031I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 105mA = 363.8mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
Total Power
(3.465V, with all outputs switching) = 363.8mW + 30mW = 393.8mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + T
A
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
= Ambient Temperature
T
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.394W * 90.5°C/W = 120.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7.THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
10
REVISION A 10/15/15
843031I-01 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V – 2V.
CC
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
)
(VCC_MAX – VOH_MAX = 0.9V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
)
(VCC_MAX – VOL_MAX = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/R ] * (VCC_MAX – VOH_MAX) = [(2V– (V _MAX – VOH_MAX /R ] * (VCC_MAX – VOH_MAX) =
L
CC
L
[(2V– 0.9V)/50Ω] * 0.9V = 19.8mW
))
– VOL_MAX /R ] * (VCC_MAX – VOL_MAX) =
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/R ] * (VCC_MAX – VOL_MAX) = [(2V– (V
_MAX
L
CC
L
[(2V– 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
REVISION A 10/15/15
11
843031I-01 DATA SHEET
RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA
θJA by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TRANSISTOR COUNT
The transistor count for 843031I-01 is: 2377
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
12
REVISION A 10/15/15
843031I-01 DATA SHEET
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
REVISION A 10/15/15
13
843031I-01 DATA SHEET
TABLE 10. ORDERING INFORMATION
Part/Order Number
843031AGI-01LF
843031AGI-01LFT
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
AI01L
AI01L
8 Lead “Lead-Free” TSSOP
8 Lead “Lead-Free” TSSOP
tape & reel
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
14
REVISION A 10/15/15
843031I-01 DATA SHEET
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
T3
2
1
A
Added OE Function Table.
1/23/07
Common Configuration Table - corrected typo in Multiplication Value M/N column from 25
A
to 12.5.
11/11/08
T10
T5
14
Ordering Information Table - added lead-free marking.
1
4
8
Deleted HiPerClockS references.
Crystal Characteristics Table - added note.
Deleted application note, LVCMOS to XTAL Interface.
Deleted quantity from tape and reel.
A
A
10/22/12
10/15/15
T10
T10
14
14
Ordering Information - removed leaded devices.
Updated data sheet format.
FEMTOCLOCK® CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
REVISION A 10/15/15
15
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, California 95138
Sales
800-345-7015 or +408-284-8200
Fax: 408-284-2775
www.IDT.com
Technical Support
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth-
er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.
This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason-
ably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or
their respective third party owners.
Copyright 2015. All rights reserved.
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