9248AG-150LNT [IDT]
Processor Specific Clock Generator, 200MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48;
| 型号： | 9248AG-150LNT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 200MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总13页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-150
Integrated
Circuit
Systems, Inc.
Frequency Generator for Multi-Processor Servers
Recommended Application:
ServerWorks Grand Champion Systems
Pin Configuration
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PCICLK
VDD48
FS0/48MHz
FS1/48MHz#
GND48
SEL100/133
GNDPCI
VDDA
GNDA
PD#
Output Features:
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
•
•
•
8 - Differential CPU Clock Pairs @ 3.3V
1 - 3V 33MHz PCI clocks
1 - 48MHz clock
VDDCPU
CPUCLKT0
CPUCLKC0
GNDCPU
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT2
CPUCLKC2
GNDCPU
CPUCLKT3
CPUCLKC3
VDDCPU
REF
VDDCPU
CPUCLKT4
CPUCLKC4
GNDCPU
CPUCLKT5
CPUCLKC5
VDDCPU
CPUCLKT6
CPUCLKC6
GNDCPU
CPUCLKT7
CPUCLKC7
VDDCPU
MULTSEL0
MULTSEL1
GND
•
•
1 - Inverted 48MHz clock
1 - 14.318MHz reference output
Features:
•
•
•
Up to 200MHz frequency support
Support power management: Power Down Mode
Supports Spread Spectrum modulation: 0 to -0.5%
down spread.
•
•
Uses external 14.318MHz crystal
Select logic for Differential Swing Control, Test mode,
Tristate, Power down, Spread Spectrum.
SPREAD#
GNDREF
X1
X2
VDDREF
GNDI REF
I REF
VDDI REF
•
•
External resistor for current reference
FS pins for frequency select
Key Specifications:
48-Pin SSOP and TSSOP
•
•
•
•
PCI Output jitter <500ps
CPU Output jitter <150ps
48MHz Output jitter <350ps
REF Output jitter < 1000ps
Block Diagram
Functionality
SEL133/100 FS0 FS1
Function
Active 100MHz
100MHz Test Mode
100MHz Test Mode
Tristate all outputs
Active 133MHz
133MHz Test Mode
Active 200MHz
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PLL2
48MHz
48MHz#
X1
X2
XTAL
OSC
REF
PLL1
Spread
Spectrum
CPUCLKT (7:0)
CPUCLKC (7:0)
CPU
DIVDER
8
8
PCI
DIVDER
PCICLK
Analog Power Groups
VDD48, GND48 = 48MHz, PLL2
VDDA=VDD (core supply voltage 3.3V)
GNDA=Ground for core supply
PD#
SPREAD#
Control
Logic
MULTSEL(1:0)
SEL100/133
FS(1:0)
Config.
Reg.
Digital Power Group
I REF
VDDREF, GNDREF = REF, Xtal
0352G—08/04/06
ICS9248-150
General Description
ICS9248-150 is a main clock for ServerWorks Grand Champion Systems.
Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. ICS9248-150 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over process and temperature variations.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
PCICLK
OUT
PCI clock output
2, 6, 12, 18, 24,
31, 37, 43,
VDD
PWR
3.3V power supply
FS0
48MHz
FS1
IN
OUT
IN
Frequency select pin
48MHz clock output
Frequency select pin
3
4
48MHz#
OUT
Inverted 48MHz clock output
5, 9, 15, 21, 28,
34, 40, 47
GND
PWR
OUT
Ground pins for 3.3V supply
"True" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
33, 36, 39, 42, 16,
13, 10, 7
CPUCLKT (7:0)
"Complementary" clocks of differential pair CPU outputs. These
are current outputs and external resistors are required for
voltage bias.
32, 35, 38, 41, 17,
14, 11, 8
CPUCLKC (7:0)
OUT
19
20
REF
OUT
IN
Reference output 14.318MHz
Invokes Spread Spectrum functionality on the Differential host
clocks, Active Low
SPREAD#
22
23
X1
X2
X2 Crystal Input 14.318MHz Crystal input
X1 Crystal Output 14.318MHz Crystal output
VDDI REF
VDDA,
25, 46
PWR
Analog power supply 3.3V
This pin establishes the reference current for the CPUCLK
pairs. This pin takes a fixed precision resistor tied to ground in
order to establish the required current.
26
I REF
OUT
29, 30
44
MULTSEL(1:0)
PD#
IN
IN
CPU swing select inputs
Invokes power-down mode. Active Low.
GNDI REF
GNDA
27, 45
48
PWR
IN
Analog Ground pins for 3.3V supply
SEL100/133
CPU Frequency Select. Low=100MHz, High=133MHz
0352G—08/04/06
2
ICS9248-150
Truth Table
SEL
FS0
CPUCLK
MHz
PCICLK
MHZ
48
MHz
FS1
133/100
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100
100
33
33
48
Disable
Disable
Tristate
48
100
Disable
Tristate
33
Tristate
133
133
33
Disable
48
200
33
TCLK/2
TCLK/8
TCLK/2
CPUCLK Buffer Configuration
Conditions
Configuration
Load
Min
Max
All combinations of
Iout Vdd = nominal (3.30V) M0, M1 and Rr shown
Nominal test load for
given configuration
-7% I nominal +7% I nominal
in table below
All combinations of
M0, M1 and Rr shown
in table below
Nominal test load for
given configuration
-12% I
nominal
+12% I
nominal
Iout
Vdd = 3.30 5%
0352G—08/04/06
3
ICS9248-150
CPUCLK Swing Select Functions
Reference R,
Iref=
Vdd/(3*Rr)
Board Target
Trace/Term Z
Output
Current
Voh @ Z,
Iref=2.32mA
MULTSEL0
MULTSEL1
Rr = 475 1%
Iref = 2.32mA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.71V @ 60
0.59V @ 50
0.85V /2 60
0.71V @ 50
0.56V @ 60
0.47V @ 50
0.99V @ 60
0.82V @ 50
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 221 1%
Iref = 5mA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.75V @ 30
0.62V @ 20
0.90V @ 30
0.75V @ 20
0.60 @ 20
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
0.5V @ 20
1.05V @ 30
0.84V @ 20
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
0352G—08/04/06
4
ICS9248-150
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
TYP
MAX
VDD + 0.3
0.8
UNITS
V
2
VSS - 0.3
-5
VIL
V
IIH
VIN = VDD
5
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
Input Low Current
IIL2
-200
Operating Supply
Current
Powerdown Current
Input Frequency
Pin Inductance
IDD3.3OP
mA
CL = 0 pF; Select @ 100 MHz
181
250
60
IDD3.3PD CL = 0 pF; Input address to VDD or GND
mA
MHz
nH
52
14.318
Fi
VDD = 3.3 V
Lpin
7
5
6
CIN
Logic Inputs
pF
Input Capacitance1
COUT
CINX
Output pin capacitance
pF
X1 & X2 pins
27
45
8
10.5
8
10.5
10
pF
ms
ms
ms
ms
ns
CPU Freq. = 100/133 MHz
CPU Freq. = 200 MHz
CPU Freq. = 100/133 MHz
CPU Freq. = 200 MHz
Clk Stabilization1, 2
Clk Recovery1, 3
TSTAB
TREC
tPZH,tPZL Output enable delay (all outputs)
1
1
Delay1
t
PHZ,tPLZ
Output disable delay (all outputs)
10
ns
1Guaranteed by design, not 100% tested in production.
2From VDD = 3.3V to 1% of target frequency
3From deassertion of PD# to 1% of target frequency
0352G—08/04/06
5
ICS9248-150
Electrical Characteristics - CPU
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Current Source
Output Impedance
Voltage High
SYMBOL
Zo1
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Ω
VO = Vx
3000
1
VHigh
VLow
Vovs
Vuds
Statistical measurement on single ended 660
signal using oscilloscope math function. -150
Measurement on single ended signal
770
5
756
-7
850
150
1150
1
1
1
1
1
mV
mV
Voltage Low
Max Voltage
Min Voltage
using absolute value.
-300
175
175
45
1
Rise Time
Fall Time
tr2B
VOL = 20%, VOH = 80%
324
501
50
700
700
55
ps
ps
%
%
1
1
1
1
1
1
1
tf2B
VOH = 80%, VOL = 20%
VDD = 3.3V
Diff. Crossover Volta
Duty Cycle
Vx
1
dt2B
VT = 50%
45
51.2
83.8
78.5
86
55
1
Skew CPUT0:7
Skew CPU C0:7
Jitter
tsk2B
VT = 50%
VT = 50%
VT = 50%
100
100
150
ps
ps
ps
1
tsk2B
1
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
2 IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
14.318
48
MAX UNITS
MHz
1
RDSP1
VO = VDD*(0.5)
20
60
Ω
V
1
VOH
IOH = -1 mA
2.4
1
VOL
IOL = 1 mA
0.4
-23
27
4
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
-29
29
1
mA
mA
ns
ns
%
IOH
1
IOL
1
tr1
1.6
2.4
1
Fall Time
tf1
1
4
1
Duty Cycle
dt1
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
45
53.5
55
1
Skew
Jitter
tsk1
N/A
1000
ps
ps
1
tjcyc-cyc
305
1Guaranteed by design, not 100% tested in production.
0352G—08/04/06
6
ICS9248-150
Electrical Characteristics - PCI
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
33.3
33
MAX UNITS
MHz
1
Ω
RDSP1
VO = VDD*(0.5)
12
55
1
VOH
IOH = -1 mA
2.4
V
V
1
VOL
IOL = 1 mA
0.55
-33
38
2
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
-33
30
mA
mA
ns
ns
%
IOH
1
IOL
1
tr1
0.5
0.5
1.2
1.2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
45
49.9
55
1
Skew
Jitter
tsk1
N/A
500
ps
ps
1
tjcyc-cyc
139.7
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
48
MAX UNITS
MHz
1
RDSP1
VO = VDD*(0.5)
20
48
60
Ω
V
1
VOH
IOH = -1 mA
IOL = 1 mA
2.4
1
VOL
0.4
-23
27
4
V
1
V
OH@MIN = 1.0 V, V OH@MAX = 3.135 V
-29
29
1
mA
mA
ns
ns
%
IOH
1
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
IOL
1
tr1
1.3
1.6
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
1
4
1
Duty Cycle
dt1
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
45
52.5
55
N/A
350
1
Skew
Jitter
tsk1
ps
ps
1
tjcyc-cyc
175
1Guaranteed by design, not 100% tested in production.
0352G—08/04/06
7
ICS9248-150
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down.When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal.The power down latency should be as short as possible
but conforming to the sequence requirements shown below.
PD#
CPUCLKT
CPUCLKC
VCO
Crystal
Notes:
1. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock.
0352G—08/04/06
8
ICS9248-150
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
hh xx 4455°°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
15.75
MAX
16.00
MIN
.620
MAX
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS9248yF-150LN-T
Example:
ICS XXXX y F - PPP LN - T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0352G—08/04/06
9
ICS9248-150
c
In Millimeters
In Inches
N
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
E1
e
L
6.00
0.50 BASIC
0.45
6.20
.236
0.020 BASIC
.018
.244
a
D
0.75
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
VARIATIONS
A1
D mm.
D (inch)
- C --
N
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
e
SEATING
PLANE
48
b
Reference Doc.: JEDEC Publication 95, MO-153
aaa
C
10-0039
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
(240 mil)
Ordering Information
ICS9248yG-150LN-T
Example:
ICS XXXX y G - PPP LN - T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0352G—08/04/06
10
ICS9248-150
Revision History
Rev.
Issue Date Description
Page #
E
F
G
6/9/2005 Removed PCI Skew from Electrical Characteristics Table.
3/29/2006 Updated Electrical Characteristics CPU Table.
8/4/2006 Added LN to Ordering Information.
7
6
9-10
0352G—08/04/06
11
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150
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9248-150 (Server/Workstation Chipsets)
Description
ServerWorks Grand Champion Systems
Market Group
PC CLOCK
Additional Info
Output Features: • 8 - Differential CPU Clock Pairs @ 3.3V • 1 - 3V 33MHz PCI clocks • 1 - 48MHz clock • 1 - Inverted 48MHz clock • 1 -
14.318MHz reference output
Related Orderable Parts
Attributes
9248AG-150LN
9248AG-150LNT
3.3 V (PAG48)
3.3 V (PAG48)
Voltage
Package
Speed
TSSOP 48
NA
TSSOP 48
NA
C
C
Temperature
Active
Yes
Active
No
Status
Sample
152
1000
1000
Minimum Order Quantity
Factory Order Increment
38
Related Documents
Type
Title
Size
Revision Date
Datasheet
Model - IBIS
9248-150 Datasheet
9248-150 IBIS Model
146 KB
132 KB
08/04/2006
03/23/2006
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