9248AG-192T [IDT]
Processor Specific Clock Generator, 66.6MHz, PDSO28, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28;
| 型号： | 9248AG-192T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 66.6MHz, PDSO28, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总15页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-192
Integrated
Circuit
Systems,Inc.
Frequency Timing Generator for Transmeta Systems
Pin Configuration
RecommendedApplication:
Transmeta
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GNDREF
X1
VDDREF
REF
CPU_STOP#
VDDLCPU
GNDLCPU
CPUCLK0
PCI_STOP#
GND_Core
VDD_Core
SEL66/60#
VDD48
GND48
48MHz/CPU3.3v_2.5V#sel
24-48MHz/Sel48_24#
OutputFeatures:
X2
PD#
•
1CPU(2.5V or 3.3V selectable) up to 66.6MHz &
overclocking of 66MHz.
PCICLK0
PCICLK1
PCICLK2
GNDPCI
VDDPCI
PCICLK3
PCICLK4
PCICLK5
SDATA
SCLK
•
6 PCI (3.3V) @ 33.3MHz (all are free running
selectable).
•
•
•
1 REF (3.3V) at 14.318MHz.
1 48MHz (3.3V).
1 24_48MHz selectable output.
Features:
•
•
•
•
Supports Spread Spectrum modulation for CPU and
28-Pin TSSOP
PCI clocks, default -0.4 downspread.
Efficient Power management scheme through stop
clocks and power down modes.
Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
28-pin TSSOP package, 4.40mm (173mil).
SkewCharacteristics:
•
•
•
CPU – CPU <175ps
PCI – PCI < 500ps
CPU(early) – PCI = 1.5ns – 4ns.
Block Diagram
PLL2
48MHz
24_48MHz
/ 2
X1
X2
XTAL
OSC
REF
PLL1
Spread
CPU
DIVDER
Stop
CPUCLK0
Spectrum
SEL48_24#
CPU3.3V_2.5V#sel
SEL66/60#
PD#
Control
Logic
PCI
DIVDER
Stop
PCICLK (5:0)
6
PCI_STOP#
CPU_STOP#
SDATA
Power Groups
Config.
Reg.
VDD_Core, GND_Core = PLL core
VDDREF, GNDREF = REF, X1, X2
VDDPCI, GNDPCI = PCICLK (5:0)
VDD48, GND48 = 48MHz (1:0)
SCLK
0540F—10/27/05
ICS9248-192
Pin Descriptions
Pin number
Pin name
GNDREF
X1
Type
Power Ground for 14.318 MHz reference clock outputs
Input 14.318 MHz crystal input
Output 14.318 MHz crystal output
Asynchronous active low input pin used to power down the device
Description
1
2
3
X2
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 3ms.
4
PD#
Input
12, 11, 10, 7, 6, 5
PCICLK (5:0)
GNDPCI
VDDPCI
Output 3.3V PCI clock outputs, free running selectable
Power Ground for PCI clock outputs
Power 3.3V power for the PCI clock outputs
8
9
Sel48_24#
24_48MHz
SDATA
Input
Selects 24MHz (0) or 48MHz (1) output
15
Output Selectable output either 24MHz or 48MHz
Data pin for I2C circuitry 5V tolerant
13
14
I/O
Clock pin of I2C circuitry 5V tolerant
IN
SCLK
3.3 (1) or 2.5 (0) VDD buffer strength selection, has pullup to VDD,
nominal 30K resistor.
CPU3.3-2.5#
Input
16
3.3V 48 MHz clock output, fixed frequency clock typically used with
USB devices
48MHz
Output
17
18
GND48
VDD48
Power Ground for 48 MHz clocks
Power 3.3V power for 48/24 MHz clocks
Control for the frequency of clocks at the
CPU & PCICLK output pins.
19
SEL 66/60#
Input
"0" = 60 MHz. "1" = 66.6 MHz.
The PCI clock is multiplexed to run at 33.3 MHz
for both selected cases.
20
21
VDD_Core
GND_Core
Power Isolated 3.3V power for core
Power Isolated ground for core
Synchronous active low input used to stop the PCICLK in active low
state. It will not effect PCICLK_F or any other outputs.
22
PCI_Stop#
Input
23
24
25
CPUCLK0
GNDLCPU
VDDLCPU
Output CPU clock outputs selectable 2.5V or 3.3V.
Power Ground for CPU clock outputs
Power 2.5V or 3.3V power for CPU clock outputs
Asynchronous active low input pin used to stop the CPUCLK in
26
CPU_STOP#
Input
active low state, all other clocks will continue to run. The CPUCLK
will have a "Turnon " latency of at least 3 CPU clocks.
27
28
REF
VDDREF
Output 3.3V 14.318 MHz reference clock output
Power 3.3V power for 14.318 MHz reference clock outputs.
0540F—10/27/05
2
ICS9248-192
CPU Select Functions
SEL 66/60#
CPU (MHz)
60MHz
0
1
66.6MHz
PowerManagement
Clock Enable Configuration
CPU_STOP# PCI_STOP# PWR_DWN#
CPUCLK
Low
PCICLK
Low
REF
Crystal
VCOs
Off
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Stopped
Off
Low
Low
Running Running
Running
Running
Running
Running
Low
33.3 MHz Running Running
Low Running Running
60/66.6MHz
60/66.6MHz 33.3 MHz Running Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During
power up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of
the running clock.The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock
network charging circuitry.Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-192PowerManagementRequirements
Latency
SIGNAL
SIGNAL STATE
No. of rising edges of free
running PCICLK
0 (Disabled)2
1 (Enabled)1
1
1
1
CPU_ STOP#
PCI_STOP#
PD#
0 (Disabled)2
1 (Enabled)1
1
1 (Normal Operation)3
0 (Power Down)4
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
0540F—10/27/05
3
ICS9248-192
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the
latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
2.
3.
4.
5.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the
controller.The bytes must be accessed in sequential order from lowest to highest byte with the ability
to stop after any complete byte has been transferred. The Command code and Byte count shown above
must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is
issued.
6.
At power-on, all registers are set to a default condition, as shown.
0540F—10/27/05
4
ICS9248-192
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit2 Bit7 Bit6 Bit5 Bit4
FS4 FS3 FS2 FS1 FS0
CPU
60
PCI
30
Spread %
PWD
Bit
0
0
0
0
0
-0.4 % down spread
60
60
60
30
30
30
-0.6 % down spread
-0.8 % down spread
-1.0 % down spread
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
1
0
0
66.6
33.3
-0.4 % down spread
66.6
66.6
66.6
33.3
33.3
33.3
-0.6 % down spread
-0.8 % down spread
-1.0 % down spread
2% over-clocking
4% over-clocking
6% over-clocking
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
67.32
68.64
69.96
33.66
34.32
34.98
0
1
0
1
1
72.6
36.3
10% over-clocking
61.5
63
64
30.75
31.5
32
over-clocking
over-clocking
over-clocking
over-clocking
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
65
32.5
00000
1
1
0
0
0
0
0
0
0
1
60
30
+/- 0.5% center spread
+/- 0.5% center spread
Bit
66.6
33.3
2,7:4
50
48
25
24
under-clocking
under-clocking
2% under-clock
4% under-clock
6% under-clock
10% under-clock
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
58.8
57.6
56.4
54
29.4
28.8
28.2
27
1
1
0
0
0
60
30
-1.4 % down spread
60
60
60
30
30
30
-1.6 % down spread
-1.8 % down spread
-2.0 % down spread
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
1
1
1
0
0
66.6
33.3
-1.4 % down spread
66.6
66.6
66.6
33.3
33.3
33.3
-1.6 % down spread
-1.8 % down spread
-2.0 % down spread
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
Hardware latch inputs can only access these frequencies
0-Frequency is seleced by hardware select. Latched input
1-Frequency is seleced by Bit 2, 7:4
Bit3
0
Bit1
Bit0
0-Normal 1-Spread spectrun Enabled
0-Running 1-Tristate all outputs
0
0
Note: PWD = Power-Up Default
0540F—10/27/05
5
ICS9248-192
Byte 2: Stop Clocks
Byte 1: PCI Stop
BIT PIN# PWD
DESCRIPTION
48MHz
BIT PIN# PWD
DESCRIPTION
PCICLK5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16
15
23
27
-
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
12
11
10
7
1
1
48_24MHz
CPUCLK0
REF
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Reserved
Reserved
1
1
1
1
X
X
X
X
Reserved
Reserved
Reserved
Reserved
6
1
-
5
1
-
-
X
X
-
-
Note:
1 = Inactive
0 = Active
Note:
1 = Inactive
0 = Active
Byte3:Free-RunningEnable
Byte4:Reserved
BIT PIN# PWD
DESCRIPTION
PCICLK5
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
12
11
10
7
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Reserved
Reserved
1
1
6
1
5
1
-
X
X
-
Note:
0 = Not free-running (controlled by PCI_STOP# pin)
1 = Free-running (can override Byte1 PCI Stop Control)
Byte6:Reserved
BIT PIN# PWD
Byte5:Reserved
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: PWD = Power-Up Default
0540F—10/27/05
6
ICS9248-192
CPU_STOP#Timing Diagram
CPUSTOP#isanasychronousinputtotheclocksynthesizer.ItisusedtoturnofftheCPUCLKsforlowpoweroperation.
CPU_STOP#issynchronizedbytheICS9248-192.TheminimumthattheCPUCLKisenabled(CPU_STOP#highpulse)
is 100 CPUCLKs.All other clocks will continue to run while the CPUCLKs are disabled.The CPUCLKs will always be
stoppedinalowstateandstartinsuchamannerthatguaranteesthehighpulsewidthisafullpulse.CPUCLKonlatency
is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PCI_STOP# (High)
PD# (High)
CPUCLK
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may
exist. This signal is synchronized to the CPUCLKs inside the ICS9248-192.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP#Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-192. It is used to turn off the PCICLK clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-192 internally. The minimum that the PCICLK clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks.PCICLK clocks are stopped in a low state and started
with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency
is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-192 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-192.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
0540F—10/27/05
7
ICS9248-192
PD#Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input.This signal is synchronized internally by the ICS9248-192 prior to its control
action of powering down the clock synthesizer.Internal clocks will not be running after the device is put in power down
state.When PD# is active (low) all clocks are driven to a low state and held prior to turning off theVCOs and the crystal
oscillator.Thepoweronlatencyisguaranteedtobelessthan3ms.ThepowerdownlatencyislessthanthreeCPUCLK
cycles.PCI_STOP# and CPU_STOP# are don’t care signals during the power down operations.
CPUCLK
(Internal)
PCICLK
(Internal)
PD#
CPUCLK
PCICLK_F, PCICLK
REF
INTERNAL
VCOs
INTERNAL
CRYSTAL OSC.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
0540F—10/27/05
8
ICS9248-192
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDDL = 2.5V, VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD + 0.3
0.8
UNITS
V
VIL
VSS - 0.3
V
IIH
VIN = VDD
5
mA
mA
mA
mA
mA
µA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
IDD2.5OP66 CL = 0 pF; Select @ 66.6MHz
IDD3.3OP66 CL = 0 pF; Select @ 66.6MHz
15
80
Operating Supply
Current
CL = 0 pF; With input address to Vdd or
GND
Power Down
Supply Current
Input frequency
Input Capacitance1
IDD3.3PD
600
Fi
VDD = 3.3 V;
11
27
14.318
16
5
MHz
pF
CIN
Logic Inputs
CINX
Ttrans
TSTAB
X1 & X2 pins
45
3
pF
Transition Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
ms
ms
ns
From VDD = 3.3 V to 1% target Freq.
TL
3
TCPU-PCI VT = 1.5 V; V = 1.25 V
1.5
4
1Guaranteed by design, not 100% tested in production.
0540F—10/27/05
9
ICS9248-192
Electrical Characteristics - CPUCLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
IOH = -12.0 mA
MIN
1.8
TYP
MAX UNITS
V
IOL = 12 mA
0.4
-27
V
mA
mA
ns
ns
%
VOH = 1.7 V
IOL2B
VOL = 0.7 V
27
0.4
0.4
44
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.6
1.6
1
Fall Time
tf2B
1
Duty Cycle
dt2B
55
1
Skew
tsk2B
VT = 1.25 V
175
250
+250
ps
ps
ps
1
tjcyc-cyc2B VT = 1.25 V
Jitter
1
tjabs2B
VT = 1.25 V
-250
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V , VDDL = 2.5V, +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP
MAX UNITS
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
V
VOL5
0.4
-22
V
mA
mA
ns
ns
%
IOH5
IOL5
16
45
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4
4
Fall Time1
Duty Cycle1
dt5
55
tjcyc-cyc5 VT = 1.5 V, REF
tjabs5 VT = 1.5 V, REF
tjcyc-cyc5 VT = 1.5 V, 48 MHz
tjabs5 VT = 1.5 V, 48 MHz
1000
800
500
800
ps
ps
ps
ps
Jitter1
Jitter1
0540F—10/27/05
10
ICS9248-192
Electrical Characteristics - 48MHz
TA = 0 - 70°C; VDD = 3.3 V , VDDL = 2.5V, +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP
MAX UNITS
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
V
VOL5
0.4
-22
V
mA
mA
ns
ns
%
IOH5
IOL5
16
45
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.2
1.2
Fall Time1
Duty Cycle1
dt5
55
tjcyc-cyc5 VT = 1.5 V, REF
tjabs5 VT = 1.5 V, REF
tjcyc-cyc5 VT = 1.5 V, 48 MHz
tjabs5 VT = 1.5 V, 48 MHz
1000
800
500
800
ps
ps
ps
ps
Jitter1
Jitter1
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V, VDDL = 2.5V +/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
IOL1
CONDITIONS
MIN
2.1
TYP
MAX UNITS
V
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-22
57
V
mA
mA
ns
ns
%
16
45
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
Fall Time1
Duty Cycle1
tf1
2
dt1
55
Skew1
tsk1
VT = 1.5 V
500
500
500
ps
ps
ps
1
tjcyc-cyc
VT = 1.5 V
VT = 1.5 V
Jitter
tjabs1
1Guaranteed by design, not 100% tested in production.
0540F—10/27/05
11
ICS9248-192
In Millimeters
SYMBOL
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
MIN
-
MAX
.047
.006
.041
.012
.008
A
A1
A2
b
0.05
0.80
0.19
0.09
.002
.032
.007
.0035
c
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
D
E
E1
e
4.30
4.50
0.65 BASIC
0.75
.169
.177
0.0256 BASIC
L
0.45
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
0°
-
8°
0°
-
8°
α
aaa
0.10
.004
VARIATIONS
D mm.
D (inch)
N
MIN
9.60
MAX
9.80
MIN
.378
MAX
28
.386
7/6/00 Rev C
MO-153 JEDEC
Doc.# 10-0035
4.40 mm. Body, 0.65 mm. pitch TSSOP
(0.0256Inch)
(173 mil)
Ordering Information
ICS9248yG-192LF-T
Example:
ICS XXXX y G - PPP LF - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Lead Free, RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
0540F—10/27/05
12
ICS9248-192
Revision History
Rev.
Issue Date Description
Page #
F
10/27/2005 Added LF to Ordering Information
12
0540F—10/27/05
13
Global Sites
Search Entire Site
Contact IDT | Investors | Press
Email | Print
Document Search | Package Search | Parametric Search | Cross Reference Search | Green & RoHS | Calculators | Thermal Data | Reliability & Quality | Military
Home > Products > Timing Solutions > PC-Notebook-Server Clocks > Clock Synthesizer by Chipset Vendor > Desktop Chipsets > 9248-192
You may also like...
Add to myIDT [?]
9248-192 (Desktop Chipsets)
Description
Frequency Timing Generator for Transmeta Systems
Market Group
PC CLOCK
Additional Info
Output Features: • 1CPU(2.5V or 3.3V selectable) up to 66.6MHz & overclocking of 66MHz. • 6 PCI (3.3V) @ 33.3MHz (all are free running
selectable). • 1 REF (3.3V) at 14.318MHz. • 1 48MHz (3.3V). • 1 24_48MHz selectable output.
Related Orderable Parts
Attributes
9248AG-192
9248AG-192LF
9248AG-192LFT
9248AG-192T
3.3 V (PG28)
3.3 V (PGG28)
3.3 V (PGG28)
3.3 V (PG28)
TSSOP 28
NA
Voltage
Package
Speed
TSSOP 28
NA
TSSOP 28
NA
TSSOP 28
NA
C
C
C
C
Temperature
Active
Yes
Active
Yes
Active
No
Active
No
Status
Sample
144
144
1000
1000
1000
Minimum Order Quantity
Factory Order Increment
48
48
1000
Related Documents
Type
Title
9248-192 Datasheet
Size
Revision Date
Datasheet
171 KB
03/23/2006
Home | Site Map | About IDT | Press Room | Investor Relations | Trademark | Privacy Policy | Careers | Register | Contact Us
Use of this website signifies your agreement to the acceptable use and privacy policy. Copyright 1997-2007 Integrated Device Technology, Inc. All Rights Reserved.
Node: www.idt.com
相关型号：
9248AG-92LF
Processor Specific Clock Generator, 100MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, GREEN, TSSOP-48
IDT
9248AG-92LFT
Processor Specific Clock Generator, 100MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, GREEN, TSSOP-48
IDT
9248BF-138LF
Processor Specific Clock Generator, 166.67MHz, PDSO48, 0.300 INCH, GREEN, MO-118, SSOP-48
IDT
9248BF-138LFT
Processor Specific Clock Generator, 166.67MHz, PDSO48, 0.300 INCH, GREEN, MO-118, SSOP-48
IDT
9248BF-195
Processor Specific Clock Generator, 140MHz, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48
IDT
©2020 ICPDF网 联系我们和版权申明