9248AG-185T [IDT]
Clock Generator, PDSO28;
| 型号： | 9248AG-185T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO28 光电二极管 |
| 文件： | 总12页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-185
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
& K6
Pin Configuration
RecommendedApplication:
VIA PM133 chipset
REF1/FREE_SEL*1
VDDL
CPUCLK0/_F
CPUCLK1
GND
CLK_STOP#
SDRAM0/_F
SDRAM1
SDRAM2
GND
VDDSDR
SDRAM3
SDRAM4
VDD48
OutputFeatures:
VDD
REF0
GND
1
2
3
4
5
6
ꢀ
8
9
10
11
12
13
14
28
2ꢀ
26
25
24
23
22
21
20
19
18
1ꢀ
16
15
•
•
•
•
•
2 - CPUs @ 2.5V
5 - SDRAM @ 3.3V
3 - PCI @ 3.3V,
1 - 48MHz, @ 3.3V fixed.
2 - REF @ 3.3V, 14.318MHz.
X1
X2
VDDPCI
1*PCICLK_F
GND
1, 2FS1/PCICLK0
Features:
BUFFER_IN
1PCICLK1
PCI_STOP#
GND
•
•
Up to 133MHz frequency support
Support power management:PCI_STOP &
CLK_STOP
*FS0/48MHz
•
Spread spectrum for EMI control (-0.5% down
spread).
28-Pin SSOP/TSSOP
•
•
Uses external 14.318MHz crystal
FS pins for frequency select
* Internal Pull-up Resistor of 120K to VDD
1. These pin will have 2X drive strength
2. FS1 is a pull down
KeySpecifications:
•
•
•
•
•
CPU – PCI Skew: 1-4ns
PCI – PCI Skew: 500ps
CPU – CPU Skew: 1ꢀ5ps
CPU Jitter: 250ps (cyc-cyc)
PCI Jitter: 500ps (cyc-cyc)
Block Diagram
Frequency Select
Down
Spread
PLL2
48MHz
FS1
FS0 CPUCLK PCICLK
0
0
1
1
0
1
0
1
66.66
100.00
97.00
33.33
33.33
32.33
33.33
-0.5%
-0.5%
-0.5%
-0.5%
X1
X2
XTAL
OSC
REF (1:0)
CPUCLK1
2
CPU
DIVDER
Stop
Stop
PLL1
Spread
Spectrum
CPUCLK0/_F
133.33
BUFFER_IN
SDRAM (4:1)
SDRAM0/_F
4
2
Control
Logic
PCI
DIVDER
PCI_STOP#
CLK_STOP#
FS (1:0)
Stop
PCICLK (1:0)
PCICLK_F
Config.
Reg.
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9248-185RevE- 12/15/08
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-185
General Description
The ICS9248-185 is the single chip clock solution for Notebook designs using the 440BX or the VIA Apollo Pro 133 style
chipset. It provides all necessary clock signals for such a system. The ICS9248-185 provides CPU and PCI clocks with
continous spread spectrum. The ICS9248-185 employs a proprietary closed loop design, which tightly controls the percentage
of spreading over process and temperature variations.
Pin Descriptions
PIN
NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 6, 15, 18, VDD
PWR Power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER buffer
for ISA BUS loads
2
REF0
OUT
3, 8, 13,
19, 24
GND
PWR Ground
4
5
7
X1
IN
Crystal input, has internal load cap (36pF) and feedback resistor from X2
X2
OUT Crystal output, nominally 14.318MHz.
PCICLK_F
FS11, 2
OUT Free running PCI clock not affected by PCI_STOP# for power management.
IN
OUT PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early)
IN Input to Fanout Buffers for SDRAM outputs.
Frequency select pin. Latched Input.
9
PCICLK0
BUFFER IN
PCICLK1
10
11
OUT PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early)
Halts PCICLK clocks at logic 0 level, when input low
(In mobile mode, MODE=0)
12
14
PCI_STOP#
IN
FS01, 2
48MHz
IN
OUT 48MHz output clock
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
Frequency select pin. Latched Input
16, 17, 20,
21
SDRAM (4:1)
SDRAM0/_F
CLK_STOP#
OUT
22
OUT Either free running SDRAM or stoppable depending on FREE_SEL
This asynchronous input halts CPUCLKs, & SDRAMs at logic "0" level
when driven low.
23
IN
25
26
27
CPUCLK1
CPUCLK0/_F
VDDL
OUT CPU clock output, powered by VDDL
OUT Either free running CPUCLK or stoppable depending on FREE_SEL
PWR Supply for CPU clocks 2.5V
Selects CPUCLK0/_F and SDRAM0/_F to be either free running or
stoppable by CLK_STOP#. When FREE_SEL is set to (0) low the above
clocks are free running - when set to (1) high, the clocks are stoppable.
FREE_SEL
REF1
IN
28
OUT 14.318 MHz reference clock.
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2
ICS9248-185
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
V
VIL
VSS-0.3
CL = 30 pF; Select @ 66MHz
CL = 30 pF; Select @ 100MHz
CL = 30 pF; Select @ 133MHz
CL = 0 pF; Input address VDD or GND
VDD = 3.3 V
63
67
73
150
Operating Supply
Current
IDD3.3OP
mA
170
180
IDDPD
Fi
µA
MHz
Powerdown Current
Input Frequency
Input Capacitance1
600
16
12
27
14.318
36
CIN
Logic Inputs
5
pF
pF
CINX
X1 & X2 pins
45
Clk Stabilization1
Skew1
TSTAB
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V
5.5
4
ms
ns
tCPU-PCI1
1
28
1Guaranteed by design, not 100% tested in production.
3
ICS9248-185
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH2A
VOL2A
IOH2A
CONDITIONS
MIN
2.4
TYP
2.85
0.31
-45
MAX UNITS
V
IOH = -20 mA
IOL = 12 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-27
V
mA
mA
IOL2A
22
45
29
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.9
1
1.6
1.6
55
ns
ns
%
ps
ps
ps
Fall Time1
Duty Cycle1
Skew window1
tf2A
dt2A
50
tsk2A
VT = 1.5 V
35
175
150
250
Jitter, Cycle-to-cycle1
Jitter, Cycle-to-cycle1
tjcyc-cyc2A VT = 1.5 V Dram not running, CPU=66.6MHz
tjcyc-cyc2A VT = 1.5 V Dram running
123
119
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL= 2.5V, +/-5%; CL = 20 pF
PARAMETER
SYMBOL
VOH2A
VOL2A
IOH2A
CONDITIONS
MIN
2
TYP
2.3
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -20 mA
IOL = 12 mA
VOH = 2.0 V
VOL = 0.8 V
0.31
-39
26
0.4
-21
V
mA
mA
IOL2A
22
45
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
tr2A
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.96
1.06
50.3
35
1.6
1.6
55
ns
ns
%
ps
ps
ps
tf2A
dt2A
tsk2A
VT = 1.25 V
175
150
250
Jitter, Cycle-to-cycle1
Jitter, Cycle-to-cycle1
tjcyc-cyc2A VT = 1.25 V Dram not running
tjcyc-cyc2A VT = 1.25 V Dram running
123
119
1Guaranteed by design, not 100% tested in production.
4
ICS9248-185
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V , VDDL = 2.5V, +/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3
MAX UNITS
V
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.2
-62
43
0.4
-33
V
IOH1
mA
mA
IOL1
38
45
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.51
1.47
50.1
2
2
ns
ns
%
Fall Time1
Duty Cycle1
dt1
55
Skew window1
tsk1
tcycle
VT = 1.5 V
VT = 1.5 V
58
500
500
ps
ps
Jitter, Cycle to cycle
145
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V, VDDL= 2.50V, +/-5%; CL = 30 pF
PARAMETER
SYMBOL
VOH3
CONDITIONS
MIN
2.4
TYP
3
MAX UNITS
V
IOH = -28 mA
IOL = 19 mA
VOH = 2.0 V
VOL = 0.8 V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
VOL3
0.3
-69
42
0.4
-46
V
mA
mA
ns
IOH3
IOL3
32
45
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
Tr3
Tf3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.07
1.3
2
1.3
50.8
104
ns
Dt3
Tsk3
55
250
%
ps
VT = 1.5 V
Propagation Time1
(Buffer In to output)
Tsk3
VT = 1.5 V
5
ns
1Guaranteed by design, not 100% tested in production.
5
ICS9248-185
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V, VDDL= 2.5V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
2.6
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -14 mA
IOL = 6 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.22
-32
22
0.4
-20
V
IOH5
mA
mA
IOL5
16
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2.11
2.14
52.1
848
4
4
ns
ns
%
ps
dt5
45
55
Jitter, cycle to cycle1
tjcycle5
VT = 1.5 V
-600
1000
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD = 3.3 V, VDDL= 2.5V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
2.6
MAX UNITS
V
IOH = -14 mA
IOL = 6 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.22
-32
22
0.4
-20
V
IOH5
mA
mA
IOL5
16
45
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.79
1.92
4
4
ns
ns
Fall Time1
Duty Cycle1
dt5
tjcycle
VT = 1.5 V
VT = 1.5 V
50.8
267
55
%
Jitter, cycle to cycle
500
ps
1Guaranteed by design, not 100% tested in production.
6
ICS9248-185
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP#issynchronizedbytheICS9248-185. TheminimumthattheCPUclockisenabled(CLK_STOP# highpulse)is100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CLK_STOP#
PCI_STOP# (High)
SDRAM
CPUCLK
CPUCLK _F
SDRAM_F
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-185.
3. All other clocks continue to run undisturbed.
7
ICS9248-185
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-185. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-185 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCI_STOP#
PCICLK [6:0]
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
8
ICS9248-185
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
9
ICS9248-185
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
0.05
1.65
0.22
0.09
MAX
2.00
--
MIN
--
.002
.065
.009
.0035
MAX
.079
--
A
A1
A2
b
E1
E
INDEX
AREA
1.85
0.38
0.25
.073
.015
.010
c
D
SEE VARIATIONS
SEE VARIATIONS
E
E1
e
7.40
5.00
8.20
5.60
.291
.197
.323
.220
1
2
α
0.65 BASIC
0.0256 BASIC
D
L
0.55
0.95
.022
.037
A
A2
N
SEE VARIATIONS
SEE VARIATIONS
α
0°
8°
0°
8°
A1
- CC --
VARIATIONS
D mm.
D (inch)
e
SEATING
PLANE
N
b
MIN
9.90
MAX
10.50
MIN
.390
MAX
28
.413
.10 (.004) C
Reference Doc.: JEDEC Publication 95, MO-150
10-0033
209 mil SSOP
Ordering Information
9248yF-185LFT
Example:
XXXX y F - PPP LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
10
information being relied upon by the customer is current and accurate.
ICS9248-185
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
MAX
.047
.006
.041
.012
.008
A
A1
A2
b
E1
E
0.05
0.80
0.19
0.09
.002
.032
.007
.0035
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
2
α
E1
e
4.30
4.50
.169
0.0256 BASIC
.177
D
0.65 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
A1
VARIATIONS
- CC -
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
b
28
aaa
C
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
4.40 mm. Body, 0.65 mm. pitch TSSOP
(0.0256 Inch)
(173 mil)
Ordering Information
9248yG-185LFT
Example:
XXXX y G - PPP LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
11
information being relied upon by the customer is current and accurate.
ICS9248-185
Revision History
Rev.
D
Issue Date Description
10/ꢀ/2008 Added LF Ordering Information.
Page #
10-11
E
12/15/2008 Removed ICS prefix from ordering information.
10-11
12
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