ICS525-02RLFT [IDT]
Clock Generator, 160MHz, CMOS, PDSO28, 0.150 INCH, SSOP-28;
| 型号： | ICS525-02RLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 160MHz, CMOS, PDSO28, 0.150 INCH, SSOP-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总8页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS525-01/02
OSCaR™ User Configurable Clock
Description
Features
The ICS525-01 and ICS525-02 OSCaR™ are
the most flexible way to generate a high quality,
high accuracy, high frequency clock output from
an inexpensive crystal or clock input. The name
OSCaR stands for OSCillator Replacement, as
they are designed to replace crystal oscillators in
almost any electronic system. The user can easily
configure the device to produce nearly any
output frequency from any input frequency by
grounding or floating the select pins. Neither
microcontroller nor software nor device
• Packaged as 28 pin SSOP (150 mil body)
• Highly accurate frequency generation
• ICS525-01 with output frequencies up to 160 MHz
• ICS525-02 with output frequencies up to 200 MHz
• User determines the output frequency by
setting all internal dividers
• Eliminates need for custom oscillators
• No software needed
programmer are needed to set the frequency.
Using Phase-Locked-Loop (PLL) techniques, the
device accepts a standard fundamental mode,
inexpensive crystal to produce output clocks up
to 200 MHz. It can also produce a highly
accurate output clock from a given input clock,
keeping them frequency locked together.
• Pull-ups on all select inputs
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 2 - 50 MHz
• Very low jitter
• Duty cycle of 45/55 up to 200 MHz
• Operating voltages of 3.0 to 5.5V
• 25mA drive capability at TTL levels
• Ideal for oscillator replacement
• Industrial temperature versions available
• Advanced, low power CMOS process
For similar capability with a serial interface, use
the ICS307. For simple multipliers to produce
common frequencies, refer to the LOCO family
of parts, which are smaller and more cost
effective.
Block Diagram
VDD
2
GND
S2:S0
2
3
Phase Comparator,
Charge Pump,
and Loop Filter
Reference
Divider
Output
Divider
VCO
PD
Output
Buffer
VCO
Divider
Crystal or
clock input
X1/ICLK
CLK
REF
Crystal
Oscillator
Output
Buffer
9
7
X2
R6:R0
V8:V0
optional
MDS525G
1
Revision10209
Printed 11/12/99
Integrated Circuit Systems, Inc. • 525 Race Street •San Jose• CA • 95126•(408) 295-9800tel• www.icst.com
ICS525-01/02
OSCaR™ User Configurable Clock
R5
R6
R4
R3
R2
R1
R0
R5
R6
R4
1
2
3
4
5
6
7
8
28
27
26
25
24
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
22
Pin Assignments
R3
S0
R2
S0
S1
S2
S1
R1
S2
R0
VDD
X1/ICLK
X2
23 VDD
22 REF
21 CLK
20 GND
VDD
X1/ICLK
VDD
REF
X2
21 CLK
20 GND
19 PD
9
GND
V0
GND
V0
19
10
11
12
13
PDTS
V1
V2
V3
18 V8
17 V7
16 V6
V8
V1 11
V2 12
V3 13
V4 14
18
17
V7
16 V6
15 V5
15
V4 14
V5
ICS525-01
ICS525-02
ICS525-01 Pin Descriptions
Pin #
Name
Type Description
1, 2, 24-28 R5, R6, R0-R4 I(PU) Reference divider word input pins determined by user. Forms a binary number from 0 to 127.
3, 4, 5
6, 23
7
S0, S1, S2
VDD
X1/ICLK
X2
I(PU) Select pins for output divider determined by user. See table above.
Connect to VDD.
P
X1 Crystal connection. Connect to a parallel resonant crystal, or input clock.
X2 Crystal connection. Connect to a crystal, or leave unconnected for clock.
8
9, 20
10-18
19
GND
V0-V8
PD
P
Connect to ground.
I(PU) VCO divider word input pins determined by user. Forms a binary number from 0 to 511.
I(PU) Power Down. Active low. Turns off entire chip when low. Clock outputs stop low.
21
CLK
O
O
Output Clock determined by status of R0-R6, V0-V8, S0-S2 and input frequency.
Reference output. Buffered crystal oscillator (or clock) output.
22
REF
ICS525-02 Pin Descriptions
Pin #
Name
Type Description
1, 2, 24-28 R5, R6, R0-R4 I(PU) Reference divider word input pins determined by user. Forms a binary number from 0 to 127.
3, 4, 5
6, 23
7
S0, S1, S2
VDD
I(PU) Select pins for output divider determined by user. See table above.
Connect to VDD.
P
X1/ICLK
X2
X1 Crystal connection. Connect to a parallel resonant crystal, or input clock.
X2 Crystal connection. Connect to a crystal, or leave unconnected for clock.
8
9, 20
10-18
19
GND
P
Connect to ground.
V0-V8
PDTS
CLK
I(PU) VCO divider word input pins determined by user. Forms a binary number from 0 to 511.
I(PU) Power Down and Tri-state. Active low. Turns off entire chip and tri-states the outputs when low.
21
O
O
Output Clock determined by status of R0-R6, V0-V8, S0-S2 and input frequency.
Reference output. Buffered crystal oscillator (or clock) output.
22
REF
Key: I(PU) = Input with internal pull-up resistor; X1, X2 = Crystal connections; O = Output;
P = Power supply connection
MDS525G
2
Revision10209
Printed 11/12/99
Integrated Circuit Systems, Inc. • 525 Race Street •San Jose• CA • 95126•(408) 295-9800tel• www.icst.com
ICS525-01/02
OSCaR™ User Configurable Clock
ICS525-01 Output Divider and Maximum Output Frequency Table
Max. Output Frequency (MHz)
S2
S1
S0
CLK
pin 5 pin 4 pin 3 Output Divider
VDD = 5V
VDD = 3.3V
0-70 -40 to +85 0-70 -40 to +85
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
2
26
160
40
23
140
36
72
45
36
30
47
18
100
25
50
34
26
20
27
16
90
22
45
30
23
18
24
8
4
80
5
50
7
40
9
33.3
53
6
ICS525-02 Output Divider and Maximum Output Frequency Table
Max. Output Frequency (MHz)
S2
S1
S0
CLK
pin 5 pin 4 pin 3 Output Divider
VDD = 5V
VDD = 3.3V
0-70 -40 to 85 0-70 -40 to85
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6
2
8
4
5
7
1
3
All Above TBD
External Components / Crystal Selection
The ICS525 requires two 0.01µF decoupling capacitors to be connected between VDD and GND, one on
each side of the chip. They must be connected close to the ICS525 to minimize lead inductance. No
external power supply filtering is required for this device. A 33Wterminating resistor can be used next to
the CLK and REF pins. The approximate total on-chip capacitance for a crystal is shown in the table
below, so a parallel resonant, fundamental mode crystal with this value of load (correlation) capacitance
should be used. For example, using the ICS525-01 with crystals having a specified load capacitance greater
than 16 pF, crystal capacitors may be connected from each of the pins X1 and X2 to Ground as shown in
the Block Diagram on page 1. The value (in pF) of these crystal caps should be = (C -16)*2, where C is
L
L
the crystal load capacitance in pF. These external capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to X1 and leave X2 unconnected (no capacitors on
either).
Approximate On-Chip Capacitance
Device
ICS525-01
ICS525-02
Capacitance
16pF
TBD
MDS525G
3
Revision10209
Printed 11/12/99
Integrated Circuit Systems, Inc. • 525 Race Street •San Jose• CA • 95126•(408) 295-9800tel• www.icst.com
ICS525-01/02
OSCaR™ User Configurable Clock
Determining (setting) the output frequency
The user has full control in setting the desired output frequency over the range shown in the table on
page 2. To replace a standard oscillator, a user should connect the divider select input pins directly to
ground (or VDD, although this is not required because of internal pull-ups) during Printed Circuit Board
layout, so that the ICS525 automatically produces the correct clock when all components are soldered. It is
also possible to connect the inputs to parallel I/O ports to switch frequencies. By choosing divides
carefully, the number of inputs which need to be changed can be minimized. Observe the restrictions
stated below on allowed values of VDW and RDW.
ICS525-01 Settings
The output of the ICS525-01 can be determined by the following simple equation:
(VDW+8)
CLK frequency = Input frequency • 2 •
(RDW+2)(OD)
Where
Reference Divider Word (RDW) = 1 to 127 (0 is not permitted)
VCO Divider Word (VDW) = 4 to 511 (0, 1, 2, 3 are not permitted)
Output Divider (OD) = values on page 3
Also, the following operating ranges should be observed:
See Table on Page 3
(VDW+8)
10 MHz < Input frequency • 2 •
(RDW+2)
< 320 MHz at 5.0V or
< 200 MHz at 3.3V
for full details of
[ ]
maximum output.
Input Frequency
200 kHz <
(RDW+2)
ICS525-02 Settings
The output of the ICS525-02 can be determined by the following simple equation:
(VDW+8)
CLK frequency = Input frequency • 2 •
(RDW+2)(OD)
Where
Reference Divider Word (RDW) = 0 to 127
VCO Divider Word (VDW) = 0 to 511
Output Divider (OD) = values on page 3
Also, the following operating ranges should be observed:
See Table on Page 3
for full details of
maximum output.
(VDW+8) < TBD MHz at 5.0V or
(RDW+2) < TBD MHz at 3.3V
10 MHz < Input frequency • 2 •
[ ]
Input Frequency
200 kHz <
(RDW+2)
MDS525G
4
Revision10209
Printed 11/12/99
Integrated Circuit Systems, Inc. • 525 Race Street •San Jose• CA • 95126•(408) 295-9800tel• www.icst.com
ICS525-01/02
OSCaR™ User Configurable Clock
The dividers are expressed as integers, so that if a 66.66 MHz output is desired from a 14.31818 input, the
Reference Divider Word (RDW) should be 59, and the VCO Divider Word (VDW) should be 276, with
an Output divider (OD) of 2. In this example, R6:R0 is 0111011, V8:V0 is 100010100, and S2:S0 is 001.
Since all of these inputs have pull-up resistors, it is only necessary to ground the zero pins, namely V7, V6,
V5, V3, V1, V0, R6, R2, S2, and S1.
To determine the best combination of VCO, reference, and output divider, use the ICS525 Calculator on
our Web site: http://www.icst.com/wwwcad/ics525inputForm.html. This online form is easy to use and
quickly shows you up to three options for these settings.
You may also fax this page to MicroClock/ICS at 408 295 9818(fax), or send an e-mail to
sales@microclock.com. Be sure to indicate the following:
Your Name ________________ Company Name___________________ Telephone_________________
Respond by e-mail (list your e-mail address) __________________or fax number ___________________
Desired input crystal/clock (in MHz) _______________ Desired output frequency________________
VDD = 3.3V or 5V ___________
Duty Cycle: 40-60% _______ or 45-55% required________
MDS525G
5
Revision10209
Printed 11/12/99
Integrated Circuit Systems, Inc. • 525 Race Street •San Jose• CA • 95126•(408) 295-9800tel• www.icst.com
ICS525-01/02
OSCaR™ User Configurable Clock
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
ICS525-0xR
7
VDD+0.5
VDD+0.5
70
V
V
-0.5
-0.5
0
Clock Output
V
Ambient Operating Temperature
°C
°C
°C
°C
ICS525-0xRI
-40
85
Soldering Temperature
Storage Temperature
Max of 10 seconds
260
-65
150
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
3
2
5.5
0.8
V
V
Input High Voltage, VIH
Input Low Voltage, VIL
V
Input High Voltage, VIH, X1/ICLK only
Input Low Voltage, VIL, X1/ICLK only
Output High Voltage, VOH, CMOS level
Output High Voltage, VOH
ICLK (Pin 7)
(VDD/2)+1
VDD/2
VDD/2
V
ICLK (Pin 7)
(VDD/2)-1
V
IOH = -4mA
VDD-0.4
2.4
V
IOH=-25mA
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
IDD Operating Supply Current, 15 MHz crystal
IDD Operating Supply Current, 15 MHz crystal
IDD Operating Supply Current, Power Down
IDD Operating Supply Current, Power Down
Short Circuit Current
No Load, 60MHz out
60MHz out, VDD=3.3V
Pin 19=0
15
8
mA
mA
µA
µA
mA
kW
pF
20
7
Pin 19=0, VDD=3.3V
CLK and REF outputs
All V, R, S pins and pin 19
All V, R, S pins and pin 19
±70
270
4
On-Chip Pull-up Resistor
Input Capacitance
MDS525G
6
Revision10209
Printed 11/12/99
Integrated Circuit Systems, Inc. • 525 Race Street •San Jose• CA • 95126•(408) 295-9800tel• www.icst.com
ICS525-01/02
OSCaR™ User Configurable Clock
Electrical Specifications (cont.)
Parameter
Conditions
Minimum
Typical
Maximum Units
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, crystal input
5
2
1
1
1
1
1
1
1
1
27
50
MH z
MH z
MH z
MH z
MH z
MH z
MH z
MH z
MH z
MH z
ns
Input Frequency, clock input
Output Frequency, VDD = 4.5 to 5.5V
ICS525-01, note 1
0 °C to 70 °C
-40 °C to +85 °C
0 °C to 70 °C
-40 °C to +85 °C
0 °C to 70 °C
-40 °C to +85 °C
0 °C to 70 °C
-40 °C to +85 °C
0.8 to 2.0V
160
140
100
90
Output Frequency, VDD = 3.0 to 3.6V
ICS525-01, note 1
Output Frequency, VDD = 4.5 to 5.5V
ICS525-02, note 1
TBD
TBD
TBD
TBD
Output Frequency, VDD = 3.0 to 3.6V
ICS525-02, note 1
Output Clock Rise Time
1
1
Output Clock Fall Time
2.0 to 0.8V
ns
Output Clock Duty Cycle, OD = 2, 4, 6, 8, or 10
Output Clock Duty Cycle, OD = 3, 5, 7, or 9
Output Clock Duty Cycle, OD = 1 (-02 only)
Power Down Time, PD low to clocks stopped low
Power Up Time, PD high to clocks stable
Absolute Clock Period Jitter
at VDD/2
45
40
49 to 51
55
60
%
at VDD/2
%
at VDD/2
TBD
TBD
50
ns
ms
ps
10
Deviation from mean
±90
40
One Sigma Clock Period Jitter
ps
Note 1: There is no constant phase relationship between the input and output clocks. If a fixed phase
relationship is required, use the ICS527 Clock Slicer.
MDS525G
7
Revision10209
Printed 11/12/99
Integrated Circuit Systems, Inc. • 525 Race Street •San Jose• CA • 95126•(408) 295-9800tel• www.icst.com
ICS525-01/02
OSCaR™ User Configurable Clock
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
28 pin SSOP
Inches
Symbol Min
Millimeters
Max
Min
1.35
0.10
0.20
0.19
9.80
3.81
Max
A
A1
B
C
D
E
0.053 0.069
0.004 0.010
0.008 0.012
0.007 0.010
0.386 0.394
0.150 0.157
.025 BSC
1.75
0.25
0.30
0.25
10.01
3.99
E
H
e
0.635 BSC
H
L
0.228 0.244
0.016 0.050
5.79
0.41
6.20
1.27
D
A
A1
C
B
e
L
Ordering Information
Part/Order Number
ICS525-01R
Marking
525-01R
525-01R
525-01RI
525-01RI
ICS525R-02
ICS525R-02
ICS525R-02I
ICS525R-02I
Package
Temperature
0 to 70 °C
0 to 70 °C
28 pin narrow SSOP
28 pin SSOP on tape and reel
28 pin narrow SSOP
ICS525-01RT
ICS525-01RI
ICS525-01RIT
ICS525-02R
ICS525-02RT
ICS525-02RI
ICS525-02RIT
-40 to +85 °C
28 pin SSOP on tape and reel -40 to +85 °C
28 pin narrow SSOP
28 pin SSOP on tape and reel
28 pin narrow SSOP
0 to 70 °C
0 to 70 °C
-40 to +85 °C
28 pin SSOP on tape and reel -40 to +85 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc. (ICS) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any
ICS product for use in life support devices or critical medical instruments.
OSCaR is a trademark of Integrated Circuit Systems
MDS525G
8
Revision10209
Printed 11/12/99
Integrated Circuit Systems, Inc. • 525 Race Street •San Jose• CA • 95126•(408) 295-9800tel• www.icst.com
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