ICS650R-01LFT [IDT]
Processor Specific Clock Generator, 80MHz, CMOS, PDSO20, 0.150 INCH, LEAD FREE, SSOP-20;
| 型号： | ICS650R-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 80MHz, CMOS, PDSO20, 0.150 INCH, LEAD FREE, SSOP-20 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总8页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
SYSTEM PERIPHERAL CLOCK SOURCE
ICS650-01
Description
Features
The ICS650-01 is a low-cost, low-jitter, high-performance
clock synthesizer for system peripheral applications. Using
analog/digital Phase-Locked Loop (PLL) techniques, the
device accepts a parallel resonant 14.31818 MHz crystal
input to produce up to eight output clocks. The device
provides clocks for PCI, SCSI, Fast Ethernet, Ethernet,
USB, and AC97. The user can select one of three USB
frequencies and also one of two AC97 audio frequencies.
The OE pin puts all outputs into a high impedance state for
board level testing. All frequencies are generated with less
than one ppm error, meeting the demands of SCSI and
Ethernet clocking.
• Packaged in 20-pin SSOP (QSOP)
• Pb (lead) free package
• Operating voltage of 3.3 V or 5 V
• Less than one ppm synthesis error in all clocks
• Inexpensive 14.31818 MHz crystal or clock input
• Provides Ethernet and Fast Ethernet clocks
• Provides SCSI clocks
• Provides PCI clocks
• Selectable AC97 audio clock
• Selectable USB clock
• OE pin tri-states the outputs for testing
• Selectable frequencies on three clocks
• Duty cycle of 40/60
• Advanced, low-power CMOS process
• Industrial temperature range available
Block Diagram
VDD
3
2
4
Processor
Clocks
PSEL1:0
ASEL
Audio Clock
Clock
Synthesis
Circuitry
USEL
USB Clock
20 MHz
14.31818 MHz
Crystal or Clock
X1/ICLK
Crystal
Oscillator
14.31818 MHz
X2
2
OE (all outputs)
GND
IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE
1
ICS650-01
REV H 051310
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE
CLOCK SYNTHESIZER
Pin Assignment
Processor Clock (MHz)
1
2
20
19
18
17
16
15
14
13
12
11
PSEL1
PSEL0
PCLK2
PCLK3
VDD
PSEL1 PSEL0
PCLK1
25
PCLK2, 3
PCLK4
18.75
TEST
TEST
20
USEL
X2
0
0
0
M
1
50
TEST
TEST
80
3
X1/ICLK
VDD
TEST
TEST
40
4
0
VDD
GND
5
M
M
M
1
0
6
ASEL
GND
M
1
33.3334
20
66.6667
40
25
UCLK
7
25
20M
ACLK
8
14.318M
PCLK1
OE
0
20
33.3334
66.6667
25
9
1
M
1
20
25
PCLK4
10
1
Stops low all clocks except 20M
20 pin (150 mil) SSOP
Audio Clock (MHz)
USB Clock (MHz)
ASEL
ACLK
49.152
24.576
12.288
0
M
1
USEL
UCLK
12
0
M
1
24
48
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
USEL
X2
Input
XO
UCLK select pin. Determines frequency of USB clock per table above.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal.
Leave open for clock.
3
X1/ICLK
XI
Crystal connection. Connect to parallel mode 14.31818 MHz crystal or
clock.
4
5
6
7
8
VDD
VDD
GND
UCLK
20M
Power Connect to VDD. Must be same value as other VDD. Decouple with pin 6.
Power Connect to VDD. Must be same value as other VDD.
Power Connect to ground.
Output USB clock output per table above.
Output Fixed 20 MHz output for Ethernet. Only clock that runs when
PSEL1=PSEL0=1.
9
ACLK
Output AC97 audio clock output per table above.
Output PCLK output number 4 per table above.
10
PCLK4
IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE
2
ICS650-01
REV H 051310
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE
CLOCK SYNTHESIZER
Pin
Number
Pin
Name
Pin
Type
Pin Description
11
12
13
14
15
16
17
18
19
OE
PCLK1
14.318M
GND
Input
Output enable. Tri-states all outputs when low.
Output PCLK output number 1 per table above.
Output 14.31818 MHz Buffered reference clock output.
Power Connect to ground.
ASEL
Input
ACLK select pin. Determines frequency of Audio clock per table above.
VDD
Power Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
Output PCLK output number 3 per table above.
PCLK3
PCLK2
PSEL0
Output PCLK output number 2 per table above.
Input
Processor select pin #0. Determines frequencies on PCLKs 1-4 per table
above.
20
PSEL1
Input
Processor select pin #1. Determines frequencies on PCLKs 1-4 per table
above.
External Components
The ICS650-01 requires a minimum number of external
components for proper operation.
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
Decoupling Capacitor
Crystal Information
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND (pins 4 and 6, pins 16 and 14),
as close to the device as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant, 300 ppm or better (to
meet Ethernet specs). Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
Crystal caps (pF) = (C - 12) x 2
L
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ωresistor in series with the clock line,
In the equation, C is the crystal load capacitance. So, for a
L
crystal with a 16 pF load capacitance, two 8 pF capacitors
should be used. If a clock input is used, drive it into X1 and
leave X2 unconnected.
IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE
3
ICS650-01
REV H 051310
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
° C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.0
+3.3
+5.5
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±% (or ± V unless noted), Ambient Temperature 0 to +70°C
Parameter
Symbol
VDD
Conditions
Min.
Typ.
Max. Units
Operating Voltage
3.0
5.5
V
Supply Current
Supply Current
IDD
At 5 V, No load, Note 1
50
30
mA
mA
IDD
At 3.3 V, No load,
Note 1
Input High Voltage
Input Low Voltage
Output High Voltage
V
Select inputs, OE
Select inputs, OE
VDD = 3.3 V,
2
V
V
V
IH
V
0.8
0.4
IL
V
2.4
OH
I
= -8 mA
OH
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance
V
VDD = 3.3 V or 5 V,
= -8 mA
VDD-0.4
V
V
OH
I
OH
V
VDD = 3.3 V,
= 8mA
OL
I
OL
I
VDD = 3.3 V,
each output
50
7
mA
pF
OS
Except X1
Note 1: With all clocks at highest frequencies.
IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE
4
ICS650-01
REV H 051310
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE
CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±±% (or ± V unless noted), Ambient Temperature 0 to +70° C
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Input Frequency
14.31818
MHz
Output Clocks Accuracy
(synthesis error)
All clocks
1
ppm
Output Rise Time
Output Fall Time
t
0.8 to 2.0 V, Note 1
2.0 to 0.8 V, Note 1
At VDD/2
1.5
1.5
50
ns
ns
%
OR
t
OF
Output Clock Duty Cycle
One Sigma Jitter
40
60
except ACLK
ACLK
75
ps
ps
ps
170
Absolute Clock Period Jitter
PCLK, UCLK, 20M
-500
500
Note 1: Measured with 15 pF load
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
135
93
° C/W
° C/W
° C/W
° C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
78
Thermal Resistance Junction to Case
60
Marking Diagram—ICS6±0R-01LF
Marking Diagram—ICS6±0R-01ILF
20
11
20
11
650R-01LF
######
YYWW
650R-01ILF
######
YYWW
10
10
1
1
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “LF” denotes Pb (lead) free package.
4. “I” denotes industrial grade device.
5. Bottom marking: (origin) = country of origin if not USA.
IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE
5
ICS650-01
REV H 051310
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE
CLOCK SYNTHESIZER
Package Outline and Package Dimensions (20-pin SSOP, 1±0 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
20
Millimeters
Inches
Symbol
Min
1.35
0.10
--
Max
1.75
0.25
1.50
0.30
0.25
8.75
6.20
4.00
Min
Max
A
A1
A2
b
0.053
0.004
--
0.008
0.007
0.337
0.228
0.150
0.069
0.010
0.059
0.012
0.010
0.344
0.244
0.157
E1
E
INDEX
AREA
0.20
0.18
8.55
5.80
3.80
c
D
E
1
2
E1
e
D
.635 Basic
.025 Basic
L
0.40
1.27
0.016
0.050
α
0°
8°
0°
8°
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
Ordering Information
Part / Order Number
650R-01LF
Marking
see page 6
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
-40 to 85° C
-40 to 85° C
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
650R-01LFT
Tape and Reel
Tubes
650R-01ILF
650R-01ILFT
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE
6
ICS650-01
REV H 051310
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE
CLOCK SYNTHESIZER
IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE
7
ICS650-01
REV H 051310
ICS650-01
SYSTEM PERIPHERAL CLOCK SOURCE
CLOCK SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
ICS650R-07LFT
Processor Specific Clock Generator, 133.33MHz, CMOS, PDSO20, 0.150 INCH, ROHS COMPLIANT, SSOP-20
IDT
©2020 ICPDF网 联系我们和版权申明