ICS650R-12LF [IDT]

Video Clock Generator, 108MHz, PDSO20, SSOP-20;
ICS650R-12LF
型号: ICS650R-12LF
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Video Clock Generator, 108MHz, PDSO20, SSOP-20

时钟 光电二极管 外围集成电路 晶体
文件: 总7页 (文件大小:132K)
中文:  中文翻译
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DATASHEET  
MPEG CLOCK SYNTHESIZER  
ICS650-12  
Description  
Features  
The ICS650-12 is a low cost, low-jitter, high-performance  
clock synthesizer designed to produce fixed clock outputs of  
13.5 MHz and 27.0 MHz, and four selectable clock outputs:  
two Processor Clocks (PCLK1) and PCLK2), an Audio  
Clock, and a Communications Clock (CCLK). Using analog  
Phase-Locked Loop (PLL) techniques, the device uses a  
27.0 MHz clock or fundamental crystal to produce clocks  
ideal for Digital Video/MPEG-based applications.  
Packaged in 20-pin tiny SSOP (QSOP)  
RoHS 5 (green) or RoHS 6 (green and lead free)  
compliant package  
Input frequency of 27.0 MHz  
Zero ppm synthesis error in output clocks  
Provides fixed 13.5 MHz and 27.0 MHz. Also provides  
two selectable processor clocks, one audio clock, and  
one communications clock.  
Ideal for digital video MPEG-based applications  
3.3 V or 5.0 V operating voltage  
Entire chip powers down (when CS1=CS0=0)  
Block Diagram  
PS2:0  
PCLK1  
PCLK2  
Clock  
AS2:0  
CS1:0  
Synthesis  
ACLK  
and Control  
Circuitry  
CCLK  
13.5 MHz  
/2  
Input  
Buffer/  
27.0 MHz crystal  
Crystal  
27.0 MHz  
or clock  
Oscillator  
IDT™ / ICS™ MPEG CLOCK SYNTHESIZER  
1
ICS650-12  
REV E 051310  
ICS650-12  
MPEG CLOCK SYNTHESIZER  
CLOCK SYNTHESIZER  
ACLK Select Table (in MHz)  
Pin Assignment  
AS2  
AS1 AS0 ACLK  
PS2  
X2  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
PS1  
PS0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
12.288  
11.2896  
8.192  
X1  
CCLK  
PCLK2  
VDD  
AS1  
VDD  
CS1  
24.576  
8.192  
GND  
ACLK  
PCLK1  
CS0  
GND  
13.5M  
27M  
16.9344  
18.432  
11.2896  
AS2  
AS0  
20-pin SSOP (QSOP)  
CCLK Select Table (in MHz)  
CS1 CS0 CCLK  
PCLK1 and PCLK2 Select Table (in MHz)  
PS2 PS1 PS0 PCLK1 PCLK2  
0
0
1
1
0
1
0
1
All off*  
20.00  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
108.00  
55.00  
66.67  
80.00  
54.00  
81.00  
50.00  
60.00  
54.00  
27.5  
66.6666  
24.576  
33.33  
40.00  
27.00  
40.5  
*Note: Entire chip powers-down (outputs stop low) when  
CS1=CS0=0.  
25.00  
30.00  
IDT™ / ICS™ MPEG CLOCK SYNTHESIZER  
2
ICS650-12  
REV E 051310  
ICS650-12  
MPEG CLOCK SYNTHESIZER  
CLOCK SYNTHESIZER  
Pin Descriptions  
Pin  
Pin  
Pin  
Pin Description  
Number Name Type  
1
2
PS2  
X2  
Input Processor Clock Select pin 2. See table on page 2.  
XO  
XI  
Crystal connection. Connect to a 27.0 MHz crystal or leave unconnected for a clock input.  
Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input.  
3
X1  
4, 16  
5
VDD  
CS1  
GND  
Power Connect to +3.3 V or +5 V.  
Input Communications Clock Select Pin 1. See table on page 2.  
Power Connect to ground.  
6, 14  
7
ACLK Output Audio Clock Output. See table on page 2.  
8
PCLK1 Output Processor Clock Output 1. See table on page 2.  
9
CS0  
AS2  
AS0  
27M  
Input Communications Clock Select 0. See table on page 2.  
Input Audio Clock Select Pin 2. See table on page 2.  
Input Audio Clock Select Pin 0. See table on page 2.  
Output 27 MHz buffered clock output.  
10  
11  
12  
13  
15  
17  
18  
19  
20  
13.5M Output 13.5 MHz clock output.  
AS1 Input Audio Clock Select Pin 1. See table on page 2.  
PCLK2 Output Processor Clock Output 2. See table on page 2.  
CCLK Output Communications Clock Output. See table on page 2.  
PS0  
PS1  
Input Processor Clock Select Pin 0. See table on page 2.  
Input Processor Clock Select Pin 1. See table on page 2.  
Key: Input = input with internal pull-up; XI and XO = crystal  
connections; Power = power supply connection; Output =  
output  
IDT™ / ICS™ MPEG CLOCK SYNTHESIZER  
3
ICS650-12  
REV E 051310  
ICS650-12  
MPEG CLOCK SYNTHESIZER  
CLOCK SYNTHESIZER  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the ICS650-12. These ratings, which are  
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these  
or any other conditions above those indicated in the operational sections of the specifications is not implied.  
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical  
parameters are guaranteed only over the recommended operating temperature range.  
Item  
Conditions  
Referenced to GND  
Referenced to GND  
Rating  
Supply Voltage, VDD  
7 V  
All Inputs and Outputs  
Ambient Operating Temperature  
Storage Temperature  
-0.5 V to VDD+0.5 V  
0 to +70°C  
-65 to +150°C  
260°C  
Soldering Temperature  
Max. of 10 seconds  
DC Electrical Characteristics  
Unless stated otherwise, VDD = 3.3 V or 5 V, Ambient Temperature 0 to +70°C  
Parameter  
Operating Voltage  
Symbol  
VDD  
VIH  
Conditions  
Min.  
3.0  
2
Typ.  
Max.  
Units  
5.5  
V
V
V
V
V
V
Input High Voltage  
Input Low Voltage  
Output High Voltage  
Output Low Voltage  
Output High Voltage  
VDD/2  
VDD/2  
VIL  
0.8  
0.8  
VOH  
VOL  
VDD = 3.3 V, IOH = -8 mA  
VDD = 3.3 V, IOL = 8 mA  
2.4  
VOH,VDD = 3.3 IOH = -8 mA  
or 5 V  
VDD-0.4  
Operating Supply Current  
Operating Supply Current  
Short Circuit Current  
Input Capacitance  
I
DD@5 V  
No Load  
No Load  
39  
22  
50  
7
mA  
mA  
mA  
pF  
IDD@5 V  
IOS, VDD = 3.3 V Each output  
Except X1  
IDT™ / ICS™ MPEG CLOCK SYNTHESIZER  
4
ICS650-12  
REV E 051310  
ICS650-12  
MPEG CLOCK SYNTHESIZER  
CLOCK SYNTHESIZER  
AC Electrical Characteristics  
Unless stated otherwise, VDD = 3.3 V or 5 V, Ambient Temperature 0 to +70°C  
Parameter  
Input Crystal or Clock Frequency  
Output Clocks Accuracy (synthesis error)  
Output Clock Rise Time  
Symbol  
Conditions  
Min. Typ. Max. Units  
27  
0
MHz  
ppm  
ns  
All clocks  
1
t
0.8 to 2.0 V  
2.0 to 0.8 V  
At VDD/2  
1.5  
1.5  
60  
OR  
Output Clock Fall Time  
t
ns  
OF  
Output Clock Duty Cycle  
40  
50  
100  
40  
%
One Sigma Jitter, ACLK  
VDD = 3.3 V  
VDD = 5.0 V  
ps  
ps  
Absolute Clock Period Jitter  
VDD = 3.3 V, except  
CCLK = 20 MHz  
300  
ps  
VDD = 5.0 V, except  
CCLK = 20 MHz  
200  
ps  
External Components  
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF  
should be connected between VDD and GND on pins 4 and 6, 16 and 14, and a 33terminating resistor may be  
used on each clock output if the trace is longer than 1 inch.  
IDT™ / ICS™ MPEG CLOCK SYNTHESIZER  
5
ICS650-12  
REV E 051310  
ICS650-12  
MPEG CLOCK SYNTHESIZER  
CLOCK SYNTHESIZER  
Package Outline and Package Dimensions (20-pin SSOP)  
Package dimensions are kept current with JEDEC Publication No. 95  
Millimeters  
Min Max  
Inches  
20  
Symbol  
Min  
Max  
A
A1  
b
1.35  
0.10  
0.20  
0.18  
8.55  
5.80  
3.80  
1.75  
0.25  
0.30  
0.25  
8.75  
6.20  
4.00  
0.053  
0.004  
0.008  
0.007  
0.337  
0.228  
0.150  
0.069  
0.010  
0.012  
0.010  
0.344  
0.244  
0.157  
E1  
E
INDEX  
AREA  
c
D
E
E1  
e
1 2  
0.635 Basic  
0.025 Basic  
L
α
0.40  
0°  
1.27  
8°  
0.016  
0°  
0.050  
8°  
D
A
A1  
c
- C -  
e
SEATING  
PLANE  
b
L
.10 (.004)  
C
Ordering Information  
Part / Order Number  
650R-12LF  
Marking  
650R-12LF  
650R-12LF  
Shipping Packaging  
Tubes  
Package  
20-pin SSOP  
20-pin SSOP  
Temperature  
0 to +70° C  
0 to +70° C  
650R-12LFT  
Tape and Reel  
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
IDT™ / ICS™ MPEG CLOCK SYNTHESIZER  
6
ICS650-12  
REV E 051310  
ICS650-12  
MPEG CLOCK SYNTHESIZER  
CLOCK SYNTHESIZER  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
800-345-7015  
408-284-8200  
Fax: 408-284-2775  
For Tech Support  
www.idt.com/go/clockhelp  
Corporate Headquarters  
Integrated Device Technology, Inc.  
www.idt.com  
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device  
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered  
trademarks used to identify products or services of their respective owners.  
Printed in USA  

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