ICS84021AYLF [IDT]
Clock Generator, 260MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32;
| 型号： | ICS84021AYLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 260MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32 时钟 外围集成电路 晶体 |
| 文件： | 总19页 (文件大小：737K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS84021
260MHz, Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer
DATA SHEET
General Description
Features
The ICS84021 is a general purpose, Crystal-to-LVCMOS/LVTTL
High Frequency Synthesizer. The ICS84021 has a selectable
TEST_CLK or crystal input. The VCO operates at a frequency range
of 620MHz to 780MHz. The VCO frequency is programmed in steps
equal to the value of the input reference or crystal frequency. The
VCO and output frequency can be programmed using the serial or
parallel interface to the configuration logic.
• Two LVCMOS/LVTTL outputs
• Selectable crystal oscillator interface or LVCMOS/LVTTL
TEST_CLK
• Output frequency range: 103.3MHz to 260MHz
• Crystal input frequency range: 14MHz to 40MHz
• VCO range: 620MHz to 780MHz
• Parallel or serial interface for programming counter and output
dividers
• RMS period jitter: 14.7ps (typical), (N ÷ 4, VDDO = 3.3V 5%)
• RMS phase jitter at 155.52MHz, using a 38.88MHz crystal (12kHz
to 20MHz): 2.61ps (typical)
Offset
Noise Power
100Hz.................-87.9 dBc/Hz
1kHz...................-115.8 dBc/Hz
10kHz.................-124.2 dBc/Hz
100kHz...............-127.7 dBc/Hz
• Full 3.3V or mixed 3.3V core/2.5V or 1.8V output supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
Pullup
OE0
Pullup
OE1
Pullup
VCO_SEL
32 31 30 29 28 27 26 25
Pullup
XTAL_SEL
1
2
3
4
5
6
7
8
M5
XTAL_OUT
24
23
22
21
20
Pulldown
TEST_CLK
0
M6
M7
TEST_CLK
XTAL_SEL
VDDA
XTAL_IN
1
OSC
M8
N0
XTAL_OUT
S_LOAD
N1
nc
S_DATA
S_CLOCK
MR
19
18
17
PLL
GND
Phase Detector
9
10 11 12 13 14 15 16
N
Pulldown
MR
÷3
÷4
÷5
÷6
0
1
VCO
Q0
Q1
÷M
ICS84021
32 Lead LQFP
7mm x 7mm x 1.4mm package body
Pulldown
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
Pulldown
Pulldown
Pulldown
TEST
Configuration Interface Logic
Y Package
Top View
M5 Pullup; M[0:4, 6:8] Pulldown
Pulldown
M[0:8]
N[0:1]
ICS84021BY REVISION E AUGUST 18, 2011
1
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 25MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The relationship between the VCO frequency, the crystal frequency
and the M divider is defined as follows: fVCO = fxtal x M
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 25MHz reference are
defined as 25 ≤ M ≤ 31. The frequency out is defined as follows:
The ICS84021 features a fully integrated PLL and therefore requires
no external components for setting the loop bandwidth. A
fundamental crystal is used as the input to the on-chip oscillator. The
output of the oscillator is fed into the phase detector. A 25MHz crystal
provides a 25MHz phase detector reference frequency. The VCO of
the PLL operates over a range of 620MHz to 780MHz. The output of
the M divider is also applied to the phase detector.
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVCMOS output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS84021 support two input
modes to program the M divider and N output divider. The two input
operational modes are parallel and serial. Figure 1 shows the timing
diagram for each mode. In parallel mode, the nP_LOAD input is
initially LOW. The data on inputs M0 through M8 and N0 and N1 is
passed directly to the M divider and N output divider. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M and N bits
can be hardwired to set the M divider and N output divider to a
specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode.
T1
0
T0
0
TEST Output
LOW
0
1
S_DATA, Shift Register Input
Output of M Divider
CMOS FOUT
1
0
1
1
SERIAL LOADING
S_CLOCK
T1 T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
S_DATA
S_LOAD
t
t
S
H
t
nP_LOAD
S
PARALLEL LOADING
M, N
M[0:8], N[0:1]
nP_LOAD
t
t
H
S
S_LOAD
Time
*NOTE: The NULL timing slot must be observed.
Figure 1. Parallel & Serial Load Operations
ICS84021BY REVISION E AUGUST 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
M5
Input
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD
input. LVCMOS/LVTTL interface levels.
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Pulldown
Pulldown
Determines N output divider value as defined in Table 3C, Function
Table. LVCMOS/LVTTL interface levels.
5, 6
N0, N1
Input
7
nc
Unused
Power
No connect.
8, 16
GND
Power supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
9
TEST
VDD
Output
Power
10
Core supply pin.
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are in an Hi-Z state. See Table 3E, OE
Function Table. LVCMOS/LVTTL interface levels.
11, 12
Input
Pullup
OE1, OE0
13
VDDO
Power
Output
Output supply pin.
14, 15
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Q1, Q0
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When Logic LOW, the internal
dividers and the outputs are enabled. Assertion of MR does not affect
loaded M, N, and T values. LVCMOS/LVTTL interface levels.
17
MR
Input
Pulldown
Clocks in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
18
19
S_CLOCK
S_DATA
Input
Input
Pulldown
Pulldown
Pulldown
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
20
21
S_LOAD
VDDA
Input
Power
Analog supply pin.
Selects between crystal or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS/LVTTL interface levels.
22
XTAL_SEL
Input
Pullup
23
TEST_CLK
Input
Input
Pulldown
Single-ended test clock input. LVCMOS/LVTTL interface levels.
24,
25
XTAL_OUT
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Parallel load input. Determines when data present at M[8:0] is loaded into
M divider, and when data present at N[1:0] sets the N output divider
value. LVCMOS/LVTTL interface levels.
26
27
nP_LOAD
VCO_SEL
Input
Input
Pulldown
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS84021BY REVISION E AUGUST 18, 2011
3
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
pF
pF
pF
kΩ
kΩ
Ω
CIN
Input Capacitance
4
V
DDO = 3.465V
VDDO = 2.625V
DDO = 1.89V
15
15
20
51
51
7
Power Dissipation Capacitance
(per output)
CPD
V
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
V
DDO = 3.3V 5%
ROUT
Output Impedance
VDDO = 2.5V 5%
VDDO = 1.8V 5%
7
Ω
10
Ω
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
MR
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA Conditions
H
X
X
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M divider and
N output divider. TEST output forced LOW.
L
L
L
L
L
↑
Data
Data
X
Data
Data
X
X
L
L
↑
Data is latched into input registers and remains loaded until
next LOW transition or until a serial event occurs.
X
↑
L
X
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
H
H
Data
Data
Contents of the shift register are passed to the M divider and
N output divider.
X
X
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don’t care
↑ = Rising edge transition
↓ = Falling edge transition
ICS84021BY REVISION E AUGUST 18, 2011
4
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
(NOTE 1)
Table 3B. Programmable VCO Frequency Function Table
256
M8
0
128
M7
0
64
32
M5
0
16
M4
1
8
M3
1
4
M2
0
2
M1
0
1
M0
1
VCO Frequency
(MHz)
M Divide
M6
0
625
•
25
•
•
•
•
•
•
•
•
•
•
700
•
28
•
0
0
0
0
1
1
1
0
0
•
•
•
•
•
•
•
•
•
775
31
0
0
0
0
1
1
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to TEST_CLK or crystal frequency of 25MHz.
Table 3C. Programmable Output Divider Function Table (PLL Enabled)
Inputs
Output Frequency (MHz)
N1
0
N0
0
N Divider Value
Minimum
206.7
155
Maximum
260
3
4
5
6
0
1
195
1
0
124
156
1
1
103.3
130
Table 3D. Commonly Used Configuration Function Table
Inputs
Output Frequency (MHz)
Crystal (MHz)
19.44
M Divider Value
N Divider Value
Minimum
155.52
156.25
156.25
125
32
32
25
25
25
25
25
16
4
4
4
5
3
4
6
4
19.53125
25
25
25.50
212.50
159.375
106.25
155.52
25.50
25.50
38.88
Table 3E. Output Enable & Clock Enable Function Table
Control Inputs Output
OE0
OE1
Q0
Hi-Z
Q1
Hi-Z
0
0
1
1
0
1
0
1
Hi-Z
Enabled
Hi-Z
Enabled
Enabled
Enabled
ICS84021BY REVISION E AUGUST 18, 2011
5
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
0V to VDD
Other Inputs
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
Package Thermal Impedance, θJA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO = 3.3V 5%, 2.5V 5% or 1.8V 5%, TA = 0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
VDD
Units
V
Core Supply Voltage
Analog Supply Voltage
VDDA
VDD – 0.36
3.135
3.3
V
3.3
3.465
2.625
1.89
110
V
VDDO
Output Supply Voltage
2.375
2.5
V
1.71
1.8
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
IDDO
24
5
ICS84021BY REVISION E AUGUST 18, 2011
6
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, VDDO = 3.3V 5%, 2.5V 5% or 1.8V 5%, TA = 0°C to 70°C
Symbol Parameter
VIH Input High Voltage
Test Conditions
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
OE[0:1], N[0:1], M[0:8],
XTAL_SEL, VCO_SEL,
S_DATA, S_CLOCK,
-0.3
-0.3
0.8
1.3
150
V
V
Input
Low Voltage
VIL
S_LOAD, nP_LOAD, MR
TEST_CLOCK
MR, S_CLOCK,
TEST_CLK, S_DATA,
S_LOAD, nP_LOAD,
M[0:4], M[6:8], N0, N1
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
µA
Input
High Current
IIH
M5, OE0, OE1,
XTAL_SEL, VCO_SEL
5
µA
µA
µA
MR, S_CLOCK,
TEST_CLK, S_DATA,
S_LOAD, nP_LOAD,
M[0:4], M[6:8], N0, N1
-5
Input
Low Current
IIL
M5, OE0, OE1,
XTAL_SEL, VCO_SEL
VDD = 3.465V, VIN = 0V
VDDO = 3.3V 5%
-150
2.6
1.8
V
V
V
V
V
VOH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 2.5V 5%
VDDO = 1.8V 5%
VDDO - 0.3
V
DDO = 3.3V 5% or 2.5V 5%
0.5
0.4
VOL
VDDO = 1.8V 5%
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagrams.
Table 5. Input Frequency Characteristics, VDD = 3.3V 5%, VDDO = 3.3V 5%, 2.5V 5% or 1.8V 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
MHz
MHz
MHz
TEST_CLK; NOTE 1
XTAL; NOTE 1
S_CLOCK
14
14
40
40
50
fIN
Input Frequency
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 620MHz to 780MHz
range. Using the minimum input frequency of 14MHz, valid values of M are 45 ≤ M ≤ 55. Using the maximum input frequency of 40MHz, valid
values of M are 16 ≤ M ≤ 19.
Table 6. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Frequency
Fundamental
14
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
pF
ICS84021BY REVISION E AUGUST 18, 2011
7
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
AC Electrical Characteristics
Table 7A. AC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
260
Units
MHz
ps
fOUT
Output Frequency
103.3
N = 3
N = 4
N = 5
N = 6
13.5
14.7
16.7
24.7
26.4
34.2
ps
42.4
ps
40.8
ps
tjit(per)
Period Jitter, RMS; NOTE 1, 2
M=40, N=4, 16.667MHz XTAL,
fOUT=166.67MHz
4.5
4.6
6.9
7.8
ps
ps
M=40, N=5, 16.667MHz XTAL,
fOUT=133.33MHz
tsk(o)
Output Skew; NOTE 2, 3
Output Rise/Fall Time
M, N to nP_LOAD
100
800
ps
ps
ns
ns
ns
ns
ns
ns
%
tR / tF
20% to 80%
100
5
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
N ≠ 3
44
56
55
M=40, N=4, 16.667MHz XTAL,
45
47
%
odc
Output Duty Cycle
fOUT=166.67MHz
M=40, N=5, 16.667MHz XTAL,
fOUT=133.33MHz
53
1
%
tLOCK
PLL Lock Time
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
ICS84021BY REVISION E AUGUST 18, 2011
8
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 7B. AC Characteristics, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
260
Units
MHz
ps
fOUT
Output Frequency
103.3
N = 3
N = 4
N = 5
N = 6
11.4
13.3
16.0
19.2
18.8
28.3
ps
39.8
ps
32.4
ps
tjit(per)
Period Jitter, RMS; NOTE 1, 2
M=40, N=4, 16.667MHz XTAL,
fOUT=166.67MHz
4.3
4.5
6.2
7.7
ps
ps
M=40, N=5, 16.667MHz XTAL,
fOUT=133.33MHz
tsk(o)
Output Skew; NOTE 2, 3
Output Rise/Fall Time
M, N to nP_LOAD
90
ps
ps
ns
ns
ns
ns
ns
ns
%
tR / tF
20% to 80%
100
5
800
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
N ≠ 3
44
56
55
M=40, N=4, 16.667MHz XTAL,
fOUT=166.67MHz
45
47
%
odc
Output Duty Cycle
PLL Lock Time
M=40, N=5, 16.667MHz XTAL,
fOUT=133.33MHz
53
1
%
tLOCK
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
ICS84021BY REVISION E AUGUST 18, 2011
9
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 7C. AC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 5%, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
260
Units
MHz
ps
fOUT
Output Frequency
103.3
N = 3
N = 4
N = 5
N = 6
9.4
13.2
10.8
12.7
13.4
19.6
ps
32.5
ps
25.4
ps
tjit(per)
Period Jitter, RMS; NOTE 1, 2
M=40, N=4, 16.667MHz XTAL,
fOUT=166.67MHz
5.4
5.1
8.3
8.8
ps
ps
M=40, N=5, 16.667MHz XTAL,
fOUT=133.33MHz
tsk(o)
Output Skew; NOTE 2, 3
Output Rise/Fall Time
M, N to nP_LOAD
90
ps
ps
ns
ns
ns
ns
ns
ns
%
tR / tF
20% to 80%
100
5
800
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
N ≠ 3
40
60
56
M=40, N=4, 16.667MHz XTAL,
fOUT=166.67MHz
44
48
%
odc
Output Duty Cycle
PLL Lock Time
M=40, N=5, 16.667MHz XTAL,
fOUT=133.33MHz
52
1
%
tLOCK
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
ICS84021BY REVISION E AUGUST 18, 2011
10
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Parameter Measurement Information
1.65V 5%
1.65V 5%
2.05V 5%
1.25V 5%
2.05V 5%
15Ω
SCOPE
V
DD,
V
DDO
V
DD
SCOPE
15Ω
V
Qx
DDA
V
DDO
Qx
V
DDA
GND
GND
-
-1.65V 5%
-1.25V 5%
3.3V Core/3.3V Output Load AC Test Circuit
3.3V Core/2.5V Output Load AC Test Circuit
2.4V 5%
0.9V 5%
VOH
2.4V 5%
VREF
V
DD
SCOPE
15Ω
VOL
V
DDO
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
Qx
V
DDA
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
GND
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
-0.9V 5%
3.3V Core/1.8V Output Load AC Test Circuit
Period Jitter
VDDO
80%
80%
tR
Qx
Qy
2
20%
20%
Q[0:1]
VDDO
2
tF
tsk(o)
Output Skew
Output Rise/Fall Time
ICS84021BY REVISION E AUGUST 18, 2011
11
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Parameter Measurement Information, continued
VDDO
2
Q[0:1]
tPW
tPERIOD
tPW
x 100%
odc =
tPERIOD
Output Duty Cycle/Pulse Width/Period
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
TEST Output
The unused TEST output can be left floating. There should be no
trace attached.
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
LVCMOS Outputs
All unused LVCMOS outputs can be left floating. We recommend that
there is no trace attached.
TEST_CLK Input
For applications not requiring the use of the test clock, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the TEST_CLK to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
ICS84021BY REVISION E AUGUST 18, 2011
12
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 2A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50Ω
applications, R1 and R2 can be 100Ω. This can also be
accomplished by removing R1 and making R2 50Ω. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
VCC
XTAL_OUT
R1
100
C1
Rs
Zo = 50 ohms
Ro
XTAL_IN
.1uf
R2
100
Zo = Ro + Rs
LVCMOS Driver
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_I N
.1uf
Zo = 50 ohms
R1
50
R2
50
LVPECL Driver
R3
50
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS84021BY REVISION E AUGUST 18, 2011
13
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Layout Guideline
Figure 3 shows a schematic example of the ICS84021. In this
example, a series termination is shown. Additional LVCMOS
termination approaches are shown in the LVCMOS Termination
Application Note. In this example, an 18pF parallel resonant crystal
is used. The C1 = 22pF and C2 = 22pF are approximate values for
frequency accuracy. The C1 and C2 may be slightly adjusted for
optimizing frequency accuracy.
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The ICS84021 provides separate power
supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
C1
X1
C2
Logic Input Pin Examples
22p
22p
Set Logic
Input to '1'
Set Logic
Input to '0'
VDD
VDD
18pF
RU1
1K
RU2
Not Install
U1
VDD
To Logic
Input
To Logic
Input
pins
1
24
R7
M5
M6
M7
M8
N0
N1
nc
X_OU T
T_CLK
2
3
4
5
6
7
8
23
22
21
20
19
18
17
15 - 24
pins
nXTAL_SEL
VDDA
VDDA
RD1
RD2
1K
Not Install
S_LOAD
S_DATA
S_CLOCK
MR
C11
C16
10u
0.01u
GND
ICS84021
VDD
3.3V
BLM18BB221SN1
2
1
1
Ferrite Bead
C18
10uF
C14
0.1u
C17
0.1uF
R1
43
Zo = 50 Ohm
3.3V, 2.5V or 1.8V
BLM18BB221SN2
2
VDDO
R2
43
Zo = 50 Ohm
Ferrite Bead
C20
C19
C15
0.1u
0.1uF
10uF
Figure 3. ICS84021 Application Schematic Example
ICS84021BY REVISION E AUGUST 18, 2011
14
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Reliability Information
Table 8. θJA vs. Air Flow Table for a 32 Lead LQFP
θJA by Velocity
0
Linear Feet per Minut
1
2.5
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
Transistor Count
The transistor count for ICS84021 is: 4325
ICS84021BY REVISION E AUGUST 18, 2011
15
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Package Outline and Package Dimensions
Package Outline - Y Suffix for 32 Lead LQFP
Table 9. Package Dimensions for 32 Lead LQFP
JEDEC Variation: BBC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
0.15
1.45
0.45
0.20
A1
0.05
1.35
0.30
0.09
0.10
1.40
0.37
A2
b
c
D & E
9.00 Basic
7.00 Basic
5.60 Ref.
0.80 Basic
0.60
D1 & E1
D2 & E2
e
L
0.45
0°
0.75
7°
θ
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
ICS84021BY REVISION E AUGUST 18, 2011
16
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Ordering Information
Table 10. Ordering Information
Part/Order Number
84021BY
84021BYT
84021BYLF
84021BYLFT
Marking
ICS84021BY
ICS84021BY
ICS84021BYLF
ICS84021BYLF
Package
32 Lead LQFP
32 Lead LQFP
Shipping Packaging
Tray
1000 Tape & Reel
Tray
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
“Lead-Free” 32 Lead LQFP
“Lead-Free” 32 Lead LQFP
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
ICS84021BY REVISION E AUGUST 18, 2011
17
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T2
4
Pin Characteristics Table - added ROUT rows.
Added Schematic Layout.
B
12
1/5/04
Changed XTAL naming convention to XTAL_IN/XTAL_OUT throughout the data sheet.
1
2
Features Section - added Lead-Free bullet.
Updated Parallel & Serial Load Operations Diagram.
Crystal Characteristics Table - added Drive Level.
Ordering Information Table - added Lead-Free package.
C
6/9/05
T6
7
T10
15
1
Features section - updated RMS period jitter spec in bullet; added RMS phase jitter bullet.
Block Diagram - added pullups/pulldowns to input pins and added “N” in output divider box.
Absolute Maximum Ratings - updated Inputs, VI.
6
6
T4A
T6
Power Supply DC Characteristics - updated VDDA, IDD, IDDA and IDDO specs.
Crystal Characteristics - deleted Drive Level row.
7
T7A - T7C
8 - 10
Updated Period Jitter, Output Rise/Fall Time and Output Duty Cycle specs. Added thermal
note.
D
11
Parameter Measurement Information - corrected Output Load AC Test Circuit diagrams to
1/5/11
coincide with 15Ω VDDA
.
12
13
13
14
17
Added Recommendations for Unused Input & Output Pins.
Deleted Power Supply Filtering Techniques section, added to schematic layout.
Added Overdriving the XTAL Interface section.
Updated Layout Guideline and diagram.
T10
T7A
Ordering Information Table - updated Part/Order Numbers and Marking to revision “B”.
Converted datasheet format.
8
AC Characteristics Table - corrected Period Jitter N = 4 spec, from 32.2ps max. to 34.2ps
max.
E
8/18/11
13
Deleted Crystal Input Interface section, added to the schematic.
ICS84021BY REVISION E AUGUST 18, 2011
18
©2011 Integrated Device Technology, Inc.
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
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party owners.
Copyright 2010. All rights reserved.
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