ICS85214AGILF [IDT]
Low Skew Clock Driver, 85214 Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-150, TSSOP-20;
| 型号： | ICS85214AGILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 85214 Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-150, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-5, Differential-to-HSTL
Fanout Buffer
ICS85214I
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The ICS85214I is a low skew, high performance 1-to-5 Differ- • Five differential HSTL compatible outputs
ential-to-HSTL Fanout Buffer. The CLK0, nCLK0 pair can accept
• Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL
clock inputs
most standard differential input levels. The single ended CLK1 in-
put accepts LVCMOS or LVTTL input levels. Guaranteed output
and part to part skew characteristics make the ICS85214I
ideal for those clock distribution applications demanding
well defined performance and repeatability.
• CLK0, nCLK0 pair can accept the following differential
input levels: LVDS, LVPECL, HSTL, HCSL
• CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Output frequency up to 700MHz
• Translates any single ended input signal to HSTL levels
with resistor bias on nCLK0 input
• Output skew: 40ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Propagation delay:1.8ns (maximum)
• 3.3V core, 1.8V output operating supply
• Available in Lead-Free (RoHS 6) package
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
VDDO
nCLK_EN
VDD
D
nCLK_EN
Q
LE
nc
CLK0
nCLK0
0
CLK1
CLK0
nCLK0
nc
CLK_SEL
GND
Q0
nQ0
1
CLK1
Q1
nQ1
9
10
CLK_SEL
nQ4
Q2
nQ2
ICS85214I
Q3
nQ3
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
Q4
nQ4
ICS8521AGI REVISION B MAY 6, 2011
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©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
GND
Type
Description
Output
Output
Output
Output
Output
Power
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Power supply ground.
3, 4
5, 6
7, 8
9, 10
11
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0, nCLK0 input. LVTTL / LVCMOS interface levels.
12
CLK_SEL
Input
Pulldown
Pullup
13, 17
14
nc
Unused
Input
No connect.
nCLK0
CLK0
CLK1
VDD
Inverting differential clock input.
15
Input
Pulldown Non-inverting differential clock input.
Pulldown Clock input. LVTTL / LVCMOS interface levels.
Power supply pin.
16
Input
18
Power
Synchronizing clock enable. When LOW, clock outputs follow clock input.
Pulldown When HIGH, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
19
nCLK_EN
Input
20
VDDO
Power
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
ICS85214AGI REVISION B MAY 6, 2011
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©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTIONT ABLE
Inputs
Outputs
nCLK_EN
Q0:Q4
Enabled
nQ0:nQ4
0
1
Enabled
Disabled; LOW
Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 inputs as described in Table 3B.
Enabled
Disabled
nCLK0
CLK0
nCLK_EN
nQ0:nQ4
Q0:Q4
FIGURE 1. nCLK_ENTIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTIONTABLE
Inputs
Outputs
CLK1 Q0:Q4 nQ0:nQ4
Input to Output Mode
Polarity
CLK_SEL
CLK0
nCLK0
0
0
0
0
0
0
1
1
0
1
X
X
X
X
X
X
0
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
Differential to Differential
Differential to Differential
Non Inverting
Non Inverting
1
0
0
Biased; NOTE 1
Single Ended to Differential Non Inverting
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
Biased; NOTE 1
0
1
Single Ended to Differential
Single Ended to Differential
Inverting
Inverting
Biased; NOTE 1
X
X
X
X
Single Ended to Differential Non Inverting
Single Ended to Differential Non Inverting
1
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
ICS85214AGI REVISION B MAY 6, 2011
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©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
I
Outputs, IO
Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Power Supply Voltage
3.465
2.0
V
V
Output Power Supply Voltage
Power Supply Current
1.6
1.8
80
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
nCLK_EN, CLK_SEL
CLK1
2
V
DD + 0.3
DD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
2
V
nCLK_EN, CLK_SEL
CLK1
-0.3
-0.3
Input Low Voltage
1.3
CLK1, CLK_SEL,
nCLK_EN
CLK1, CLK_SEL,
nCLK_EN
IIH
IIL
Input High Current
Input Low Current
VDD = VIN = 3.465V
150
µA
µA
VDD = 3.465V, VIN = 0V
-5
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ,VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
Minimum Typical Maximum Units
nCLK0
CLK0
5
µA
µA
µA
µA
V
150
nCLK0
CLK0
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD - 0.85
V
NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
ICS85214AGI REVISION B MAY 6, 2011
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©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 4D. HSTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Output High Voltage;
NOTE 1
VOH
1
1.4
V
Output Low Voltage;
NOTE 1
VOL
0
38ꢀ x (VOH - VOL) + VOL
0.6
0.4
60ꢀ x (VOH - VOL) + VOL
1.1
V
V
V
VOX
Output Crossover Voltage
Peak-to-Peak
Output Voltage Swing
VSWING
NOTE 1: Outputs terminated with 50Ω to ground.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V,TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK0, nCLK0
CLK1
700
300
1.8
40
MHz
MHZ
ns
fOUT
Output Frequency
tPD
Propagation Delay; NOTE 1
IJ 700MHz
1.0
tsk(o)
tsk(pp)
tR / tF
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
ps
300
800
54
ps
20ꢀ to 80ꢀ
200
46
ps
CLK0, nCLK0
CLK1
ꢀ
odc
Output Duty Cycle
IJ 266MHz
44
56
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at fOUT unless noted otherwise.
NOTE: The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS85214AGI REVISION B MAY 6, 2011
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©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V 5ꢀ
1.8V 0.2V
VDD
SCOPE
VDD
Qx
nCLK0
CLK0
VDDO
VPP
VCMR
Cross Points
HSTL
GND
nQx
GND
0V
3.3V/1.8V OUTPUT LOAD ACTEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
80ꢀ
tF
80ꢀ
tR
CLK1
VSWING
20ꢀ
Clock
20ꢀ
nQ0:nQ4
Outputs
Q0:Q4
tPD
OUTPUT RISE/FALLT IME
nQ0:nQ4
Q0:Q4
nCLK0
CLK0
tPW
tPERIOD
nQ0:nQ4
tPW
Q0:Q4
odc =
x 100ꢀ
tPD
tPERIOD
OUTPUT DUTY CYCLE/PULSEWIDTH/PERIOD
PROPAGATION DELAY
ICS85214AGI REVISION B MAY 6, 2011
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©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
APPLICATIONS INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how a differential input can be wired to accept
single ended levels.The reference voltageVREF =VDD/2 is generated
by the bias resistors R1 and R2. The bypass capacitor (C1) is
used to help filter noise on the DC bias. This bias circuit should
be located as close to the input pin as possible. The ratio of R1
and R2 might need to be adjusted to position the VREF in the
center of the input voltage swing. For example, if the input clock
swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted
to set VREF at 1.25V.The values below are for when both the single-
ended swing and VDD are at the same voltage. This configuration
requires that the sum of the output impedance of the driver (Ro)
and the series resistance (Rs) equals the transmission line
impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50 applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading
for slower and weaker LVCMOS driver. When using single ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
ICS85214AGI REVISION B MAY 6, 2011
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©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, HCSL and examples only. Please consult with the vendor of the driver
other differential signals. Both differential signals must meet component to confirm the driver termination requirements. For
the VPP and VCMR input requirements. Figures 3A to 3E show example in Figure 3A, the input termination applies for IDT
interface examples for the CLK/nCLK input driven by the most open emitter LVHSTL drivers. If you are using an LVHSTL
common driver types. The input interfaces suggested here are driver from another vendor, use their termination
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Differential
Input
nCLK
LVPECL
Differential
Input
R1
50
R2
50
LVHSTL
R1
50
R2
50
IDT
HiPerClockS
LVHSTL Driver
R2
50
FIGURE 3A. CLK/nCLK INPUT DRIVEN BY AN
FIGURE 3B. CLK/nCLK INPUT DRIVEN BY A
3.3V LVPECL DRIVER
IDT OPEN EMITTER LVHSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
Differential
Input
Receiver
LVPECL
LVDS
R1
84
R2
84
FIGURE 3C. CLK/nCLK INPUT DRIVEN BY A
3.3V LVPECL DRIVER
FIGURE 3D. CLK/nCLK INPUT DRIVEN BY A
3.3V LVDS DRIVER
2.5V
3.3V
Zo = 50Ω
*R3
*R4
33
33
CLK
Zo = 50Ω
nCLK
Differential
Input
HCSL
R1
50
R2
50
*Optional – R3 and R4 can be 0Ω
FIGURE 3E. CLK/nCLK INPUT DRIVEN BY A
3.3V HCSL DRIVER
ICS85214AGI REVISION B MAY 6, 2011
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©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of the ICS85214I. In this near the power pin. For ICS85214I, the unused outputs can be
example, the input is driven by an HSTL driver. The decoupling left floating.
capacitors should be physically located
Zo = 50
+
Zo = 50
-
R2
50
R1
50
U1
1.8V
R12 1K
11
12
13
14
15
16
17
18
19
20
10
9
8
7
6
5
4
3
2
1
GND
CLK_SEL
nc
nCLK
CLK
SCLK
nc
VDD
nCLK_EN
VDDO
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
Zo = 50
Zo = 50
+
-
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
C2
1.8V
R4
50
R3
50
LVHSTL Driver
R9
50
R10
50
0.1u
C1
0.1u
ICS85214I
Zo = 50
+
-
R11
1K
Zo = 50
R8
50
R7
50
FIGURE 4. ICS85214I HSTL BUFFER SCHEMATIC EXAMPLE
ICS85214AGI REVISION B MAY 6, 2011
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©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85214I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85214I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 80mA = 227.2mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 32.8mW = 164mW
Total Power_MAX (3.465V, with all outputs switching) = 227.2mW + 164mW = 391.2mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.391W * 66.6°C/W = 111°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θ
JA by Velocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
ICS85214AGI REVISION B MAY 6, 2011
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©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 5.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 5. HSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
)
OH_MIN
L
DDO_MAX
DDO_MAX
OH_MIN
/R ) * (V
- V
)
OL_MAX
L
OL_MAX
Pd_H = (1.0V/50Ω) * (2V - 1.0V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
ICS85214AGI REVISION B MAY 6, 2011
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©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θ
JA by Velocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85214I is: 674
ICS85214AGI REVISION B MAY 6, 2011
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©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEADTSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS85214AGI REVISION B MAY 6, 2011
13
©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 9.ORDERING INFORMATION
Part/Order Number
85214AGI
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS85214AGI
ICS85214AGI
20 lead TSSOP
85214AGIT
20 Lead TSSOP
2500 tape & reel
tube
85214AGILF
ICS85214AGIL
ICS85214AGIL
20 Lead "Lead-Free" TSSOP
20 Lead "Lead-Free" TSSOP
85214AGILFT
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS
compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc.(IDT) assumes no responsibility for either its use or for infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications
such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications
without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
ICS85214AGI REVISION B MAY 6, 2011
14
©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
A
T9
14
Added Lead-Free marking in Ordering Information table.
6/1/05
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
B
T9
15
16
7/25/10
4 - 5
AC/DC Characteristics Tables - corrected temperature in table headings from 0°C to
-40°C.
T5
T9
5
7
14
AC Characteristics Table - Added thermal note.
Updated Wiring the differential Input to Accept Single Ended Levels application note.
Ordering Information Table - Part/Order Number column, added suffix "T" in the order
number for table and reel.
B
5/6/11
Updated header and footer of the document.
ICS85214AGI REVISION B MAY 6, 2011
15
©2011 Integrated Device Technology, Inc.
ICS85214I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
We’ve Got Your Timing Solution.
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© 2011 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are
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marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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