ICS85357AG-01LFT [IDT]
Multiplexer, 85357 Series, 1-Func, 4 Line Input, 1 Line Output, Complementary Output, PDSO20, 4.40 X 6.50 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20;
| 型号： | ICS85357AG-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Multiplexer, 85357 Series, 1-Func, 4 Line Input, 1 Line Output, Complementary Output, PDSO20, 4.40 X 6.50 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20 光电二极管 |
| 文件： | 总13页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS85357-01 is a 4:1 or 2:1 Differential-to- • High speed differential multiplexer.The device can be
ICS
3.3V LVPECL / ECL clock multiplexer which can
operate up to 750MHz and is a member of the
HiPerClockS™family of High Perfor mance Clock
Solutions from ICS. The ICS85357-01 has 4
configured as either a 4:1 or 2:1 multiplexer
• 1 differential 3.3V LVPECL output
• 4 selectable CLK, nCLK inputs
HiPerClockS™
selectable clock inputs.The CLK, nCLK pair can accept most
standard differential input levels. The device can operate
using a 3.3V LVPECL (VEE = 0V, VCC = 3.135V to 3.465V) or
3.3V ECL (VCC = 0V, VEE = -3.135V to -3.465V). The fully dif-
ferential architecture and low propagation delay make it
ideal for use in clock distribution circuits.The select pins have
internal pulldown resistors. Leaving one input unconnected
(pulled to logic low by the internal resistor) will transform
the device into a 2:1 multiplexer. The SEL1 pin is the most
significant bit and the binary number applied to the select pins
will select the same numbered data input (i.e., 00
selects CLK0, nCLK0).
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 750MHz
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nCLKx input
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.5ns (maximum)
• LVPECL mode operating voltage supply range:
VCC = 3.135V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.135V to -3.465V
• 0°C to 70°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
VCC
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
VEE
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
VCC
SEL1
SEL0
VCC
Q0
nQ0
VCC
nc
CLK0
00
nCLK0
CLK1
01
nCLK1
Q0
nQ0
CLK2
10
nCLK2
9
10
nc
VEE
CLK3
11
nCLK3
ICS85357-01
20-LeadTSSOP
4.40mm x 6.50mm x 0.90mm body package
G Package
SEL0
SEL1
TopView
85357AG-01
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REV. A MARCH 21, 2005
1
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 14,
17, 20
VCC
Power
Positive supply pins.
2
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
VEE
Input
Input
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential clock input.
3
4
Input
5
Input
6
7
Input
Input
8
Input
9
Input
Pullup
Inverting differential clock input.
Negative supply pins.
10, 11
12, 13
15, 16
18
Power
Unused
Output
Input
nc
No connect.
nQ0, Q0
SEL0
SEL1
Differential output pairs. LVPECL interface levels.
Pulldown Clock select input. LVCMOS / LVTTL interface levels.
Pulldown Clock select input. LVCMOS / LVTTL interface levels.
19
Input
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
kΩ
kΩ
RPULLUP
RPULLDOWN
51
51
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs
Clock Out
CLK
SEL1
SEL0
0
0
1
1
0
1
0
1
CLK0, nCLK0
CLK1, nCLK1
CLK2, nCLK2
CLK3, nCLK3
85357AG-01
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REV. A MARCH 21, 2005
2
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
73.2°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
35
V
IEE
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage SEL0, SEL1
Input Low Voltage SEL0, SEL1
Input High Current SEL0, SEL1
Input Low Current SEL0, SEL1
2
3.765
0.8
V
V
-0.3
VCC = VIN = 3.465V
150
µA
µA
IIL
VCC = 3.465V, VIN = 0V
-5
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK0, CLK1,
CLK2, CLK3
VCC = VIN = 3.465V
150
5
µA
IIH
Input High Current
nCLK0, nCLK1,
nCLK2, nCLK3
VCC = VIN = 3.465V
µA
µA
CLK0, CLK1,
CLK2, CLK3
nCLK0, nCLK1,
nCLK2, nCLK3
VCC = 3.465V, VIN = 0V
-5
IIL
Input Low Current
V
CC = 3.465V, VIN = 0V
-150
0.15
µA
V
VPP
Peak-to-Peak Voltage
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
VEE + 0.5
VCC - 0.85
V
NOTE 1: Common mode input voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V.
85357AG-01
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REV. A MARCH 21, 2005
3
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 1.0
VCC -1.7
0.85
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter Test Conditions
Minimum
Typical
1.2
Maximum Units
fMAX
Maximum Output Frequency
750
1.5
150
700
53
MHz
ns
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
IJ 750MHz
1
tsk(pp)
tR / tF
odc
ps
20ꢀ to 80ꢀ @50MHz
300
47
400
ps
Output Duty Cycle
ꢀ
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
85357AG-01
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REV. A MARCH 21, 2005
4
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nCLK0:
nCLK3
LVPECL
VPP
VCMR
Cross Points
nQx
CLK0:
CLK3
VEE
-1.3V 0.165V
VEE
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
nCLK0:
nCLK3
CLK0:
CLK3
PART 1
Qx
nQy
nQ0
PART 2
Qy
Q0
tPD
tsk(pp)
PART-TO-PART SKEW
PROPAGATION DELAY
nQ0
80ꢀ
tF
80ꢀ
Q0
VSWING
20ꢀ
Pulse Width
Clock
20ꢀ
tPERIOD
Outputs
tR
tPW
tPERIOD
odc =
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
85357AG-01
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REV. A MARCH 21, 2005
5
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit should be located as close as possible to the input pin.The ratio of
R1 and R2 might need to be adjusted to position theV_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
85357AG-01
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REV. A MARCH 21, 2005
6
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3E show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
85357AG-01
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REV. A MARCH 21, 2005
7
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85357-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85357-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 35mA = 121.3mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW
Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120.8mW = 151.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.151W * 66.6°C/W = 80.06°C. This is well below the limit of 125°C
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
85357AG-01
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REV. A MARCH 21, 2005
8
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
85357AG-01
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REV. A MARCH 21, 2005
9
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85357-01 is: 400
85357AG-01
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REV. A MARCH 21, 2005
10
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
85357AG-01
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REV. A MARCH 21, 2005
11
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS85357AG-01
ICS85357AG-01T
ICS85357AG-01LF
ICS85357AG-01LFT
ICS85357AG01
ICS85357AG01
ICS85357A01L
ICS85357A01L
20 lead TSSOP
20 lead TSSOP
2500 tape & reel
tube
20 lead "Lead-Free" TSSOP
20 lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
85357AG-01
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REV. A MARCH 21, 2005
12
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
Table
Page
7
12
Description of Change
Date
A
Added Termination for LVPECL Outputs section.
5/30/02
9
Ordering Information Table, revised Marking to read ICS85357AG01 from
ICS85357AG-01.
Output Load Test Circuit Diagram, changed VEE = -1.3V 0.135V to
A
A
8/16/02
3/21/05
5
V
EE = -1.3 0.165V.
Features Section - added Lead-Free bullet.
Added "Differential Clock Input Interface" section.
Ordering Information Table - added Lead-Free part number and note.
Updated datasheet format.
1
7
12
T9
85357AG-01
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REV. A MARCH 21, 2005
13
相关型号：
ICS85357AG-11LF
Clock Generator, 27MHz, PDSO20, 4.40 X 6.50 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
IDT
ICS85357AG-11LFT
Clock Generator, 27MHz, PDSO20, 4.40 X 6.50 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
IDT
ICS85357AGI-01LFT
Multiplexer, 85357 Series, 1-Func, 4 Line Input, 1 Line Output, Complementary Output, PDSO20, 4.40 X 6.50 MM, 0.90 MM HEIGHT, MO-153, TSSOP-20
IDT
ICS85357AGI-01T
Multiplexer, 85357 Series, 1-Func, 4 Line Input, 1 Line Output, Complementary Output, PDSO20, 4.40 X 6.50 MM, 0.90 MM HEIGHT, MO-153, TSSOP-20
IDT
ICS8535AG-01LF
Low Skew Clock Driver, 8535 Series, 4 True Output(s), 4 Inverted Output(s), PDSO20, ROHS COMPLIANT, 4.40 X 6.50 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
ICS8535AG-01LFT
Low Skew Clock Driver, 8535 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20
IDT
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