ICS87332AMI-01LF [IDT]
Low Skew Clock Driver, 87332 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, ROHS COMPLIANT, MS-012, SOIC-8;
| 型号： | ICS87332AMI-01LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 87332 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, ROHS COMPLIANT, MS-012, SOIC-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总14页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
÷2, Differential-to-2.5V/3.3V
ICS87332I-01
ECL/LVPECL Clock Generator
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The ICS87332I-01 is a high performance ÷2 Differen- • One ÷2 differential 2.5V/3.3V LVPECL / ECL output
ICS
HiPerClockS™
tial-to-2.5V/3.3V ECL/LVPECL Clock Generator. The
• One CLK, nCLK input pair
CLK, nCLK pair can accept most standard differential
input levels The ICS87332I-01 is characterized to op-
erate from either a 2.5V or a 3.3V power supply. Guar-
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
anteed output and part-to-part skew characteristics make the
ICS87332I-01 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
• Maximum output frequency: 500MHz
• Maximum input frequency: 1GHz
• Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
• Part-to-part skew: 400ps (maximum)
• Propagation delay: 1.6ns (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
MR
CLK
nCLK
nc
Vcc
Q
1
2
3
4
8
7
6
5
Q
nQ
CLK
nCLK
÷2
nQ
VEE
ICS87332I-01
MR
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
1
©2009 Integrated Device Technology, Inc.
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
Master reset. When LOW, outputs are enabled. When HIGH,
1
MR
Input
Pulldown divider is reset forcing Q output LOW and nQ output HIGH.
LVCMOS / LVTTL interface level.
2
3
CLK
nCLK
nc
Input
Input
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
No connect.
4
Unused
Power
Output
Power
5
VEE
Negative supply pin.
6, 7
8
Q, nQ
VCC
Differential output pair. LVPECL interface levels.
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
CLK
MR
Q
FIGURE 1. TIMING DIAGRAM
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
2
©2009 Integrated Device Technology, Inc.
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θJA 112.7°C/W (0 lfpm)
StorageTemperature, T -65°C to 150°C
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Positive Supply Voltage
Power Supply Current
2.375
3.3
3.8
30
V
IEE
mA
TABLE 3B. LVCMOS DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage
MR
2
VCC + 0.3
0.8
V
VIL
IIH
Input Low Voltage
Input High Current
Input Low Current
MR
MR
MR
-0.3
V
VCC = VIN = 3.8V
150
µA
µA
IIL
VCC = 3.8V, VIN = 0V
-5
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
CC = VIN = 3.8V
Minimum
Typical
Maximum Units
CLK
V
150
5
µA
µA
µA
µA
V
nCLK
CLK
VCC = VIN = 3.8V
V
CC = 3.8V, VIN = 0V
-5
IIL
Input Low Current
nCLK
VCC = 3.8V, VIN = 0V
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
V
EE + 0.5
VCC - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
3
©2009 Integrated Device Technology, Inc.
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VCC - 1.4
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VSWING
Peak-to-Peak Output Voltage Swing
0.65
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol Parameter
fMAX Input Frequency
tPD
Test Conditions
Minimum
Typical
Maximum Units
1
GHz
ns
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise Time
IJ 1GHz
1.1
1.4
1.6
400
700
700
51
tsk(pp)
tR
ps
20% to 80%
20% to 80%
200
200
49
ps
tF
Output Fall Time
ps
odc
Output Duty Cycle
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
4
©2009 Integrated Device Technology, Inc.
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nCLK
CLK
LVPECL
VEE
VPP
VCMR
Cross Points
nQx
-1.8V to -0.375V
VEE
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nCLK
CLK
Qx
PART 2
nQy
nQ
Qy
Q
tPD
tsk(pp)
PART-TO-PART SKEW
PROPAGATION DELAY
nQ
Q
tPW
nQ
tPERIOD
80%
tF
80%
VSWING
20%
tPW
tPERIOD
odc =
x 100%
20%
Q
tR
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
5
©2009 Integrated Device Technology, Inc.
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/
R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
signed to drive 50Ω transmission lines. Matched impedance
techniques should be used to maximize operating frequency
and minimize signal distortion. Figures 3A and 3B show two
different layouts which are recommended only as guidelines.
Other suitable clock layouts may exist and it would be recom-
mended that the board designers simulate to guarantee com-
patibility across all printed circuit and clock component pro-
The differential outputs are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. Therefore,
terminating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are de-
3.3V
R3
125Ω
R4
125Ω
3.3V
3.3V
3.3V
Z
o = 50Ω
3.3V
+
_
Z
o = 50Ω
+
_
Input
LVPECL
Zo = 50Ω
LVPECL
Input
Zo = 50Ω
R1
R2
50Ω
50Ω
R1
84Ω
R2
84Ω
VCC - 2V
1
RTT =
* Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 3A. LVPECL OUTPUTTERMINATION
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
FIGURE 3B. LVPECL OUTPUTTERMINATION
©2009 Integrated Device Technology, Inc.
6
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 4A and Figure 4B show examples of termination for 2.5V level. The R3 in Figure 4B can be eliminated and the termination
LVPECL driver. These terminations are equivalent to terminating is shown in Figure 4C.
50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
7
©2009 Integrated Device Technology, Inc.
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 5A to 5F show interface ex-
amples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm
the driver termination requirements. For example in Figure 5A,
the input termination applies for IDT open emitter LVHSTL drivers.
If you are using an LVHSTL driver from another vendor, use their
termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 5A. CLK/nCLK INPUT DRIVEN BY AN IDT OPEN
EMITTER LVHSTL DRIVER
FIGURE 5B. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL
DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 5C. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL
DRIVER
FIGURE 5D. CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
2.5V
2.5V
3.3V
3.3V
2.5V
R3
R4
120
120
Zo = 50Ω
Zo = 50Ω
*R3
*R4
33
33
Zo = 60Ω
Zo = 60Ω
CLK
CLK
nCLK
nCLK
HiPerClockS
HiPerClockS
Input
SSTL
HCSL
R1
50
R2
50
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
FIGURE 5F. CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER
FIGURE 5E. CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
8
©2009 Integrated Device Technology, Inc.
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS87332I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS87332I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 30mA = 114mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.8V, with all outputs switching) = 114mW + 30mW = 144mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature for HiPerClockSTM devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.144W * 103.3°C/W = 99.9°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
TABLE 5. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θ
JA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC StandardTest Boards
Multi-Layer PCB, JEDEC StandardTest Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
9
©2009 Integrated Device Technology, Inc.
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V – 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
– V
/R ] * (V
– V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
L
CC
L
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
– V
/R ] * (V
– V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
10
©2009 Integrated Device Technology, Inc.
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
θ
JA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC StandardTest Boards
Multi-Layer PCB, JEDEC StandardTest Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87332I-01 is: 383
Compatible to part number MC100EP32
PACKAGE OUTLINE AND DIMENSIONS
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
PACKAGE OUTLINE - M SUFFIX
Millimeters
MINIMUN
MAXIMUM
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
11
©2009 Integrated Device Technology, Inc.
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
87332AMI-01
Marking
7332AI01
7332AI01
332AI01L
332AI01L
Package
8 lead SOIC
Shipping Package
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
87332AMI-01T
8 lead SOIC
2500 tape & reel
tube
87332AMI-01LF
87332AMI-01LFT
8 lead "Lead-Free" SOIC
8 lead "Lead-Free" SOIC
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any
patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any
other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT.IDT reserves the right to change any circuitry
or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
12
©2009 Integrated Device Technology, Inc.
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
1
2
6
Features Section - added Lead-Free bullet.
T2
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Added "Wiring the Differential Input to Accept Single Ended Levels.
Added Termination for 3.3V LVPECL Output.
6
B
7
Added Termination for 2.5V LVPECL Output.
7/5/05
8
Added Differential Clock Input Interface.
T8
13
Ordering Information Table - corrected marking. Added Lead-Free part number
and note.
Updated format of datasheet.
T3D
4
LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to
C
C
V
CC - 0.9V; and VSWING max. from 0.9V to 1.0V.
4/13/07
9 - 10
4
6
8
12
Power Considerations - corrected power dissipation to reflect VOH max in Table 3D.
Added thermal note to AC Characteristics table.
Updated figures 3A & 3B, LVPECL Output Termination diagrams.
Updated Differential Clock Input Interface.
Ordering Information Table - add LF marking. Deleted "ICS" prefix from part/order
number.
T4
11/16/09
Updated header/footer of datasheet.
ICS87332AMI-01 REVISION C NOVEMBER 16, 2009
13
©2009 Integrated Device Technology, Inc.
ICS87332I-01 Data Sheet
÷2DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL CLOCK GENERATOR
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