ICS87339AG-01LF [IDT]
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 X 0.92 MM, TSSOP-20;
| 型号： | ICS87339AG-01LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 X 0.92 MM, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总15页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87339-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS87339-01 is a low skew, high perfor- • 2 divide by 2/4 differential 3.3V LVPECL outputs;
mance Differential-to-3.3V LVPECL / ECL Clock
Generator/Divider and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS87339-01 has one
2 divide by 4/6 differential 3.3V LVPECLoutputs
HiPerClockS™
• 1 differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
differential clock input pair. The CLK, nCLK pair can accept
most standard differential input levels. The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum input frequency: 1GHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics
make the ICS87339-01 ideal for clock distribution applications
demanding well defined performance and repeatability.
• Output skew: 50ps (maximum)
• Part-to-part skew: 200ps (maximum)
• LVPECLmode operating voltage supply range:
VCC = 3V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3V to -3.8V
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Compatible with MC100LVEL39
BLOCK DIAGRAM
PIN ASSIGNMENT
DIV_SELA
VCC
nCLK_EN
DIV_SELB
CLK
VCC
1
2
3
4
20
19
18
17
16
15
14
13
12
11
QA0
nQA0
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
VEE
D
nCLK_EN
÷2, ÷4
QA1
nQA1
Q
R
nCLK
nc
MR
VCC
nc
5
6
7
8
9
10
LE
CLK
nCLK
DIV_SELA
QB0
nQB0
ICS87339-01
20-Lead TSSOP, G Package
6.5mm x 4.4mm x 0.92mm
body package
÷4, ÷6
QB1
nQB1
R
MR
Top View
DIV_SELB
ICS87339-01
20-Lead SOIC, M Package
7.5mm x 12.8mm x 2.25
package body
Top View
87339AG-01
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REV. A AUGUST 15, 2002
1
ICS87339-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
1, 8, 20
2
Name
VCC
Type
Description
Power
Input
Positive supply pins.
nCLK_EN
Pulldown Clock enable.
Selects divide value for Bank B outputs as described in Table 3.
3
DIV_SELB
Input
Pulldown
LVCMOS / LVTTL interface levels.
4
5
CLK
nCLK
nc
Input
Input
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
6, 9
Unused
No connect.
Active High Master Reset. When logic HIGH, the internal dividers
7
MR
Input
Pulldown are reset. When LOW, the Master Reset is disabled.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank A outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
10
DIV_SELA
VEE
Input
Pulldown
11
Power
Negative supply pin.
12, 13
14, 15
16, 17
18, 19
nQB1, QB1 Output
nQB0, QB0 Output
nQA1, QA1 Output
nQA0, QA0 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
QA0 thru QA1 nQA0 thru nQA1 QB0 thru QB1 nQB0 thru nQB1
MR nCLK_EN DIV_SELA
DIV_SELB
1
0
0
0
0
0
X
1
0
0
0
0
X
X
0
0
1
1
X
X
0
1
0
1
LOW
HOLD Qx
÷2
HIGH
HOLD Qx
÷2
LOW
HOLD Qx
÷4
HIGH
HOLD Qx
÷4
÷2
÷2
÷6
÷6
÷4
÷4
÷4
÷4
÷4
÷4
÷6
÷6
NOTE: After nCLK_EN switches, the clock outputs stop switching following a rising and falling input clock edge.
87339AG-01
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ICS87339-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
73.2°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = 0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
Positive Supply Voltage
Power Supply Current
3.0
3.6
V
IEE
85
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
nCLK_EN, MR,
DIV_SELA, DIV_SELB
nCLK_EN, MR,
IIH
IIL
VIN = VCC = 3.6V
150
µA
µA
Input Low Current
VIN = 0V, VCC = 3.6V
-5
DIV_SELA, DIV_SELB
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VCC = 3.6V
Minimum Typical Maximum Units
nCLK
CLK
5
µA
µA
µA
µA
V
VIN = VCC = 3.6V
150
nCLK
CLK
VIN = 0V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
VEE + 0.5
VCC - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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REV. A AUGUST 15, 2002
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ICS87339-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum Typical
VCC - 1.4
Maximum Units
VOH
Output High Voltage; NOTE1
VCC - 1.0
VCC - 1.7
0.85
V
V
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VSWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum
Typical
Maximum Units
fMAX
tpLH
tpHL
tsk(o)
tsk(pp)
tS
Maximum Toggle Frequency
1
3
GHz
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
Propagation Delay; NOTE 1
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
1
1
3
50
500
Part-to-Part Skew; NOTE 3, 4
Setup Time
nCLK_EN to CLK
CLK to nCLK_EN
250
100
tH
Hold Time
tRR
Reset Recovery Time
300
tPW
Minimum Pulse Width CLK
Output Rise Time
500
200
200
tR
20% to 80%
20% to 80%
700
700
tF
Output Fall Time
All parameters measured up to 1GHz unless noted otherwise.
This device does not add measureable jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
87339AG-01
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REV. A AUGUST 15, 2002
4
ICS87339-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VCC
SCOPE
Qx
LVPECL
VCC = 2V
nQx
VEE = -1.3V ± 0.3V
3.3V OUTPUT LOAD TEST CIRCUIT
VCC
nCLK
VPP
VCMR
Cross Points
CLK
VEE
DIFFERENTIAL INPUT LEVEL
87339AG-01
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REV. A AUGUST 15, 2002
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ICS87339-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
nQx
Qx
nQy
Qy
tsk(o)
OUTPUT SKEW
nQx
PART1
Qx
nQy
PART2
Qy
tsk(pp)
PART-TO-PART SKEW
80%
80%
VSWING
20%
20%
Clock Outputs
tR
tF
OUTPUT RISE AND FALL TIME
87339AG-01
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REV. A AUGUST 15, 2002
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ICS87339-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
nCLK
CLK
nQA0, nQA1, nQB0, nQB1
QA0, QA1, QB0, QB1
tPD
PROPAGATION DELAY
nQA0, nQA1, nQB0, nQB1
QA0, QA1, QB0, QB1
Pulse Width
tPERIOD
tPW & tPERIOD
87339AG-01
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REV. A AUGUST 15, 2002
7
ICS87339-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 1 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
5
2
5
Zo
Zo
2
FIN
FOUT
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
➤
VCC - 2V
Zo = 50Ω
RTT
1
3
2
3
2
Zo
RTT =
Zo
Zo
(VOH + VOL / VCC –2) –2
FIGURE 2A - LVPECL OUTPUT TERMINATION
FIGURE 2B - LVPECL OUTPUT TERMINATION
87339AG-01
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REV. A AUGUST 15, 2002
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ICS87339-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS87339-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS87339-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * ICC_MAX = 3.6V * 95mA = 342
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
Total Power_MAX (3.6V, with all outputs switching) = 342mW + 120.8mW = 462.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA =Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6Abelow.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.463W * 66.6°C/W = 101°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE qJA FOR 20-PIN TSSOP, FORCED CONVECTION
q by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. THERMAL RESISTANCE qJA FOR 20-PIN SOIC, FORCED CONVECTION
q by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS87339-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 3.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 3 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
/R ] * (V
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
/R ] * (V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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ICS87339-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TSSOP TABLE
q
by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. θJAVS. AIR FLOW SOIC TABLE
q
by Velocity (Linear Feet per Minute)
0
JA
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87339-01 is: 1745
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LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX
TABLE 8A. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
PACKAGE OUTLINE - M SUFFIX
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
20
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
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ICS87339-01
Integrated
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Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS87339AG-01
ICS87339AG-01T
ICS87339AM-01
ICS87339AM-01T
Marking
Package
20 lead TSSOP
Count
72 per Tube
2500
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS87339AG01
ICS87339AG01
ICS87339AM01
ICS87339AM01
20 lead TSSOP on Tape and Reel
20 lead SOIC
38 per Tube
1000
20 lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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Integrated
Circuit
Systems, Incꢀ
LOW SKEW, ÷2/4,÷4/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
T1
Page
Description of Change
Date
A
8
2
6
Added Termination for LVPECL Outputs section.
Pin Description Table, revised MR description.
Updated Output Rise & Fall Time diagram.
5/31/02
A
8/15/02
87339AG-01
www.icst.com/products/hiperclocks.html
REV. A AUGUST 15, 2002
15
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