ICS9112BM-18LF [IDT]
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16;型号: | ICS9112BM-18LF |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16 驱动 光电二极管 逻辑集成电路 |
文件: | 总5页 (文件大小:74K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ICS9112-18
ZERO DELAY, LOW SKEW BUFFER
Description
Features
The ICS9112-18 is a low jitter, low skew, high
• Packaged in 16 pin SOIC
performance Phase Lock Loop (PLL) based zero delay
buffer for high speed applications. Based on ICS’
proprietary low jitter PLL techniques, the device
provides eight low skew outputs at speeds up to 160
MHz at 3.3V. The ICS9112-18 includes a bank of four
outputs running at 1/2X. In the zero delay mode, the
rising edge of the input clock is aligned with the rising
edges of all eight outputs. Compared to competitive
CMOS devices, the ICS9112-18 has the lowest jitter.
• Zero input-output delay
• Four 1X outputs plus four 1/2X outputs
• Output to output skew is less than 250 ps
• Output clocks up to 160 MHz at 3.3V
• Ability to generate 2X the input
• Full CMOS outputs with 18 mA output drive
capability at TTL levels at 3.3V
• Spread SmartTM technology works with spread
ICS manufactures the largest variety of clock
generators and buffers and is the largest clock supplier
in the world.
spectrum clock generators
• Advanced, low power, sub micron CMOS process
• Operating voltage of 3.3V or 5V
Block Diagram
VDD
2
CLKA1
CLKA2
CLKA3
CLKA4
FBIN
PLL
CLKIN
/2
CLKB1
CLKB2
CLKB3
CLKB4
Control
Logic
2
S1, S0
2
GND
MDS 9112-18 G
1
Revision 121302
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS9112-18
ZERO DELAY, LOW SKEW BUFFER
Pin Assignment
Feedback Configuration Table
Feedback From
Bank A
CLKA1:A4
CLKIN
CLKB1:B4
CLKIN/2
CLKIN
CLKIN
CLKA1
CLKA2
VDD
1
2
3
4
5
6
7
8
FBIN
16
15
14
13
12
11
10
9
CLKA4
CLKA3
VDD
Bank B
2XCLKIN
GND
GND
CLKB1
CLKB2
S2
CLKB4
CLKB3
S1
16 Pin (150 mil) SOIC
Output Clock Mode Select Table
S2 S1
Clocks A1:A4
Clocks B1:B4
Internet Generation
PLL Status
0
0
1
1
0
1
0
1
Tri-state (high impedance) Tri-state (high impedance)
None
On
On
Off
On
Running
Running
Running
Tri-state (high impedance)
Running
PLL
Buffer only (no zero delay)
PLL
Running
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
1
2 - 3
4
CLKIN
Input Clock input. Connect to input clock source.
CLKA1:A4 Output Clock A bank of four outputs.
VDD
GND
Power Power supply. Connect pin to same voltage as pin 13 (either 3.3V or 5V).
Power Connect to ground.
5
6 - 7
8
CLKB1:B4 Output Clock B bank of four outputs. These are low skew divide by two of bank A.
S2
S1
Input Select input 2. Selects mode for outputs per table above.
Input Select input 1. Selects mode for outputs per table above.
9
10 - 11
12
CLKB1:B4 Output Clock B bank of four outputs. These are low skew divide by two of bank A.
GND
VDD
Power Connect to ground.
13
Power Power supply. Connect pin to same voltage as pin 4 (either 3.3V or 5V).
14 - 15
16
CLKA1:A4 Output Clock A bank of four outputs.
FBIN Input Feedback input. Determines outputs per table above.
MDS 9112-18 G
2
Revision 121302
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS9112-18
ZERO DELAY, LOW SKEW BUFFER
External Components
The ICS9112-18 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1 µF should be connected between VDD and GND, as close to the part as possible. A 33 Ω
series terminating resistor should be used on each clock output to reduce reflections.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS9112-18. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70 °C
-65 to +150 °C
175 °C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260 °C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.0
+5.5
V
DC Electrical Characteristics
VDD=3.3 V ±10%, Ambient temperature 0 to +70°C
Parameter
Operating Voltage
Symbol
VDD
VIH
Conditions
Min.
Typ.
Max.
5.5
Units
3.0
V
V
V
V
V
V
V
V
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
CLKIN pin only
CLKIN pin only
(VDD/2)+1 VDD/2
VIL
VDD/2 (VDD/2)-1
VIH
2
VIL
0.8
0.4
VOH
VOL
IOH = -18mA
IOL = 18mA
IOH = -5mA
2.4
VOH
VDD-0.4
MDS 9112-18 G
3
Revision 121302
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS9112-18
ZERO DELAY, LOW SKEW BUFFER
Parameter
Symbol
Conditions
No Load
Min.
Typ.
Max.
Units
Operating Supply Current
IDD
44
mA
S1=S2=1
Short Circuit Current
IOS
Each output
S1, S1, FBIN
± 65
7
mA
pF
Input Capacitance
CIN
AC Electrical Characteristics
VDD = 3.3V ±10%, Ambient Temperature 0 to +70° C
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ. Max. Units
FBIN to CLKA1
S1=S2=1
20
160
MHz
Output Frequency
FBIN to CLKA1
S1=S2=1
20
160
MHz
Output Rise Time
tOR
tOF
0.8 to 2.0 V, CL=30pF
0.8 to 2.0 V, CL=30pF
at 1.4V
1.5
1.5
60
ns
ns
%
Output Fall Time
Output Clock Duty Cycle
40
50
Device to Device skew, equally
loaded
rising edges at VDD/2
700
ps
Output to Output skew, equally
loaded
rising edges at VDD/2
250
400
ps
Maximum Absolute Jitter
Cycle to Cycle Jitter
300
ps
ps
30pF loads
66.67 MHz outputs
Thermal Characteristics
Parameter
Symbol
θJA
Conditions
Still air
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
120
115
105
58
°C/W
°C/W
°C/W
°C/W
θJA
θJA
θJC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
MDS 9112-18 G
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Revision 121302
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS9112-18
ZERO DELAY, LOW SKEW BUFFER
Package Outline and Package Dimensions (16 pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
Min Max
Symbol
Min
Max
1.75
0.24
0.51
0.24
Index
Area
A
A1
B
C
D
E
e
1.35
.010
0.33
0.19
9.80
3.80
0.0532 0.0688
0.0040 0.0098
E
H
0.013
0.020
0.0075 0.0098
10.00 0.3859 0.3937
4.00
0.1497 0.1574
0.050 Basic
1.27 Basic
H
h
L
5.80
0.25
0.41
0°
6.20
0.50
1.27
8°
0.2284 0.2440
0.0099 0.0195
Pin 1
D
0.016
0.050
a
0°
8°
A
a
c
e
b
L
Ordering Information
Part / Order Number
Marking
Shipping
Package
Temperature
packaging
ICS9112BM-18
9112BM-18
9112BM-18
Tubes
16 pin SOIC
16 pin SOIC
0 to 70° C
0 to 70° C
IICS9112BM-18T
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those
requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant
any ICS product for use in life support devices or critical medical instruments.
MDS 9112-18 G
5
Revision 121302
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
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