ICS9148F-37LF-T [IDT]
Clock Generator, PDSO48;
| 型号： | ICS9148F-37LF-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO48 光电二极管 |
| 文件： | 总16页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9148-37
Integrated
Circuit
Systems, Inc.
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
Features
•
Generates the following system clocks:
The ICS9148-37 is the single chip clock solution for
Desktop/Notebook designs using the VIA MVP3 style
chipset. It provides all necessary clock signals for such a
system.
- 4 CPU(2.5V/3.3V) upto 100MHz.
- 6 PCI(3.3V) @ 33.3MHz
- 2AGP(3.3V) @ 2 x PCI
- 12 SDRAMs(3.3V) @ either CPU or AGP
- 2 REF (3.3V) @ 14.318MHz
SpreadspectrummaybeenabledthroughI2Cprogramming.
Spread spectrum typically reduces system EMI by 8dB to
10dB.ThissimplifiesEMIqualificationwithoutresortingto
board design iterations or costly shielding.The ICS9148-
37 employsaproprietaryclosedloopdesign, whichtightly
controls the percentage of spreading over process and
temperaturevariations.
•
Skew characteristics:
- CPU – CPU<250ps
- SDRAM – SDRAM < 250ps
- CPU – SDRAM < 250ps
- CPU–AGP: < 1ns
- CPU(early) – PCI : 1-4ns
•
•
Supports Spread Spectrum modulation +0.25, ±0.6%
Serial I2C interface for Power Management,
Frequency Select, Spread Spectrum.
SerialprogrammingI2Cinterfaceallowschangingfunctions,
stop clock programming and frequency selection. The
SD_SEL latched input allows the SDRAM frequency to
follow the CPUCLK frequency(SD_SEL=1) or the AGP
clock frequency(SD_SEL=0)
•
Efficient Power management scheme through PCI and
CPU STOP CLOCKS.
•
•
Uses external 14.318MHz crystal
48 pin 300mil SSOP.
Block Diagram
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
VDD4 = AGP (0:1)
VDDL = CPUCLK (0:3)
0143G—08/04/04
ICS9148-37
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDD1
REF0
PWR Ref (0:2), XTAL power supply, nominal 3.3V
OUT 14.318 MHz reference clock.
2
Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU,
CPU3.3#_2.51,2
IN
LOW=3.3V CPU1. Latched input2
3,9,16,22,27,
33,39,45
GND
X1
PWR Ground
Crystal input, has internal load cap (33pF) and feedback
4
IN
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
5
X2
OUT
6,14
VDD2
PCICLK_F
PWR Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns
skew (CPU early) This is not affected by PCI_STOP#
OUT
7
8
Frequency select pin. Latched Input. Along with other FS pins
determines the CPU, SDRAM, PCI & AGP frequencies.
FS11, 2
IN
PCICLK0
FS21, 2
OUT
IN
PCI clock output. Synchronous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input Along with other FS pins
determines the CPU, SDRAM, PCI & AGP frequencies.
PCI clock outputs. Synchronous CPUCLKs with 1-4ns skew (CPU
early)
10, 11, 12, 13
15, 47
PCICLK(1:4)
AGP (0:1)
OUT
OUT
Advanced Graphic Port outputs, powered by VDD4.
This asynchronous input halts CPUCLK (0:3) and AGP (0:1) clocks at
logic 0 level, when input low (in Mobile Mode, MODE=0)
CPU_STOP#1
IN
SDRAM clock output. Frequency is selected by the SD_SEL latched
input. SD_SEL = 1 at power on causes SDRAM frequency = CPU
frequency SD_SEL = 0 at power on causes SDRAM frequency = AGP
frequency
This asynchronous input halts PCICLK(0:5) clocks at logic 0 level,
when input low (In mobile mode, MODE=0)
SDRAM clock output. Frequency is selected by the SD_SEL latched
input. SD_SEL = 1 at power on causes SDRAM frequency = CPU
frenquency SD_SEL = 0 at power on causes SDRAM frequency =
AGP frequency
17
18
SDRAM 11
PCI_STOP#1
SDRAM 10
OUT
IN
OUT
SDRAM clock outputs. Frequency is selected by the SD_SEL latched
input. SD_SEL = 1 at power on causes SDRAM frequency = CPU
frequency SD_SEL = 0 at power on causes SDRAM frequencies =
AGP frequency
20, 21,28, 29, 31,
32, 34, 35,37,38
SDRAM (0:9)
VDD3
OUT
Supply for SDRAM (0:11), CPU Core and 24, 48MHz clocks,
nominal 3.3V.
19,30,36
PWR
23
24
SDATA
SCLK
IN
IN
Data input for I2C serial input.
Clock input of I2C input
24MHz
OUT
24MHz output clock, for Super I/O timing.
25
26
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock, for USB timing.
Frequency select pin. Latched Input Along with other FS pins
determines the CPU, SDRAM, PCI & AGP frequencies.
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
MODE1, 2
48MHz
FS01, 2
IN
OUT
IN
40, 41, 43, 44
42
CPUCLK(0:3)
VDDL
REF1
OUT
PWR Supply for CPU (0:3), either 2.5V or 3.3V nominal
OUT 14.318MHz reference clock.
46
48
Latched input at Power On selects either CPU (SDSEL=1) or AGP
(SD_SEL=0) frequencies for the SDRAM clock outputs.
PWR Supply for AGP (0:1)
SD_SEL
VDD4
IN
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0143G—08/04/04
2
ICS9148-37
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
Pin 17
Pin 18
CPU_STOP#
(INPUT)
PCI_STOP#
(INPUT)
0
SDRAM 11
(OUTPUT)
SDRAM 10
(OUTPUT)
1
Power Management Functionality
PCICLK_F,
REF,
24/48MHz
and SDRAM
AGP,
CPUCLK
Outputs
Crystal
OSC
CPU_STOP# PCI_STOP#
PCICLK (0:5)
VCO
0
1
1
1
1
0
Stopped Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Buffer Selected
Input level
for operation at:
(Latched Data)
1
0
2.5V VDD
3.3V VDD
Functionality
VDD1, 2, 3, 4 = 3.3V±5%, VDDL = 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C
Crystal (X1, X2) = 14.31818MHz
SDRAM (MHz)
CPU
(MHz)
100
95.25
83.3
75
FS2
FS1
FS0
PCI (MHz)
AGP (MHz)
SD_SEL=1
SD_SEL=0
66.6
63.5
66.6
60
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
100
95.25
83.3
75
33.3
31.75
33.3
30
37.5
34.25
33.4
30
66.6
63.5
66.6
60
75
75
75
75
68.5
66.8
60
68.5
66.8
60
68.5
66.8
60
68.5
66.8
60
0143G—08/04/04
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ICS9148-37
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controler (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component.It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0143G—08/04/04
4
ICS9148-37
Serial Configuration Command Bitmap
Byte0:FunctionalityandFrequencySelectRegister
(default = 0)
Bit
Description
0 - ±0.25% Spread Spectrum Modulation
1 - ±0.6% Spread Spectrum Modulation
PWD
0
Bit 7
Bit6 Bit5
Bit4
111
CPU Clock
PCI
AGP
100
95.25
83.3
75
33.3
31.75
33.3
30
37.5
34.25
33.4
30
66.6
63.5
66.6
60
110
Bit
6:4
101
Note
1
100
011
75
75
010
68.5
66.8
60
68.5
66.8
60
001
000
0 - Frequency is selected by hardware
select,
Bit 3
0
Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
0 - Spread Spectrum center spread type.
0
0
0
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Bit 1
Bit 0
Byte 1: CPU, Active/Inactive
Register (1 = enable, 0 = disable)
Byte 2: PCI Active/Inactive
Register (1 = enable, 0 = disable)
Bit
Pin # PWD
Description
(Reserved)
PCICLK_F (Act/Inact)
AGP0 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Bit
Pin #
-
-
-
-
40
41
43
44
PWD
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
7
15
13
12
11
10
8
Notes:
Notes:
1. InactivemeansoutputsareheldLOWandaredisabled
from switching.
1. InactivemeansoutputsareheldLOWandaredisabled
from switching.
0143G—08/04/04
5
ICS9148-37
Byte4:SDRAM Active/InactiveRegister
(1 = enable, 0 = disable)
Byte3:SDRAMActive/InactiveRegister
(1 = enable, 0 = disable)
Bit
Pin #
PWD
Description
Bit
Pin #
28
29
31
32
34
35
37
38
PWD
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
-
-
-
-
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 3
Bit 2
17
18
1
1
Bit 1
Bit 0
20
21
1
1
Notes:
1. InactivemeansoutputsareheldLOWandaredisabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are
disabled from switching.
Byte 5: Peripheral Active/Inactive
Register (1 = enable, 0 = disable)
Bit
Pin #
-
-
-
47
-
-
46
2
PWD
Description
(Reserved)
(Reserved)
(Reserved)
AGP1(Act/Inact)
(Reserved)
(Reserved)
REF1 (Act/Inact)
REF0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Notes:
1. InactivemeansoutputsareheldLOWandaredisabled
from switching.
0143G—08/04/04
6
ICS9148-37
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation.CPU_STOP#issynchronizedbytheICS9148-37.TheminimumthattheCPUclockisenabled(CPU_STOP#
high pulse) is 100 CPU clocks.All other clocks will continue to run while the CPU clocks are disabled.The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS9148-37.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
0143G—08/04/04
7
ICS9148-37
PCI_STOP#Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-37. It is used to turn off the PCICLK (0:5) clocks for low power
operation.PCI_STOP# is synchronized by the ICS9148-37 internally.The minimum that the PCICLK (0:5) clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state
and started with a full high pulse width guaranteed.PCICLK (0:5) clock on latency cycles are only one rising PCICLK
clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
0143G—08/04/04
8
ICS9148-37
Shared Pin Operation -
Input/Output Pins
solderspottabsoraphysicaljumperheadermaybeused.
These figures illustrate the optimal PCB physical layout
options.These configuration resistors are of such a large
ohmic value that they do not effect the low impedance
clock signals.The layouts have been optimized to provide
as little impedance transition to the clock signal as
possible, as it passes through the programming resistor
pad(s).
Pins 2, 7, 8, 25, 26 and 46 on the ICS9148-37 serve as
dual signal functions to the device. During initial power-
up, they act as input pins.The logic level (voltage) that is
present on these pins at this time is read and stored into
a 4-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm(10K) resistor is used to provide
boththesolidCMOSprogrammingvoltageneededduring
the power-up programming period and to provide an
insignificantloadontheoutputclockduringthesubsequent
operatingperiod.
Figs. 1 and 2 show the recommended means of
implementing this function. In Fig. 1 either one of the
resistors is loaded onto the board (selective stuffing) to
configure the device’s internal logic. Figs. 2a and b
provide a single resistor loading option where either
Fig. 1
0143G—08/04/04
9
ICS9148-37
Fig. 2a
Fig. 2b
0143G—08/04/04
10
ICS9148-37
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
CaseTemperature . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD + 0.3
0.8
UNITS
V
VIL
VSS - 0.3
V
IIH
VIN = VDD
0.1
2.0
5
mA
mA
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
-100
100
IDD3.3OP CL = 0 pF; 66.8 MHz
160
Supply Current
Input frequency
Input Capacitance1
Fi
CIN
VDD = 3.3 V;
14.318
36
MHz
pF
Logic Inputs
5
45
2
CINX
Ttrans
Ts
X1 & X2 pins
27
pF
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
ps
TSTAB
2
500
4
TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads
TCPU-PCI1 VT = 1.5 V; CPU Leads
TCPU-AGP VT = 1.5 V; CPU Leads
-500
1
200
2.8
0
Skew1
ns
-1
1
ns
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
CL = 0 pF; 66.8 MHz
MIN
TYP
10
MAX
20
UNITS
mA
Operating
IDD2.5OP
Supply Current
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Lead -500
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
200
2.7
500
4
ps
ns
Skew1
1
1Guaranteed by design, not 100% tested in production.
0143G—08/04/04
11
ICS9148-37
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
2
TYP
2.2
0.3
-20
26
MAX
UNITS
V
Output High Voltage VOH2B IOH = -8 mA
Output Low Voltage VOL2B
Output High Current IOH2B
I
OL = 12 mA
0.4
-16
V
V
OH = 1.7 V
OL = 0.7 V
mA
mA
ns
Output Low Current
Rise Time
IOL2B
tr2B1
tf2B1
dt2B1
tsk2B1
V
19
40
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.5
1.6
47
1.8
1.8
55
Fall Time
ns
Duty Cycle
%
Skew
VT = 1.25 V
60
250
ps
Jitter, Single Edge
Displacement2
Jitter, One Sigma
Jitter, Absolute
tjsed2B1
VT = 1.25 V
200
250
ps
tj1s2B1
tjabs2B1
VT = 1.25 V
VT = 1.25 V
65
150
300
ps
ps
-300
160
1 Guaranteed by design, not 100% tested in production.
2 Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
2.5
TYP
2.6
0.35
-29
37
MAX
UNITS
V
VOH2A IOH = -28 mA
VOL2A IOL = 27 mA
0.4
-23
V
IOH2A
IOL2A
VOH = 2.0 V
mA
mA
ns
VOL = 0.8 V
33
45
1
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.75
1.1
50
2
1
Fall Time
tf2A
2
ns
1
Duty Cycle
dt2A
55
%
1
Skew
tsk2A
VT = 1.5 V
50
250
150
250
ps
1
Jitter, One Sigma
Jitter, Absolute
tj1s2A
VT = 1.5 V
65
ps
1
tjabs2A
VT = 1.5 V
-250
165
ps
1Guaranteed by design, not 100% tested in production.
0143G—08/04/04
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ICS9148-37
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
3
MAX
UNITS
V
IOL = 23 mA
0.2
-60
50
0.4
-40
V
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
41
45
Tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.75
1.5
50
2
2
Fall Time1
Duty Cycle1
Tf1
ns
Dt1
55
%
Skew1
Tsk1
VT = 1.5 V
200
50
500
150
+250
400
ps
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Absolute1
Tj1s1
Tjabs1
Tjabs1
VT = 1.5 V
ps
VT = 1.5 V (with synchronous PCI)
VT = 1.5 V (with asynchronous PCI)
-250
-400
ps
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
3
MAX
UNITS
V
V
VOL1
IOL = 23 mA
0.2
-60
50
0.4
-40
IOH1
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
41
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.8
1.6
51
2
2
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
55
250
%
1
Skew
tsk1
VT = 1.5 V
130
ps
Jitter, One Sigma1
tj1s1a
tj1s1b
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
40
150
250
ps
ps
200
Jitter, Absolute1
tabs1a VT = 1.5 V, synchronous
tjabs1b VT = 1.5 V, asynchronous
-250
-650
135
500
250
650
ps
ps
1Guaranteed by design, not 100% tested in production.
0143G—08/04/04
13
ICS9148-37
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
3
MAX
UNITS
V
VOL1
IOL = 23 mA
0.2
-60
50
1.1
1
0.4
-40
V
IOH1
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
41
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.4 V
2
2
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
49
130
2
55
250
3
%
1
Skew
tsk1
VT = 1.5 V
ps
Jitter, One Sigma1
Jitter, Absolute1
tj1s1
VT = 1.5 V
%
tabs1a
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
-5
-6
2.5
4.5
5
%
tjabs1b
6
%
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz, REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH5
CONDITIONS
IOH = -16 mA
MIN
2.4
TYP
MAX
UNITS
2.6
0.3
-32
25
2
V
V
VOL5
IOL = 9 mA
0.4
-22
IOH5
VOH = 2.0 V
mA
mA
ns
ns
%
IOL5
VOL = 0.8 V
16
1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4
4
1
Fall Time
tf5
1.9
54
1
1
Duty Cycle
dt5
45
-5
57
3
1
Jitter, One Sigma
Jitter, Absolute
tj1s5
VT = 1.5 V
%
1
tjabs5
VT = 1.5 V
-
5
%
1Guaranteed by design, not 100% tested in production.
0143G—08/04/04
14
ICS9148-37
GeneralLayoutPrecautions:
1) Use a ground plane on the top
layer of the PCB in all areas not
used by traces.
2)Makeallpowertracesandviasas
wide as possible to lower
inductance.
Notes:
1) All clock outputs should have
series terminating resistor. Not
shown in all places to improve
readibility of diagram.
2) 47 ohm / 56pf RC termination
shouldbeusedonallover50MHz
outputs.
3) Optional crystal load capacitors
are recommended.
ConnectionstoVDD:
0143G—08/04/04
15
ICS9148-37
300 mil SSOP
In Millimeters
COMMON DIMENSIONS
c
N
In Inches
COMMON DIMENSIONS
SYMBOL
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
h
L
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
0.635 BASIC
0.025 BASIC
α
h x 45°
0.38
0.50
0.64
1.02
.015
.020
.025
.040
D
N
a
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
D mm.
D (inch)
N
A1
MIN
15.75
MAX
16.00
MIN
.620
MAX
.630
- CC -
48
e
SEATING
PLANE
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
b
.10 (.004)
C
Ordering Information
ICS9148yF-37 LF-T
Example:
ICS XXXX y F PPP LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0143G—08/04/04
16
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