ICS9248YF-135-T [IDT]
Processor Specific Clock Generator, 150MHz, PDSO48, 0.300 INCH, SSOP-48;
| 型号： | ICS9248YF-135-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 150MHz, PDSO48, 0.300 INCH, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总15页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-135
Frequency Generator & Integrated Buffers for Celeron & PII/III™& K6
Recommended Application:
Motherboard Single chip clock solution for SIS540,
SIS630 Pentium II/III and K6 chipsets.
Pin Configuration
VDDREF
*1REF0/FS3
GNDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1
VDDLCPU
CPUCLK_F
CPUCLK1
GNDL
CPUCLK2
VDD
SDRAM_F1
SDRAM_F0
GND
SDRAM7
SDRAM6
VDD
SDRAM5
SDRAM4
GND
SDRAM3
SDRAM2
VDD
Output Features:
X2
•
•
3- CPUs @ 2.5/3.3V, up to 166MHz.
VDDPCI
*PCICLK_F/FS1
*PCICLK1/FS2
PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VDD
10 - SDRAM @ 3.3V, up to 166MHz
including 2 SDRAM_F's
•
•
•
7- PCI @3.3V,
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz).
GND
SDRAM_STOP#
**PD#
•
2- REF @3.3V, 14.318MHz.
VDD
Features:
CPU_STOP#
PCI_STOP#
GND
SDRAM1
SDRAM0
VDD
•
•
•
Up to 166MHz frequency support
Support FS0-FS3 trapping status bit for I2C read back.
SDATA
SCLK
48MHz/FS0*1
24_48MHz/CPU2.5_3.3#*
Support power management: CPU, PCI, SDRAM stop
and Power down Mode form I2C programming.
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
** These inputs have a 120K pullup to VDD.
1 These are double strength.
•
•
Spread spectrum for EMI control (0 to -0.5%, 0.25%).
FS0, FS1, FS3 must have a internal 120K pull-Down
to GND.
•
Uses external 14.318MHz crystal
Skew Specifications:
•
•
•
•
•
CPU - CPU: < 175ps
SDRAM - SDRAM < 250ps
PCI - PCI: < 500ps
CPU - SDRAM: < 500ps
CPU (early) - PCI: 1-4ns (typ. 2ns)
Functionality
Block Diagram
CPU
(MHz)
66.6
100.0
150.0
133.3
66.8
100.0
100.0
133.3
66.8
97.0
70.0
95.0
95.0
112.0
97.0
96.2
SDRAM PCICLK
FS3 FS2 FS1 FS0
(MHz)
100.0
100.0
100.0
100.0
133.6
133.3
150.0
133.3
66.8
(MHz)
33.3
33.3
37.5
33.3
33.4
33.3
37.5
33.3
33.4
32.3
35.0
31.7
31.7
37.3
32.2
32.1
PLL2
48MHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
24_48MHz
/ 2
X1
X2
XTAL
OSC
REF[1:0]
2
2
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
CPUCLK [2:1]
CPUCLK_F
SDRAM
DIVDER
Stop
Stop
SDRAM [7:0]
8
CPU2.5_3.3#
97.0
105.0
95.0
SDRAM_F [1:0]
2
6
Control
Logic
SDATA
SCLK
PCI
DIVDER
PCICLK [6:1]
PCICLK_F
FS[3:0]
126.7
112.0
129.3
96.2
PD#
PCI_STOP#
Config.
Reg.
CPU_STOP#
SDRAM_STOP#
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-135 Rev A 1/16/01
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9248-135
General Description
The ICS9248-135 is the single chip clock solution for Desktop/Notebook designs using the SIS 540/630 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-135
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 6, 15, 19, 27,
30, 36, 42
3.3V Power supply for SDRAM output buffers, PCI output buffers, reference
output buffers and 48MHz output
VDD
PWR
REF0
FS3
OUT
IN
14.318 MHz reference clock.
2
Frequency select pin.
3, 10, 16, 22, 33,
GND
PWR
Ground pin for 3V outputs.
39, 44
4
5
X1
X2
IN
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
OUT
IN
FS1
7
PCICLK_F
FS2
OUT
IN
Free running PCICLK clock output. Not affected by PCI_STOP#
Frequency select pin.
8
14, 13, 12, 11, 9
17
PCICLK1
PCICLK (6:2)
OUT
OUT
PCI clock outputs.
PCI clock outputs.
SDRAM_STOP#
IN
Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level, when input low
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Stops all CPUCLKs clocks at logic 0 level, when input low
18
PD#
IN
20
21
CPU_STOP#
PCI_STOP#
IN
IN
Stops all PCICLKs clocks at logic 0 level, when input low
38, 37, 35, 34,
32, 31, 29, 28
23
SDRAM (7:0)
SDATA
OUT
SDRAM clock outputs
Data input for I2C serial input, 5V tolerant input
IN
Clock input of I2C input, 5V tolerant input
Voltage select 2.5V when high - 3.3V when low
Clock output for super I/O/USB default is 24MHz
Frequency select pin.
24
SCLK
CPU2.5_3.3#
24_48MHz
FS0
IN
IN
25
OUT
IN
26
48MHz
OUT
OUT
OUT
OUT
PWR
OUT
48MHz output clock
41, 40
45, 43
46
SDRAM_F (1:0)
CPUCLK (1:2)
CPUCLK_F
VDDLCPU
REF1
Free running SDRAM clock outputs. Not affected by SDRAM_STOP#
CPU clock outputs.
Free running CPUCLK clock output. Not affected by CPU_STOP#
Power pin for the CPUCLKs. 2.5V
47
48
14.318 MHz reference clock.
Third party brands and names are the property of their respective owners.
2
ICS9248-135
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
3
ICS9248-135
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
CPU
PWD
Bit7 Bit2 Bit6 Bit5 Bit4
SDRAM
100.0
100.0
100.0
100.0
133.6
133.3
150.0
133.3
66.8
PCI
33.3
33.3
37.5
33.3
33.4
33.3
37.5
33.3
33.4
32.3
35.0
31.7
31.7
37.3
32.3
32.1
33.4
33.4
27.7
33.4
37.5
31.3
35.0
33.4
36.8
38.3
30.0
34.5
35.0
36.3
36.9
26.7
SS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.6
100.0
150.0
133.3
66.8
0 to-0.5%
0 to-0.5%
0.25%
0 to-0.5%
0 to-0.5%
0 to-0.5%
0.25%
100.0
100.0
133.3
66.8
0 to-0.5%
0.25%
97.0
97.0
0 to-0.5%
0.25%
70.0
105.0
95.0
95.0
0.25%
95.0
126.7
112.0
129.3
96.2
0.25%
112.0
97.0
0.25%
00010
Note1
0 to-0.5%
0 to-0.5%
0.25%
96.2
Bit 7, 2,
Bit 6:4
66.8
100.2
100.2
110.7
133.6
100.0
125.0
140.0
133.6
147.0
153.3
120.0
138.0
140.0
145.0
147.5
160.0
100.2
166.0
100.2
75.0
0.25%
0.25%
0.25%
0.25%
83.3
0.25%
105.0
133.6
110.3
115.0
120.0
138.0
140.0
145.0
147.5
160.0
0.25%
0.25%
0.25%
0.25%
0.25%
0.25%
0.25%
0.25%
0.25%
0.25%
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 7, 2, 6:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
Bit 3
Bit 1
Bit 0
0
1
0
1- Tristate all outputs
Note: PWD = Power-Up Default
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I2C readback for Bits 7, 2, 6:4 indicate the revision code.
I2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
4
ICS9248-135
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
(CPU2.5_3.3#)
BIT PIN# PWD
DESCRIPTION
SEL24_48#
(48MHz when set to 0)
(24MHz when set to 1)
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Bit 7
-
1
14
13
12
11
9
PCICLK6 (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK_F (Act/Inact)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
Reserved
-
Reserved
43
45
46
-
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Reserved
8
7
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
25
26
41
40
38
37
35
34
1
1
1
1
1
1
1
1
24_48MHz
48MHz
32
31
29
28
-
1
1
1
1
1
1
1
1
SDRAM_F1
SDRAM_F0
SDRAM7
SDRAM6
SDRAM5
SDRAM4
-
Reserved
-
Reserved
-
Reserved
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved (Note)
BIT PIN# PWD
DESCRIPTION
Reserved
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved
FS3#
-
-
FS2#
-
FS1#
-
FS0#
48
2
REF1 (Act/Inact)
REF0 (Act/Inact)
Note: Don’t write into this register, writing into this register
can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
5
ICS9248-135
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. When no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, then
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used both to provide the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
6
ICS9248-135
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-135. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is
less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-135.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
Third party brands and names are the property of their respective owners.
7
ICS9248-135
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the
clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to
a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power
down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
SDRAM
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-135 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
8
ICS9248-135
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-135. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-135 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-135 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-135.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
9
ICS9248-135
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power operation.
SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-135. All other clocks will continue to run
while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner
that guarantees the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to the
SDRAM clocks inside the ICS9248-135.
3. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
10
ICS9248-135
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
0.8
V
V
VIL
VSS-0.3
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
IDD3.3OP133 CL = 0 pF; Select @ 133MHz
148
150
180
mA
mA
mA
MHz
pF
Supply Current
180
161
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
11
27
14.318
16
5
CIN
Logic Inputs
CINX
Ttrans
TSTAB
tCPU-PCI
X1 & X2 pins
36
45
3
pF
Transition Time1
Clk Stabilization1
To 1st crossing of target Freq.
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V
ms
3
ms
1
2.39
4
ns
Skew
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
6.13
9.22
11.6
273
MAX UNITS
IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz
IDD2.5OP100 CL = 0 pF; Select @ 100 MHz
IDD2.5OP133 CL = 0 pF; Select @ 133 MHz
tCPU-SDRAM VT = 1.5 V; VTL = 1.25 V
30
mA
mA
mA
ps
Operating Supply
Current
500
4
Skew1
tCPU-PCI
VT = 1.5 V; VTL = 1.25 V
1
2.25
ns
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
ICS9248-135
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP
36.5
29
MAX UNITS
1
RDSP2A
VO=VDD*(0.5)
VO=VDD*(0.5)
IOH = -20.0 mA
IOL = 12 mA
40
Ω
1
RDSN2A
10
40
Ω
VOH1a
VOL1a
IOH1a
IOL1a
2
2.85
0.31
-45
V
0.4
-19
V
mA
mA
ns
VOH = 2 V
VOL = 0.8 V
22
0.4
0.4
45
29
1
tr1a
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.24
1.6
2
2
1
Fall Time
tf1a
ns
1
Duty Cycle
dt1a
52.6
80.8
128
62
175
250
%
1
Skew
tsk1a
VT = 1.5 V
VT = 1.5 V
ps
1
tjcyc-cyc1a
Jitter, Cycle-to-cycle
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP
36.5
29
MAX UNITS
1
RDSP2A
VO=VDD*(0.5)
VO=VDD*(0.5)
IOH = -12.0 mA
IOL = 12 mA
40
Ω
1
RDSN2A
10
40
Ω
VOH1B
VOL1B
IOH1B
IOL1B
2
2.3
V
0.31
-39
0.4
-21
V
mA
mA
ns
VOH = 1.7 V
VOL = 0.7 V
19
45
26
1
tr1B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.5 V
1.03
1.26
51.7
66.1
170
124.5
1.6
1.6
55
1
Fall Time
tf1B
ns
1
Duty Cycle
dt1a
%
1
Skew
tsk1a
VT = 1.5 V
175
250
350
ps
1
Jitter, Cycle-to-cycle
tjcyc-cyc1B
tjcyc-cyc1B
VT = 1.25 V CPU, SDRAM Synchronous
VT = 1.25 V CPU, SDRAM Asynchronous
ps
1
ps
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
ICS9248-135
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
21
MAX UNITS
1
Output Impedance
RDSP1
VO=VDD*(0.5)
55
55
Ω
Ω
V
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSP1
VO=VDD*(0.5)
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
21
3.3
0.17
-62
43
VOH2
VOL2
IOH2
IOL2
2.4
0.4
-33
V
mA
mA
38
tr2
tf2
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.62
1.81
49.8
2.2
2.2
55
ns
ns
%
Fall Time1
Duty Cycle1
dt2
45
Skew1
tsk2
tjcyc2
VT = 1.5 V
VT = 1.5 V
200
306
500
350
ps
ps
Jitter, Cycle-to-cycle
-350
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
1
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
RDSP2A
VO=VDD*(0.5)
VO=VDD*(0.5)
IOH = -25 mA
IOL = 20 mA
VOH = 2.0 V
VOL = 0.8 V
10
10
17
18
20
Ω
1
RDSN2A
20
Ω
VOH3
VOL3
IOH3
IOL3
2.4
2.9
V
0.32
-73
50
0.4
-40
V
mA
mA
ns
41
0.4
0.4
47
1
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.14
1.38
51.8
2
2
1
Fall Time
Tf3
ns
1
Duty Cycle
Dt3
57
%
Skew1
Tsk1
VT = 1.5 V
155.5
250
ps
(0-1,2,4,5,7,10,11)
Skew1
Jitter, Cycle-to-cycle
Tsk1
tjcyc
VT = 1.5 V
VT = 1.5 V
298.5
369.17
500
650
ps
ps
(0-6,6,8,9,12,13)
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
13
ICS9248-135
Electrical Characteristics - 48MHz, REF_0
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
21
MAX UNITS
1
Output Impedance
RDSP1
VO=VDD*(0.5)
55
55
Ω
Ω
V
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1 48MHz
Fall Time1 48MHz
Duty Cycle1 48MHz
Rise Time1 REF_0
Fall Time1 REF_0
RDSP1
VO=VDD*(0.5)
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
21
3.3
0.17
-62
57
VOH2
VOL2
IOH2
IOL2
2.4
0.4
-22
V
mA
mA
16
45
tr2
tf2
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.78
1.92
52
2
2
ns
ns
%
ns
ns
dt2
tr2
tf2
55
2
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.32
1.56
2
Duty Cycle1 REF_0
Jitter, 48MHz
Jitter, REF_0
dt2
tjcyc2
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
45
52.2
500.6
1243
55
%
ps
ps
700
tjcyc2
-350
1500
Electrical Characteristics - REF_1;24/48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF
PARAMETER
SYMBOL
CONDITIONS
VO=VDD*(0.5) Output P
MIN
TYP
MAX UNITS
1
Output Impedance
Output Impedance
RDSP5
20
20
42
43
60
60
Ω
Ω
RDSN5
1
VO=VDD*(0.5) Output N
IOH = -14 mA
IOL = 6mA
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1 24_48MHz
Fall Time1 24_48MHz
Duty Cycle1 24_48MHz
Rise Time1 REF_1
VOH4
VOL4
IOH4
IOL4
2.4
2.6
0.3
-26
22
V
0.4
-22
V
VOH = 2.0 V
mA
mA
VOL = 0.8 V
16
45
tr4
tf4
dt4
tr4
tf4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.75
1.88
52
4
4
ns
ns
%
ns
ns
55
4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
2.22
2.43
Fall Time1 REF_1
4
Duty Cycle1 REF_1
Jitter, 24_48MHz
Jitter, REF_1
dt4
tjcyc4
VT = 1.5 V
VT = 1.5 V
45
-1
51.1
727
55
%
ps
ns
1000
1500
tjcyc4
VT = 1.5 V
1208
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
14
ICS9248-135
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
A1
b
2.413
0.203
0.203
0.127
2.794
0.406
0.343
0.254
.095
.008
.008
.005
.110
.016
.0135
.010
c
SEE VARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.620
MAX
.630
48
15.748
16.002
JEDEC MO-118
6/1/00
DOC# 10-0034
REV B
Ordering Information
ICS9248yF-135-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
15
information being relied upon by the customer is current and accurate.
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