IDT74ALVCH16600PV8 [IDT]

Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56;


型号：	IDT74ALVCH16600PV8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56 光电二极管
文件：	总7页 (文件大小：74K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74ALVCH16600

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

IDT74ALVCH16600

3.3V CMOS 18-BIT UNIVERSAL

BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

AND BUS-HOLD

FEATURES:

DESCRIPTION:

• 0.5 MICRON CMOS Technology

This 18-bit universal bus transceiver is built using advanced dual metal

CMOS technology. The transceiver combines D-type latches and D-type flip-

flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB and

OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA)

inputs. The clock can be controlled by the clock-enable (CLKENAB and

CLKENBA) inputs. ForA-to-B data flow, the device operates in the transpar-

ent mode when LEAB is high. When LEAB is low, theAdata is latched if CLKAB

is held at a high or low logic level. If LEAB is low, theA data is stored in the

latch/flip-flop on the high-to-low transition of CLKAB . Output enable OEAB is

active low. When OEAB is low, the outputs are active. When OEAB is high, the

outputs are in the high-impedance state.

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• VCC = 2.5V ± 0.2V

• CMOS power levels (0.4µ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in SSOP, TSSOP, and TVSOP packages

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Suitable for heavy loads

Data flow for B toAis similar to that ofAto B but uses OEBA, LEBA, CLKBA

and CLKENBA.

The ALVCH16600 has been designed with a ±24mA output driver. This

driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed

performance.

The ALVCH16600 has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputsand

eliminatestheneedforpull-up/downresistors.

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

FUNCTIONALBLOCKDIAGRAM

OEAB

CLKENAB

CLKAB

LEAB

LEBA

CLKBA

CLKENBA

OEBA

CLK

TO 17 OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

APRIL 1999

DSC-4548/1

IDT74ALVCH16600

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

Description

Max

Unit

(2)

VTERM

Terminal Voltage with Respect to GND

–0.5 to +4.6

CLKENAB

OEAB

LEAB

(3)

VTERM

Terminal Voltage with Respect to GND –0.5 to VCC+0.5

CLKAB

TSTG

IOUT

IIK

Storage Temperature

DC Output Current

–65 to +150

–50 to +50

±50

°C

Continuous Clamp Current,

VI < 0 or VI > VCC

GND

IOK

Continuous Clamp Current, VO < 0

–50

ICC

ISS

Continuous Current through each

VCC or GND

±100

VCC

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

GND

2. V^CCterminals.

3. All terminals except V^CC.

A10

A11

A12

B10

B11

B12

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

GND

A13

GND

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

COUT

CI/O

B13

B14

B15

A14

NOTE:

A15

1. As applicable to the device type.

VCC

A16

A17

VCC

B16

B17

GND

A18

GND

B18

PINDESCRIPTION

CLKBA

OEBA

LEBA

Pin Names

OEAB

OEBA

LEAB

LEBA

CLKAB

CLKBA

Description

CLKENBA

A-to-B Output Enable Input (Active LOW)

B-to-A Output Enable Input (Active LOW)

A-to-B Latch Enable Input

SSOP/ TSSOP/ TVSOP

TOP VIEW

B-to-A Latch Enable Input

A-to-B Clock Input

B-to-A Clock Input

A-to-B Data Inputs or B-to-A 3-State Outputs⁽¹⁾

B-to-A Data Inputs or A-to-B 3-State Outputs⁽¹⁾

CLKENAB A-to-B Clock Enable Input (Active LOW)

CLKENBA B-to-A Clock Enable Input (Active LOW)

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

IDT74ALVCH16600

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

FUNCTIONTABLE^(1,2)

Inputs

Output

CLKENAB

OEAB

LEAB

CLKAB

B⁽³⁾

↓

B⁽³⁾

L or H

NOTES:

1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and

CLKBA, and CLKENBA.

2. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High-Impedance

↓ = HIGH-to-LOW transition

3. Level of B before the indicated steady-state inputs were established.

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

Input HIGH Current

VCC = 3.6V

VI = VCC

—

±5

µA

Input LOW Current

VI = GND

VO = VCC

VO = GND

IOZH

IOZL

VIK

High Impedance Output Current

(3-State Output pins)

—

±10

–1.2

—

Clamp Diode Voltage

VCC = 2.3V, IIN = –18mA

VCC = 3.3V

–0.7

Input Hysteresis

—

100

0.1

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VCC = 3.6V

VIN = GND or VCC

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

—

750

µA

NOTE:

1. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74ALVCH16600

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µA

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-Hold Input Overdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

–45

—

µA

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

VCC = 2.3V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC – 0.2

1.7

2.2

2.4

—

VCC = 2.3V

—

VCC = 2.7V

—

VCC = 3V

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

IOL = 12mA

IOL = 24mA

VCC = 2.7V

VCC = 3V

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, TA = 25°C

VCC = 2.5V ± 0.2V

VCC = 3.3V ± 0.3V

Symbol

CPD

Parameter

Test Conditions

Typical

Unit

PowerDissipationCapacitanceOutputsenabled

PowerDissipationCapacitanceOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

IDT74ALVCH16600

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.5V ± 0.2V

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

fMAX

tPLH

tPHL

tPLH

tPHL

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tSU

Parameter

Min.

150

Max.

—

Min.

150

—

Max.

—

Min.

150

Max.

—

Unit

MHz

PropagationDelay

5.1

4.7

Ax to Bx or Bx to Ax

PropagationDelay

5.9

7.3

6.5

5.1

—

5.5

6.8

6.3

4.7

4.8

5.7

5.2

4.4

LEAB to Bx or LEBA to Ax

PropagationDelay

1.3

1.1

1.2

CLKAB to Bx or CLKBA to Ax

OutputEnableTime

OEAB to Bx or OEBA to Ax

OutputDisableTime

OEAB to Bx or OEBA to Ax

Set-upTime,databeforeCLK↓

Set-up Time, data before LE↓, CLK HIGH

Set-upTime,databeforeLE↓, CLKLOW

Set-upTime,CLKENbeforeCLK

HoldTime,dataafterCLK

1.3

1.2

1.8

0.7

1.5

1.6

1.2

1.4

3.3

—

1.3

1.1

1.5

0.7

1.8

1.9

1.6

1.7

3.3

—

1.2

1.1

1.5

0.8

1.5

1.6

1.3

1.4

3.3

—

500

tSU

Hold Time, data after LE↓, CLK HIGH

Hold Time, data after LE↓, CLK LOW

Hold Time, CLKEN after CLK↓

Pulse Width, LEAB or LEBA HIGH

Pulse Width, CLKAB or CLKBA, HIGH or LOW

OutputSkew⁽²⁾

t^SK(o)

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

Skew between any two outputs of the same package and switching in the same direction.

IDT74ALVCH16600

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

VIH

SAME PHASE

INPUT TRANSITION

TESTCONDITIONS

tPHL

tPLH

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V

Unit

VOH

VOL

OUTPUT

VLOAD

VIH

2 x Vcc

Vcc

2.7

1.5

300

2.7

1.5

300

VIH

Vcc / 2

150

OPPOSITE PHASE

INPUT TRANSITION

VLZ

VHZ

150

ALVC Link

Propagation Delay

VLOAD

Open

GND

DISABLE

VCC

ENABLE

VIH

CONTROL

INPUT

500Ω

tPZL

tPLZ

VIN

VOUT

(1, 2)

Pulse

VLOAD/2

D.U.T.

VLOAD/2

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

Generator

V^LZ

VOL

500Ω

tPHZ

tPZH

OUTPUT

NORMALLY

HIGH

VOH

VHZ

SWITCH

OPEN

ALVC Link

Test Circuit for All Outputs

ALVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

VIH

1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

DATA

INPUT

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.

t^SU

VIH

TIMING

INPUT

SWITCHPOSITION

Test

Switch

V^LOAD

GND

tREM

ASYNCHRONOUS

CONTROL

Open Drain

Disable Low

Enable Low

SYNCHRONOUS

CONTROL

Disable High

Enable High

tSU

ALVC Link

All Other Tests

Open

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

VOL

LOW-HIGH-LOW

PULSE

OUTPUT 1

OUTPUT 2

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

ALVC Link

tPLH2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

tPHL2

Pulse Width

ALVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74ALVCH16600

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

Device Type Package

IDT

ALVC

XXX

Temp. Range

Bus-Hold

Family

Shrink Small Outline Package

Thin Shrink Small Outline Package

Thin Very Small Outline Package

600 18-Bit Universal Bus Transceiver with 3-State Outputs

Double-Density with Resistors, ±24mA

Bus-Hold

-40°C to +85°C

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

logichelp@idt.com

(408) 654-6459

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

IDT74ALVCH16600PV8 [IDT]

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