IDT74LVCR16501APA8 [IDT]
Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56;
| 型号： | IDT74LVCR16501APA8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 18-BIT
IDT74LVCR16501A
REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
FEATURES:
DESCRIPTION:
–
–
Typical tSK(0) (Output Skew) < 250ps
The LVCR16501A 18-bit registered transceiver is built using advanced
dual metal CMOS technology. This high-speed, low power, 18-bit regis-
teredbustransceivercombinesD-typelatchesandD-typeflip-flopstoallow
data flow in transparent, latched, and clocked modes. Data flow in each
direction is controlled by output-enable (OEAB and OEBA), latch enable
(LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data
flow, the device operates in transparent mode when LEAB is high. When
LEABislow,theAdataislatchedifCLKABisheldatahighorlowlogiclevel.
IfLEABislow,theAbusdataisstoredinthelatch/flip-floponthelow-to-high
transitionofCLKAB. OEABperformstheoutputenablefunctionontheBport.
DataflowfromBporttoAportissimilarbutrequiresusingOEBA,LEBAand
CLKBA. Flow-throughorganizationofsignalpinssimplifieslayout. Allinputs
are designed with hysteresis for improved noise margin.
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
Extended commercial range of -40°C to +85°C
VCC = 3.3V ±0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4µW typ. static)
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
–
–
–
–
–
–
–
Drive Features for LVCR16501A:
–
–
Balanced Output Drivers: ±12mA
Low switching noise
The LVCR16501A has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been developed to drive ±12mA at the designated thresholds.
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system
FUNCTIONAL BLOCK DIAGRAM
1
OEAB
30
CLKBA
28
LEBA
27
OEBA
CLKAB
2
L
C
C
D
54
3
B1
D
C
C
D
D
TO 17 OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OCTOBER 1999
1
c
1999 Integrated Device Technology, Inc.
DSC-4948/-
IDT74LVCR16501A
3.3VCMOS18-BITREGISTEREDTRANSCEIVERW/3-STATEOUTPUTS
EXTENDEDCOMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS (1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Max.
Unit
V
1
2
56
55
54
53
52
OEAB
LEAB
A1
GND
CLKAB
B1
Terminal Voltage with Respect to GND
Storage Temperature
– 0.5 to +6.5
– 65 to +150
°C
3
IOUT
DC Output Current
– 50 to +50
– 50
mA
mA
4
5
6
GND
A2
GND
IIK
IOK
ICC
Continuous Clamp Current,
VI < 0 or VO < 0
B2
B3
Continuous Current through
±100
mA
A3
VCC
A4
51
50
49
48
ISS
each VCC or GND
7
VCC
LVC Link
8
B4
B5
NOTE:
9
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
A5
10
47
46
45
44
B6
A6
11
12
13
14
15
GND
GND
A7
B7
B8
A8
A9
SO56-1
SO56-2 43
SO56-3
B9
42
B10
A10
A11
A12
CAPACITANCE (TA = +25oC, f = 1.0MHz)
16
17
18
41
B11
B12
40
39
38
Symbol
Parameter(1)
Conditions
Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
GND
B13
GND
A13
19
20
21
22
23
COUT
CI/O
Output
Capacitance
I/O Port
VOUT = 0V
VIN = 0V
6.5
8
pF
37
36
35
34
A14
B14
6.5
8
pF
B15
A15
Capacitance
VCC
A16
VCC
B16
LVC Link
NOTE:
1. As applicable to the device type.
24
25
26
27
33
32
B17
A17
GND
GND
31
30
29
B18
A18
FUNCTION TABLE (1, 2)
OEBA
LEBA
CLKBA
GND
28
Inputs
Outputs
OEAB
LEAB
CLKAB
Ax
X
L
Bx
L
X
H
H
L
X
X
X
↑
↑
L
Z
SSOP/ TSSOP/ TVSOP
TOP VIEW
H
L
H
H
H
L
H
L
H
L
H
X
X
H
PIN DESCRIPTION
H
H
L
B(3)
B(4)
Pin Names
Description
A-to-B Output Enable Input
L
H
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
NOTES:
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH Transition
2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,
LEBA, and CLKBA.
3. Output level before the indicated steady-state input conditions were
established.
4. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
Bx
c 1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVCR16501A
3.3VCMOS18-BITREGISTEREDTRANSCEIVERW/3-STATEOUTPUTS
EXTENDEDCOMMERCIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40OC to +85OC
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max. Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
—
—
—
V
2
—
—
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
—
—
—
0.7
0.8
±5
V
IIH
IIL
VI = 0 to 5.5V
µA
µA
IOZH
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
IOZL
IOFF
VIK
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
—
—
—
—
—
– 0.7
100
—
±50
– 1.2
—
µA
V
VH
Input Hysteresis
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
10
(2)
—
—
—
—
10
3.6 ≤ VIN ≤ 5.5V
∆ICC
Quiescent Power Supply
Current Variation
One input at VCC - 0.6V
other inputs at VCC or GND
500
µA
LVC Link
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Output HIGH Voltage
Test Conditions(1)
Min.
Max.
Unit
VOH
VCC = 2.3V to 3.6V
VCC = 2.3V
IOH = – 0.1mA
IOH = – 4mA
IOH = – 6mA
IOH = – 4mA
IOH = – 8mA
IOH = – 6mA
IOH = – 12mA
IOL = 0.1mA
IOL = 4mA
VCC – 0.2
—
—
V
1.9
1.7
2.2
2
—
VCC = 2.7V
VCC = 3.0V
—
—
2.4
2
—
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
IOL = 6mA
VCC = 2.7V
VCC = 3.0V
IOL = 4mA
IOL = 8mA
IOL = 6mA
IOL = 12mA
LVC Link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to +85°C.
3
IDT74LVCR16501A
3.3VCMOS18-BITREGISTEREDTRANSCEIVERW/3-STATEOUTPUTS
EXTENDEDCOMMERCIALTEMPERATURERANGE
OPERATING CHARACTERISTICS, V
= 3.3V ± 0.3V, T = 25°C
CC
A
Symbol
Parameter
Test Conditions
Typical
Unit
CPD
Power Dissipation Capacitance per transceiver Outputs enabled
Power Dissipation Capacitance per transceiver Outputs disabled
CL = 0pF, f = 10Mhz
pF
CPD
pF
SWITCHING CHARACTERISTICS (1)
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
tPHL
Propagation Delay
Ax to Bx or Bx to Ax
Propagation Delay
LEBA to Ax, LEAB to Bx
Propagation Delay
CLKBA to Ax, CLKAB to Bx
Output Enable Time
OEBA to Ax, OEAB to Bx
Output Disable Time
OEBA to Ax, OEAB to Bx
Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Hold Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
1.5
7
1.5
1.5
1.5
1.5
1.5
2.5
0
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPLH
tPHL
tPLH
tPHL
tPLH
tPZH
tPZL
tPHZ
tPLZ
tSU
1.5
1.5
1.5
1.5
2.5
0
8
7
6.7
7.2
7
8
8.2
8
—
—
—
—
—
—
—
—
tH
tSU
Set-up Time
HIGH or LOW
Ax to LEAB,
Bx to LEBA
Clock
LOW
Clock
HIGH
2.5
2.5
2.5
2.5
tH
Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA
LEAB or LEBA Pulse Width HIGH
CLKAB or CLKBA Pulse Width HIGH or LOW
Output Skew(2)
1.5
3
—
—
—
—
1.5
3
—
—
ns
ns
ns
ps
tW
tW
3
3
—
tSK(o)
—
—
500
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVCR16501A
3.3VCMOS18-BITREGISTEREDTRANSCEIVERW/3-STATEOUTPUTS
EXTENDEDCOMMERCIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS:
TESTCONDITIONS
PROPAGATIONDELAY
(1)
(1)
(2)
VCC = 3.3V ±0.3V VCC = 2.7V VCC = 2.5V ±0.2V
Symbol
Unit
VLOAD
6
6
2 x Vcc
Vcc
V
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
VIH
VT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
tPHL
tPHL
VCC / 2
150
V
tPLH
tPLH
VOH
VT
OUTPUT
VLZ
VHZ
CL
mV
mV
VOL
150
VIH
VT
30
pF
LVC Link
OPPOSITE PHASE
INPUT TRANSITION
0V
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
VLOAD
ENABLEANDDISABLETIMES
VCC
Open
GND
DISABLE
ENABLE
VIH
VT
500Ω
CONTROL
INPUT
VIN
VOUT
0V
Pulse (1, 2)
Generator
tPZL
tPLZ
D.U.T.
VLOAD/2
VT
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
500Ω
VOL+VLZ
VOL
RT
CL
tPHZ
tPZH
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
LVC Link
VT
0V
VOH-VHZ
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
0V
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
LVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCHPOSITION
SET-UP, HOLD, AND RELEASE TIMES
Test
Switch
VIH
VT
0V
DATA
INPUT
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
VLOAD
tSU
tH
VIH
VT
0V
TIMING
INPUT
GND
tREM
VIH
VT
0V
ASYNCHRONOUS
CONTROL
Open
LVC Link
VIH
VT
0V
SYNCHRONOUS
CONTROL
OUTPUT SKEW - tsk (x)
tSU
tH
LVC Link
VIH
VT
0V
INPUT
PULSEWIDTH
tPLH1
tPHL1
VOH
LOW-HIGH-LOW
PULSE
VT
VT
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
tSK (x)
tW
VOH
VT
HIGH-LOW-HIGH
PULSE
VT
VOL
LVC Link
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVCR16501A
3.3VCMOS18-BITREGISTEREDTRANSCEIVERW/3-STATEOUTPUTS
EXTENDEDCOMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
X
XX
XX
XXXX
IDT
XX
LVC
Bus-Hold
Family Device Type Package
Temp. Range
PV
PA
PF
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
18-bit Registered Transceiver with 3 State Outputs
501A
R16
Double-Density with Resistors, ±12mA
Blank
74
No Bus-hold
-40°C to +85°C
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6
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