IDTCV152PV [IDT]
Processor Specific Clock Generator, 400MHz, PDSO56, SSOP-56;
| 型号： | IDTCV152PV |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 400MHz, PDSO56, SSOP-56 光电二极管 |
| 文件： | 总15页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
IDTCV152
DESCRIPTION:
FEATURES:
IDTCV152 is a 56 pin clock device, compliant with Intel CK410B
specification.The CPU output buffer is designed to support up to 400MHz
processor. This chiphas three PLLs inside forCPU,SRC/PCI, and48MHz
IOclocks. ThisdevicealsoimplementsBand-gapreferencedIREF toreduce
theimpactofVDD variationondifferentialoutputs,whichcanprovidemorerobust
systemperformance. EachCPUandSRC/PCIhasitsownSpreadSpectrum
selection,whichallows forisolatedchanges insteadofaffecting otherclock
groups.
• One high precision PLL for CPU, SSC, and N programming
• One high precision PLL for SRC/PCI, SSC, and N programming
• One high precision PLL for 48MHz
• Band-gap circuit for differential outputs
• Support spread spectrum modulation, down spread 0.5% and
others
• Support SMBus block read/write, index read/write
• Selectable output strength for REF, 48MHz, PCI
• Allows for CPU frequency to change to a higher frequency for
maximum system computing power
• Available in SSOP and TSSOP packages
OUTPUTS:
KEYSPECIFICATION:
• CPU CLK cycle to cycle jitter < 85ps
• SRC CLK cycle to cycle jitter < 100ps
• PCI CLK cycle to cycle jitter < 250ps
• 5*0.7V current –mode differential CPU CLK pair
• 4*0.7V current –mode differential SRC CLK pair
• 7*PCI, 3 free running, 33.3MHz
• 1*48MHz
• 2*REF
FUNCTIONALBLOCKDIAGRAM
PLL1
SSC
N Programmable
CPU CLK
CPU[4:0]
Output Buffers
Stop Logic
XTAL_IN
XTAL
IREF
Osc Amp
REF[1:0]
XTAL_OUT
SDATA
SM Bus
Controller
SCLK
SRC CLK
Output Buffer
Stop Logic
SRC[4:1]
PLL2
SSC
N Programmable
PCI[3:0], PCIF[2:0]
IREF
VTT_PWRGD#/PD
Control
Logic
FSA.B.C
48MHz
Output BUffer
48MHz
PLL3
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
MAY 2005
1
© 2005 Integrated Device Technology, Inc.
DSC 6537/5
IDTCV152
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VDDA
Description
Min
Max
4.6
Unit
V
3.3V Core Supply Voltage
VDD_PCI
VSS_PCI
PCI0
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FSC/TEST_SEL
REF0
VDD
3.3V Logic Input Supply Voltage GND - 0.5
4.6
V
2
TSTG
Storage Temperature
–65
0
+150
+70
+115
° C
° C
° C
V
3
REF1
TAMBIENT
TCASE
Ambient Operating Temperature
Case Temperature
PCI1
4
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
FSB/TEST_MODE
FSA
PCI2
5
ESD Prot Input ESD Protection
Human Body Model
NOTE:
2000
6
PCI3
VSS_PCI
VDD_PCI
PCIF0
7
8
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
9
PCIF1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD_CPU
CPU0
PCIF2
VDD_48MHz
48MHz
CPU0#
VDD_CPU
CPU1
VSS_48MHz
VDD_SRC
NC
CPU1#
VSS_CPU
CPU2
CPU AND SRC SPREAD SPECTRUM
MAGNITUDECONTROL
VTT_PWRGD#/PWRDWN
SRC1#
CPU2#
VDD_CPU
CPU3
SRC1
SMC[2:0]
000
%
VSS_SRC
SRC2
-0.25
-0.5
001
CPU3#
VDDA
010
-0.75
- 1
SRC2#
011
SRC3#
VSSA
100
±0.125
±0.25
±0.375
±0.5
SRC3
IREF
101
VDD_SRC
SRC4
CPU4
110
CPU4#
SDA
111
SRC4#
VDD_SRC
SCL
SSOP/ TSSOP
TOP VIEW
FREQUENCYSELECTIONTABLE
FSC, B, A
CPU
SRC
100
100
100
100
100
100
100
100
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
USB
REF
101
100
48
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
001
133
48
011
166
48
010
200
48
000
266
48
100
333
48
110
400
48
111
Reserve
48
2
IDTCV152
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PINDESCRIPTION
Pin Name
XTAL_IN
Type
I
Pin #
52
Description
14.318XTALinput
14.318XTALoutput
14.318 MHz
XTAL_OUT
REF[1:0]
O
51
O
54,55
3, 4, 5, 6
9, 10, 11
13
PCI[3:0]
O
33.33MHz PCI CLK
PCIF[2:0]
O
33.33MHz PCI free running CLK
48MHz
USB48
O
CPU[4:0], CPU#[4:0]
O
31,32, 36, 37, 39,
40, 42, 43, 45, 46
CPU differential CLK
SRC[4:1], SRC#[4:1]
FSB/TEST_MODE
FSC/TEST_SEL
O
I
18, 19, 21-24, 26, 27
SRCdifferentialclk
49
56
Frequency select. When in test mode, 0 = CLK Hi-Z, 1 = CLK REF/N
I
Frequency select. Select test mode if pulled to 2V and above when VTT_PWRGND#
assertion.
FSA
IREF
I
I
I
48
33
17
Frequencyselect,sampledonVTT_PWRGND#assertion
Referencecurrentfordifferentialoutputs
VTT_PWRGND#/PD
3.3VLVTTLinput, alevel-sensitivestrobeusedtolatchtheFSA,FSB,FSC/TEST_SEL
inputs. AfterVTT_PWRGND#assertion,becomesareal-timeinputforassertingpowerdown
(active HIGH).
SDA
SCL
I/O
I
30
29
SMBus data
SMBus clock
3
IDTCV152
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
RESOLUTION
SESIGNALSTRENGTHSELECTION
CPU (MHz)
100
Resolution
0.666667
0.666667
1.333333
1.333333
1.333333
2.666667
2.666667
N =
150
200
125
150
200
125
150
Str[1:0]
00
Strength
0.6x
133
01
0.8x
166
10
1x
200
11
1.2x
266
333
400
INDEXBLOCKWRITEPROTOCOL
INDEXBLOCKREADPROTOCOL
Mastercanstopreadinganytimebyissuingthestopbitwithoutwaiting
untilNthbyte(bytecountbit30-37).
Bit
1
# of bits
From
Master
Master
Slave
Description
1
8
1
8
1
8
1
8
1
8
1
Start
D2h
2-9
Bit
1
# of bits
From
Master
Master
Slave
Description
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
1
8
1
8
1
1
8
1
8
Start
D2h
11-18
19
Master
Slave
2-9
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
RepeatedStart
20-27
28
Master
Slave
11-18
19
Master
Slave
29-36
37
Master
Slave
20
Master
Master
Slave
21-28
29
D3h
38-45
46
Master
Slave
Ack (Acknowledge)
Ack (Acknowledge)
:
30-37
Slave
Byte count, N (block read back of N
bytes), power on is 8
38
1
8
1
8
Master
Slave
Master
Slave
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
Master
Slave
Nthdatabyte
39-46
47
Acknowledge
Master
Stop
48-55
Ack (Acknowledge)
:
Master
Slave
Ack (Acknowledge)
Nthdatabyte
Notacknowledge
Stop
Master
INDEX BYTE WRITE
INDEX BYTE READ
Settingbit[11:18]=startingaddress,bit[20:27]=01h.
Settingbit[11:18]=startingaddress. Afterreadingbackthe firstdata byte,
masterissuesStopbit.
4
IDTCV152
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTE 0
Bit
0
Output(s)Affected
CPU[T/C]4
Description/Function
OutputEnable
0
1
Type
RW
RW
RW
RW
RW
Power On
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
1
SRCT1, SRCC1
SRCT2, SRCC2
SRCT3, SRCC3
SRCT4, SRCC4
Reserved
OutputEnable
2
OutputEnable
3
OutputEnable
4
OutputEnable
5
6
Reserved
7
Reserved
BYTE 1
Bit
0
Output(s)Affected
SpreadSpectrumEnable
CPUT0, CPUC0
CPUT1, CPUC1
Reserved
Description/Function
SpreadSpectrummodeEnable
OutputEnable
0
1
Type
RW
RW
RW
Power On
Spreadoff
Tristate
Tristate
Spreadon
Enable
Enable
0
1
1
1
1
1
1
1
1
2
OutputEnable
3
4
CPUT2, CPUC2
CPUT3, CPUC3
REF0
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
RW
RW
RW
RW
5
6
7
REF1
BYTE 2
Bit
0
Output(s)Affected
USB_48
PCIF0
Description/Function
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
1
2
PCIF1
3
PCIF2
4
PCI0
5
PCI1
6
PCI2
7
PCI3
BYTE 3
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
CPUCLK4
Allowcontrolledby
Freerunning
Stoppable
RW
0
SRC_STOP/CPU_Stop# assertion
1
2
3
4
5
6
7
SRCT1, SRCC1
SRCT2, SRCC2
SRCT3, SRCC3
SRCT4, SRCC4
PCIF0
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
Allowcontrolledby
Freerunning,not
Stoppedwith
PCI_STOP#
PCI_STOP# assertion
affected by PCI_STOP#
PCIF1
PCIF2
5
IDTCV152
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 4
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
CPUCLK0 Stop EN
CPUCLK1 Stop EN
CPUCLK2 Stop EN
CPUCLK3 Stop EN
CPUT0, CPUC0
CPUT1, CPUC1
CPUT2, CPUC2
CPUT3, CPUC3
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
0
0
0
0
Free-runningcontrol,
Free-running
Stoppable
Default:notaffectedbyCPU_STOP
CPU0 Pwrdwn drive mode
CPU1 Pwrdwn drive mode
CPU2 Pwrdwn drive mode
CPU3 Pwrdwn drive mode
Driven in power down
Tristatein
powerdown
BYTE 5
Bit
0
Output(s)Affected
CPUCLK0
CPUCLK1
CPUCLK2
CPUCLK3
CPUCLK4
SRC
Description / Function
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
0
0
0
0
0
0
0
0
1
2
Stop Drive - Drive mode in Stop
Driven
Tri-state
3
4
5
SRC Pwrdwn drive mode
PCI_STOP drive mode
CPU1 Pwrdwn drive mode
Driven in power down
Driven in PCI_Stop
Driven in power down
Tristateinpowerdown
Tristateinpowerdown
Tristateinpowerdown
6
SRC
7
CPUCLK4
BYTE 6
Bit
0
Output(s)Affected
Description / Function
FSA latched value on power up
FSB latched value on power up
FSC latched value on power up
0
1
Type
R
Power On
FSA
1
R
FSB
2
R
FSC
Stop all PCI/F & SRC
except PCIF[2:0] and SRC
clocks settofreerunning
3
4
5
6
7
Software PCI_STOP
function
No stop
Run
RW
RW
RW
RW
RW
1
1
1
0
0
REFstr1
REF drive strength , work with
byte12bit2,seestrengthtable
CPU
CPU_Stopcontrol
Stopnon-freerunning
CPU clocks
Test Modeentrycontrol
Normaloperation
Testmode,controlled
by byte 6 bit 7
Only valid when Byte6 bit6
is HIGH
Hi-Z
REF/N mode
6
IDTCV152
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTE 7
Bit
0
Output(s)Affected
Description / Function
VendorID
0
1
Type
R
Power On
1
0
1
0
0
0
0
0
1
VendorID
R
2
VendorID
R
3
VendorID
R
4
Revision ID
Revision ID
Revision ID
Revision ID
R
5
R
6
R
7
R
BYTE 8 (BLOCK READ BYTE COUNT)
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
0
1
1
1
0
0
0
0
BYTE 9
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
SRC SMC0
SRC SMC1
SRC SMC2
Reserved
SSC control
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
0
1
0
0
0
(see SMC table)
CPU SMC0
CPU SMC1
CPU SMC2
Reserved
SSC control
(see SMC table)
BYTE10
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
CPU_N0, LSB
CPU_N1
CPU CLK = N* Resolution
RW
RW
RW
RW
RW
RW
RW
RW
0
1
1
0
1
0
0
1
CPU_N2
CPU_N3
CPU_N4
CPU_N5
CPU_N6
CPU_N7, MSB
7
IDTCV152
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE11
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
SRC_N0, LSB
SRC_N1
CPU CLK = N* Resolution
RW
RW
RW
RW
RW
RW
RW
RW
0
1
1
0
1
0
0
1
SRC_N2
SRC_N3
SRC_N4
SRC_N5
SRC_N6
SRC_N7, MSB
BYTE12
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
48MHzStr0
48MHStr1
REFStr0
RW
RW
RW
1
1
1
USB48MHzstrengthselection
Work with Byte 6 Bit 4 REFstr1
(seestrengthtable)
3
4
5
6
7
Reserved
PCIStrC0
PCIStrC1
PCIFStr0
PCIFStr1
RW
RW
RW
RW
RW
0
0
1
0
1
PCIstrengthselection
PCIFstrengthselection
BYTE13
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
Test_scl
Onchiptestmodeenable
Normal
SCLK=1, CLK outputs=1
SCLK=0, CLK outputs=0
RW
0
1
2
3
4
5
6
7
NProgrammingenable
Disable
enable
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
Reserved
Reserved
USB PLL power down
SRC PLL power down
CPU PLL power down
Normal
Normal
Normal
Power down
Power down
Power down
Reserved
BYTE 62 DEVICE ID + REV
BIT[7:4] = 2h
BIT[3:0] = 0h
BYTE 63 = DEVICE ID
BIT[7:4] = 1h
BIT[3:0] = 5h
8
IDTCV152
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
VIH
Parameter
Input HIGH Voltage
Test Conditions
Min.
2
Typ.
—
Max.
Unit
V
3.3V ± 5%
3.3V ± 5%
VDD + 0.3
VIL
Input LOW Voltage
VSS - 0.3
0.7
—
0.8
V
VIH_FS
VIL_FS
IIL
LOW Voltage, HIGH Threshold
LOW Voltage, LOW Threshold
Input LeakageCurrent
For FSA.B.C test_mode
For FSA.B.C test_mode
0< VIN < VDD, no internal pull-up or pull-down
Full active, CL = full load
All differential pairs driven
All differential pairs tri-stated
VDD = 3.3V
—
VDD + 0.3
V
VSS - 0.3
–5
—
0.35
+5
400
70
12
—
7
V
—
mA
mA
mA
IDD3.3OP
IDD3.3PD
Operating Supply Current
Powerdown Current
—
—
—
—
—
—
(1)
FI
Input Frequency
—
14.31818
—
MHz
nH
LPIN
Pin Inductance(2)
—
CIN
Logic inputs
—
—
5
COUT
CINX
TSTAB
Input Capacitance(2)
Clock Stabilization(2,3)
Output pin capacitance
—
—
6
pF
XTAL_IN and XTAL_OUT pins
From VDD power-up or de-assertion of PD to first clock
Triangular modulation
—
—
5
—
—
1.8
33
300
5
ms
KHz
us
(2)
Modulation Frequency
30
—
(2)
TDRIVE_PD
CPU output enable after PD de-assertion
Fall time of PD
—
—
(2)
TFALL_PD
—
—
ns
(2)
TRISE_PD
Rise time of PD
—
—
5
ns
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
9
IDTCV152
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - CPU AND SRC 0.7 CURRENT MODE
DIFFERENTIALPAIR(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
ZO
Parameter
Test Conditions
Min.
3000
2.4
Typ.
—
—
—
—
—
—
—
—
—
Max.
—
Unit
Ω
Current Source Output Impedance(2) VO = VX
VOH3
VOL3
Output HIGH Voltage
Output LOW Voltage
IOH = -1mA
IOL = 1mA
—
V
—
0.4
V
(2)
VHIGH
VLOW
VOVS
Voltage HIGH
Statistical measurement on single-ended signal using
oscilloscope math function
660
–300
—
1150
150
1150
—
mV
(2)
Voltage LOW
Max Voltage(2)
Min Voltage(2)
Measurement on single-ended signal using absolute value
mV
VUDS
–300
250
—
VCROSS(ABS) Crossing Voltage (abs)(2)
550
140
mV
mV
ppm
d - VCROSS
ppm
Crossing Voltage (var)(2)
Static Error(2,3)
Variation of crossing over all edges
See TPERIOD Min. - Max. values
400MHz nominal / -0.5% spread
333.33MHz nominal / -0.5% spread
266.66MHz nominal / -0.5% spread
—
—
—
—
—
0
2.4993
2.9991
3.7489
2.5133
3.016
3.77
TPERIOD
Average Period(3)
200MHz nominal / -0.5% spread
4.9985
—
5.0266
ns
166.66MHz nominal / -0.5% spread
133.33MHz nominal / -0.5% spread
100MHz nominal / -0.5% spread
5.9982
7.4978
9.997
—
—
—
6.032
7.54
10.0533
96MHz nominal
10.4135
2.4143
2.9141
3.6639
—
—
—
—
10.4198
—
400MHz nominal / -0.5% spread
333.33MHz nominal / -0.5% spread
266.66MHz nominal / -0.5% spread
—
—
200MHz nominal / -0.5% spread
166.66MHz nominal / -0.5% spread
4.9135
5.9132
—
—
—
—
TABSMIN
Absolute Min Period(2,3)
ns
133.33MHz nominal / -0.5% spread
100MHz nominal / -0.5% spread
96MHz nominal
7.4128
9.912
10.1635
175
—
—
—
—
—
—
—
—
—
tR
tF
Rise Time(2)
VOL = 0.175V, VOH = 0.525V
VOL = 0.175V, VOH = 0.525V
700
700
125
ps
ps
ps
Fall Time(2)
175
d-tR
Rise Time Variation(2)
—
d-tF
dT3
Fall Time Variation(2)
Duty Cycle(2)
—
45
—
—
125
55
ps
%
Measurement from differential waveform
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
10
IDTCV152
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - CPU AND SRC 0.7 CURRENT MODE
DIFFERENTIALPAIR,CONTINUED(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
(2)
tSK3
Skew, CPU
VT = 50%
—
—
100
ps
Skew, SRC(2)
—
—
250
(2)
tJCYC-CYC
Jitter, Cycle to Cycle, CPU
Jitter, Cycle to Cycle, SRC(2)
Measurement from differential waveform
—
—
—
—
85
ps
125
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
33.33MHzoutputnominal
33.33MHzoutputspread
IOH = -1mA
Min.
—
Typ.
Max.
Unit
ppm
ns
(1,2)
ppm
StaticError
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
30.009
30.1598
—
TPERIOD
ClockPeriod(2)
29.991
29.991
2.4
—
VOH
VOL
IOH
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
V
IOL = 1mA
0.55
—
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
IOL
OutputLOWCurrent
30
—
mA
—
38
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
1
4
V/ns
V/ns
ns
Fallingedgerate
1
4
tR1
tF1
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.3
0.3
45
1.2
1.2
ns
dT1
Duty Cycle(1)
55
%
(1)
tSK1
Skew
VT = 1.5V
—
500
500
ps
tJCYC-CYC
Jitter, Cycle to Cycle(1)
VT = 1.5V
—
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
11
IDTCV152
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICALCHARACTERISTICS,48MHZ,USB
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
0
Unit
ppm
ns
(1,2)
ppm
StaticError
See Tperiod Min. - Max. values
48MHzoutputnominal
IOH = -1mA
TPERIOD
VOH
ClockPeriod(2)
20.8257
2.4
—
20.834
—
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
VOL
IOL = 1mA
0.55
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-29
—
mA
-23
—
IOL
OutputLOWCurrent
29
mA
—
27
EdgeRate(1)
1
2
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
2
tR1
tF1
RiseTime(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.5
0.5
45
1.2
1.2
55
FallTime(1)
ns
dT1
Duty Cycle(1)
%
tJCYC-CYC
Jitter, Cycle to Cycle
—
350
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICALCHARACTERISTICS-REF-14.318MHZ
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
14.318MHzoutputnominal
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
0
Unit
ppm
ns
(1)
ppm
LongAccuracy
TPERIOD
VOH
Clock Period
69.827
2.4
—
69.855
—
OutputHIGHVoltage(1)
OutputLOWVoltage(1)
Output HIGH Current
V
VOL
IOL = 1mA
0.4
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
—
IOL
OutputLOWCurrent
30
mA
—
38
EdgeRate(1)
1
4
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
4
tR1
tF1
Rise Time(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.3
0.3
45
1.2
1.2
55
Fall Time(1)
ns
dT1
Duty Cycle(1)
Jitter, Cycle to Cycle(1)
%
tJCYC-CYC
VT = 1.5V
—
1000
ps
NOTE:
1. This parameter is guaranteed by design, but not 100% production tested.
12
IDTCV152
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PCISTOPFUNCTIONALITY
If PCIF (2:0) and SRC clocks are set to be free-running through SMBus programming, they will ignore the PCI_STOP register bit.
PCI_STOP
CPU
CPU#
SRC
SRC#
PCIF/PCI
USB
DOT96
DOT96#
REF
(Byte 6 bit 3)
1
0
Normal
Normal
Normal
Normal
Normal
Normal
Low
33MHz
Low
48MHz
48MHz
Normal
Normal
Normal
Normal
14.318MHz
14.318MHz
IREF * 6 or float
PD, POWER DOWN
PDisanasynchronousactivehighinputusedtoshutoffallclockscleanlypriortoclockpower. WhenPDisassertedhighallclockswillbedrivenlowbefore
turningofftheVCO.InPDde-assertionallclockswillstartwithoutglitches.
PD
0
CPU
Normal
CPU#
Normal
Float
SRC
Normal
SRC#
Normal
Float
PCIF/PCI
33MHz
Low
USB
48MHz
Low
REF
14.318MHz
Low
1
IREF * 2 or float
IREF * 2 or float
PDASSERTION
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
13
IDTCV152
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PDDE-ASSERTION
Thetimefromthede-assertionofPDoruntilpowersupplyrampstogetstableclockswillbelessthan1.8ms.IfthedrivemodecontrolbitforPDtristateis
programmedto‘1’thestoppeddifferentialpairmustfirstbedrivenhightoaminimumof200mVinlessthan300µs ofPDdeassertion.
tSTABLE <1.8mS
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
tDRIVE_PD
<300μS, <200mV
14
IDTCV152
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ORDERINGINFORMATION
IDTCV XXX
Device Type
XX
Package
X
Grade
Blank Commercial Temperature Range
(0°C to +70°C)
Thin Small Shrink Outline Package
TSSOP - Green
Small Shrink Outline Package
PA
PAG
PV
SSOP - Green
PVG
Programmable FlexPC Clock for P4 Processor
152
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San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
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www.idt.com
for Tech Support:
logichelp@idt.com
15
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